TW200810372A - Transmitting/receiving methods and systems for DC balance encoded data including simultaneous switching noise reducing preambles - Google Patents

Transmitting/receiving methods and systems for DC balance encoded data including simultaneous switching noise reducing preambles Download PDF

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Publication number
TW200810372A
TW200810372A TW096111636A TW96111636A TW200810372A TW 200810372 A TW200810372 A TW 200810372A TW 096111636 A TW096111636 A TW 096111636A TW 96111636 A TW96111636 A TW 96111636A TW 200810372 A TW200810372 A TW 200810372A
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TW
Taiwan
Prior art keywords
data
preamble
bits
virtual
logical value
Prior art date
Application number
TW096111636A
Other languages
English (en)
Chinese (zh)
Inventor
Seung Jun Bae
Seong-Jin Jang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200810372A publication Critical patent/TW200810372A/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dram (AREA)
TW096111636A 2006-04-04 2007-04-02 Transmitting/receiving methods and systems for DC balance encoded data including simultaneous switching noise reducing preambles TW200810372A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060030752A KR100885869B1 (ko) 2006-04-04 2006-04-04 프리엠블 코드를 사용하여 노이즈를 감소시키는 단일형병렬데이터 인터페이스 방법, 기록매체 및 반도체 장치

Publications (1)

Publication Number Publication Date
TW200810372A true TW200810372A (en) 2008-02-16

Family

ID=38558042

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096111636A TW200810372A (en) 2006-04-04 2007-04-02 Transmitting/receiving methods and systems for DC balance encoded data including simultaneous switching noise reducing preambles

Country Status (5)

Country Link
US (4) US7492288B2 (enExample)
JP (2) JP5064867B2 (enExample)
KR (1) KR100885869B1 (enExample)
DE (1) DE102007016461B4 (enExample)
TW (1) TW200810372A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105794112A (zh) * 2013-12-27 2016-07-20 英特尔公司 高速短距离输入/输出(i/o)

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JP2006517767A (ja) * 2003-01-29 2006-07-27 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 一定全電流を用いるデータ通信
KR100885869B1 (ko) * 2006-04-04 2009-02-27 삼성전자주식회사 프리엠블 코드를 사용하여 노이즈를 감소시키는 단일형병렬데이터 인터페이스 방법, 기록매체 및 반도체 장치
US7936289B2 (en) * 2006-04-04 2011-05-03 Samsung Electronics Co., Ltd. Method, device, and system for data communication with preamble for reduced switching noise
JP5030698B2 (ja) * 2007-07-24 2012-09-19 株式会社リコー 半導体装置及びノイズ低減方法
JP5465376B2 (ja) * 2007-10-18 2014-04-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置、およびドライバ制御方法
JP5365132B2 (ja) * 2008-10-17 2013-12-11 富士ゼロックス株式会社 直列信号の受信装置、直列伝送システム、直列伝送方法、直列信号の送信装置
KR101653205B1 (ko) * 2010-04-01 2016-09-01 삼성전자주식회사 멀티 프리앰블 프레임 구조를 이용한 데이터 전송 시스템
WO2012170780A2 (en) * 2011-06-10 2012-12-13 Mayo Foundation For Medical Education And Research Zero sum signaling in a digital system environment
KR101960242B1 (ko) * 2012-09-18 2019-03-20 삼성전자주식회사 신체 영역 네트워크 또는 저전력 네트워크에서 직류 발란싱을 수행하는 최소 에너지 코딩 방법 및 장치
KR102509941B1 (ko) * 2016-10-06 2023-03-13 에스케이하이닉스 주식회사 송신 장치 및 이를 포함하는 시스템
JP2021044046A (ja) * 2019-09-13 2021-03-18 キオクシア株式会社 メモリシステム、半導体集積回路、及びブリッジ通信システム
GB2593691B (en) * 2020-03-30 2022-08-24 Imagination Tech Ltd Efficient encoding methods
US11756592B2 (en) 2020-09-29 2023-09-12 Samsung Electronics Co., Ltd. Memory device supporting DBI interface and operating method of memory device

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US5185717A (en) * 1988-08-05 1993-02-09 Ryoichi Mori Tamper resistant module having logical elements arranged in multiple layers on the outer surface of a substrate to protect stored information
US5387911A (en) * 1992-02-21 1995-02-07 Gleichert; Marc C. Method and apparatus for transmitting and receiving both 8B/10B code and 10B/12B code in a switchable 8B/10B transmitter and receiver
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KR100667594B1 (ko) * 2004-10-19 2007-01-11 삼성전자주식회사 프리엠퍼시스 출력버퍼와, 반도체 메모리 장치 및 데이터출력구동방법.
JP4620504B2 (ja) * 2005-03-10 2011-01-26 富士通セミコンダクター株式会社 半導体メモリおよびシステム装置
KR100885869B1 (ko) * 2006-04-04 2009-02-27 삼성전자주식회사 프리엠블 코드를 사용하여 노이즈를 감소시키는 단일형병렬데이터 인터페이스 방법, 기록매체 및 반도체 장치

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105794112A (zh) * 2013-12-27 2016-07-20 英特尔公司 高速短距离输入/输出(i/o)
US10396840B2 (en) 2013-12-27 2019-08-27 Intel Corporation High speed short reach input/output (I/O)
CN105794112B (zh) * 2013-12-27 2019-11-15 英特尔公司 高速短距离输入/输出(i/o)

Also Published As

Publication number Publication date
US20090146850A1 (en) 2009-06-11
US20070229320A1 (en) 2007-10-04
US7961121B2 (en) 2011-06-14
DE102007016461A1 (de) 2007-11-29
KR100885869B1 (ko) 2009-02-27
US7768429B2 (en) 2010-08-03
US20100259426A1 (en) 2010-10-14
US7492288B2 (en) 2009-02-17
US20110249513A1 (en) 2011-10-13
JP2007282235A (ja) 2007-10-25
JP2010172002A (ja) 2010-08-05
KR20070099374A (ko) 2007-10-09
JP5064867B2 (ja) 2012-10-31
DE102007016461B4 (de) 2012-03-08

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