TW200746318A - Fabrication of three dimensional integrated circuit employing multiple die panels - Google Patents

Fabrication of three dimensional integrated circuit employing multiple die panels

Info

Publication number
TW200746318A
TW200746318A TW095125134A TW95125134A TW200746318A TW 200746318 A TW200746318 A TW 200746318A TW 095125134 A TW095125134 A TW 095125134A TW 95125134 A TW95125134 A TW 95125134A TW 200746318 A TW200746318 A TW 200746318A
Authority
TW
Taiwan
Prior art keywords
panel
die
panels
wafer
fabrication
Prior art date
Application number
TW095125134A
Other languages
English (en)
Other versions
TWI397132B (zh
Inventor
Robert E Jones
Scott K Pozder
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200746318A publication Critical patent/TW200746318A/zh
Application granted granted Critical
Publication of TWI397132B publication Critical patent/TWI397132B/zh

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1062—Prior to assembly
TW095125134A 2005-07-29 2006-07-10 使用多晶粒面板之三維積體電路之製造 TWI397132B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/193,926 US7622313B2 (en) 2005-07-29 2005-07-29 Fabrication of three dimensional integrated circuit employing multiple die panels

Publications (2)

Publication Number Publication Date
TW200746318A true TW200746318A (en) 2007-12-16
TWI397132B TWI397132B (zh) 2013-05-21

Family

ID=37693001

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125134A TWI397132B (zh) 2005-07-29 2006-07-10 使用多晶粒面板之三維積體電路之製造

Country Status (5)

Country Link
US (1) US7622313B2 (zh)
JP (1) JP2009503846A (zh)
CN (1) CN100587913C (zh)
TW (1) TWI397132B (zh)
WO (1) WO2007018850A2 (zh)

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US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7425499B2 (en) * 2004-08-24 2008-09-16 Micron Technology, Inc. Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
SG120200A1 (en) * 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7622377B2 (en) * 2005-09-01 2009-11-24 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
US7737003B2 (en) * 2005-10-11 2010-06-15 International Business Machines Corporation Method and structure for optimizing yield of 3-D chip manufacture
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7494846B2 (en) * 2007-03-09 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Design techniques for stacking identical memory dies
SG149710A1 (en) 2007-07-12 2009-02-27 Micron Technology Inc Interconnects for packaged semiconductor devices and methods for manufacturing such devices
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US8796073B2 (en) 2008-09-24 2014-08-05 Qualcomm Incorporated Low cost die-to-wafer alignment/bond for 3d IC stacking
US20110300669A1 (en) * 2010-06-07 2011-12-08 Chi-Chih Shen Method for Making Die Assemblies
JPWO2012169168A1 (ja) 2011-06-09 2015-02-23 パナソニック株式会社 三次元集積回路、及びそのテスト方法
CN103714188B (zh) * 2012-09-28 2018-03-23 恩智浦美国有限公司 用于优化在晶片上制造的管芯数目的系统
KR20140099604A (ko) 2013-02-04 2014-08-13 삼성전자주식회사 적층 패키지 및 적층 패키지의 제조 방법
US9250288B2 (en) * 2013-09-05 2016-02-02 Powertech Technology Inc. Wafer-level testing method for singulated 3D-stacked chip cubes
CN105023877B (zh) 2014-04-28 2019-12-24 联华电子股份有限公司 半导体晶片、封装结构与其制作方法
KR101544319B1 (ko) 2014-06-24 2015-08-12 성균관대학교산학협력단 3차원 반도체의 제조방법
US10707138B1 (en) * 2017-03-29 2020-07-07 Xilinx, Inc. High yield package assembly technique
CN112563250B (zh) * 2020-11-29 2022-07-22 中国电子科技集团公司第五十五研究所 一种多颗芯片同时制备封装使用的方法

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Also Published As

Publication number Publication date
WO2007018850A3 (en) 2008-01-03
CN101258583A (zh) 2008-09-03
US20070023121A1 (en) 2007-02-01
US7622313B2 (en) 2009-11-24
CN100587913C (zh) 2010-02-03
JP2009503846A (ja) 2009-01-29
TWI397132B (zh) 2013-05-21
WO2007018850A2 (en) 2007-02-15

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