TW200745854A - Self prefetching L2 cache mechanism for data lines - Google Patents

Self prefetching L2 cache mechanism for data lines

Info

Publication number
TW200745854A
TW200745854A TW096103718A TW96103718A TW200745854A TW 200745854 A TW200745854 A TW 200745854A TW 096103718 A TW096103718 A TW 096103718A TW 96103718 A TW96103718 A TW 96103718A TW 200745854 A TW200745854 A TW 200745854A
Authority
TW
Taiwan
Prior art keywords
instruction
prefetching
line
data lines
cache mechanism
Prior art date
Application number
TW096103718A
Other languages
English (en)
Inventor
David A Luick
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200745854A publication Critical patent/TW200745854A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
TW096103718A 2006-02-03 2007-02-01 Self prefetching L2 cache mechanism for data lines TW200745854A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/347,414 US20070186050A1 (en) 2006-02-03 2006-02-03 Self prefetching L2 cache mechanism for data lines

Publications (1)

Publication Number Publication Date
TW200745854A true TW200745854A (en) 2007-12-16

Family

ID=38335339

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096103718A TW200745854A (en) 2006-02-03 2007-02-01 Self prefetching L2 cache mechanism for data lines

Country Status (4)

Country Link
US (1) US20070186050A1 (zh)
JP (1) JP5084280B2 (zh)
CN (1) CN101013401A (zh)
TW (1) TW200745854A (zh)

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CN102831078B (zh) * 2012-08-03 2015-08-26 中国人民解放军国防科学技术大学 一种cache中提前返回访存数据的方法
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KR102083390B1 (ko) 2013-03-15 2020-03-02 인텔 코포레이션 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US10140138B2 (en) * 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9658963B2 (en) * 2014-12-23 2017-05-23 Intel Corporation Speculative reads in buffered memory
US10666774B2 (en) * 2016-03-16 2020-05-26 International Business Machines Corporation Message processing
US10346943B2 (en) * 2017-01-03 2019-07-09 Microsoft Technology Licensing, Llc Prefetching for a graphics shader
CN107273098B (zh) * 2017-05-03 2020-07-31 北京中科睿芯科技有限公司 一种优化数据流架构数据传输延迟的方法及其系统
KR102606009B1 (ko) * 2018-08-16 2023-11-27 에스케이하이닉스 주식회사 캐시 버퍼 및 이를 포함하는 반도체 메모리 장치
US11314644B2 (en) 2019-05-24 2022-04-26 Texas Instruments Incorporated Cache size change
CN111399913B (zh) * 2020-06-05 2020-09-01 浙江大学 一种基于预取的处理器加速取指方法
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Also Published As

Publication number Publication date
CN101013401A (zh) 2007-08-08
JP2007207240A (ja) 2007-08-16
JP5084280B2 (ja) 2012-11-28
US20070186050A1 (en) 2007-08-09

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