TW200743140A - Method for fabricating fine pattern in semiconductor device - Google Patents

Method for fabricating fine pattern in semiconductor device

Info

Publication number
TW200743140A
TW200743140A TW096115015A TW96115015A TW200743140A TW 200743140 A TW200743140 A TW 200743140A TW 096115015 A TW096115015 A TW 096115015A TW 96115015 A TW96115015 A TW 96115015A TW 200743140 A TW200743140 A TW 200743140A
Authority
TW
Taiwan
Prior art keywords
polymer layer
semiconductor device
fine pattern
patterned
layer
Prior art date
Application number
TW096115015A
Other languages
English (en)
Other versions
TWI374477B (en
Inventor
Sung-Kwon Lee
Seung-Chan Moon
Won-Kyu Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200743140A publication Critical patent/TW200743140A/zh
Application granted granted Critical
Publication of TWI374477B publication Critical patent/TWI374477B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer
    • Y10T428/2813—Heat or solvent activated or sealable
    • Y10T428/2817—Heat sealable
    • Y10T428/2826—Synthetic resin or polymer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)
TW096115015A 2006-05-02 2007-04-27 Method for fabricating fine pattern in semiconductor device TWI374477B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060039708A KR100875660B1 (ko) 2006-05-02 2006-05-02 반도체 소자의 미세 패턴 형성 방법

Publications (2)

Publication Number Publication Date
TW200743140A true TW200743140A (en) 2007-11-16
TWI374477B TWI374477B (en) 2012-10-11

Family

ID=38661711

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096115015A TWI374477B (en) 2006-05-02 2007-04-27 Method for fabricating fine pattern in semiconductor device

Country Status (5)

Country Link
US (1) US7494599B2 (zh)
JP (1) JP5100198B2 (zh)
KR (1) KR100875660B1 (zh)
CN (1) CN100550297C (zh)
TW (1) TWI374477B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7718546B2 (en) * 2007-06-27 2010-05-18 Sandisk 3D Llc Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon
US8227176B2 (en) 2007-11-02 2012-07-24 Hynix Semiconductor Inc. Method for forming fine pattern in semiconductor device
KR100965774B1 (ko) * 2007-11-02 2010-06-24 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
KR101342038B1 (ko) * 2011-08-10 2013-12-16 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
CN103985629B (zh) * 2014-05-21 2017-07-11 上海华力微电子有限公司 自对准双层图形半导体结构的制作方法
KR101926023B1 (ko) * 2015-10-23 2018-12-06 삼성에스디아이 주식회사 막 구조물 제조 방법 및 패턴형성방법
US11437238B2 (en) * 2018-07-09 2022-09-06 Applied Materials, Inc. Patterning scheme to improve EUV resist and hard mask selectivity
US11276579B2 (en) * 2018-11-14 2022-03-15 Hitachi High-Tech Corporation Substrate processing method and plasma processing apparatus
CN112928070B (zh) * 2021-03-19 2023-06-06 长鑫存储技术有限公司 存储器的制作方法及存储器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2720404B2 (ja) * 1989-05-02 1998-03-04 富士通株式会社 エッチング方法
JPH0677176A (ja) * 1992-08-25 1994-03-18 Mitsubishi Electric Corp 珪素樹脂のパターン形成方法
US6475904B2 (en) * 1998-12-03 2002-11-05 Advanced Micro Devices, Inc. Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques
US6573030B1 (en) * 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
JP3971088B2 (ja) * 2000-06-30 2007-09-05 株式会社東芝 パターン形成方法
JP2004214465A (ja) * 2003-01-07 2004-07-29 Renesas Technology Corp 半導体装置の製造方法
US20040229159A1 (en) * 2003-02-23 2004-11-18 Subbareddy Kanagasabapathy Fluorinated Si-polymers and photoresists comprising same
KR100510558B1 (ko) 2003-12-13 2005-08-26 삼성전자주식회사 패턴 형성 방법
KR20060019668A (ko) 2004-08-28 2006-03-06 엘지전자 주식회사 2층 하드마스크를 이용한 실리콘온인슐레이터 웨이퍼의식각방법
US7067435B2 (en) * 2004-09-29 2006-06-27 Texas Instruments Incorporated Method for etch-stop layer etching during damascene dielectric etching with low polymerization

Also Published As

Publication number Publication date
JP2007300125A (ja) 2007-11-15
US20070259524A1 (en) 2007-11-08
CN101067999A (zh) 2007-11-07
KR100875660B1 (ko) 2008-12-26
TWI374477B (en) 2012-10-11
CN100550297C (zh) 2009-10-14
JP5100198B2 (ja) 2012-12-19
US7494599B2 (en) 2009-02-24
KR20070107345A (ko) 2007-11-07

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees