TW200713464A - Selective deposition of germanium spacers on nitride - Google Patents
Selective deposition of germanium spacers on nitrideInfo
- Publication number
- TW200713464A TW200713464A TW095100790A TW95100790A TW200713464A TW 200713464 A TW200713464 A TW 200713464A TW 095100790 A TW095100790 A TW 095100790A TW 95100790 A TW95100790 A TW 95100790A TW 200713464 A TW200713464 A TW 200713464A
- Authority
- TW
- Taiwan
- Prior art keywords
- nitride
- germanium
- selective deposition
- oxide
- spacers
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
- H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3451—Structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/281—Auxiliary members
- H10W72/283—Reinforcing structures, e.g. bump collars
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/905,587 US7705385B2 (en) | 2005-09-12 | 2005-09-12 | Selective deposition of germanium spacers on nitride |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200713464A true TW200713464A (en) | 2007-04-01 |
Family
ID=37855727
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095100790A TW200713464A (en) | 2005-09-12 | 2006-01-09 | Selective deposition of germanium spacers on nitride |
| TW102132073A TWI496221B (zh) | 2005-09-12 | 2006-01-09 | 半導體結構與鍺結構 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102132073A TWI496221B (zh) | 2005-09-12 | 2006-01-09 | 半導體結構與鍺結構 |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US7705385B2 (https=) |
| JP (2) | JP5270067B2 (https=) |
| CN (1) | CN100570884C (https=) |
| TW (2) | TW200713464A (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687804B2 (en) * | 2008-01-08 | 2010-03-30 | International Business Machines Corporation | Method for fabricating a semiconductor structures and structures thereof |
| US8580646B2 (en) * | 2010-11-18 | 2013-11-12 | International Business Machines Corporation | Method of fabricating field effect transistors with low k sidewall spacers |
| KR20160053001A (ko) * | 2014-10-30 | 2016-05-13 | 삼성디스플레이 주식회사 | 투명 표시 기판, 투명 표시 장치 및 투명 표시 장치의 제조 방법 |
| US10037923B1 (en) * | 2017-04-19 | 2018-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming transistor by selectively growing gate spacer |
| CN109309006B (zh) * | 2017-07-27 | 2021-10-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| JP7221187B2 (ja) * | 2019-09-30 | 2023-02-13 | 東京エレクトロン株式会社 | 成膜方法、及び成膜装置 |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5624925A (en) * | 1979-08-08 | 1981-03-10 | Hitachi Ltd | Selective growth of silicon |
| JPS5854684A (ja) | 1981-09-08 | 1983-03-31 | テキサス・インスツルメンツ・インコ−ポレイテツド | 太陽エネルギ−変換装置 |
| JPS63239934A (ja) * | 1987-03-27 | 1988-10-05 | Canon Inc | 半導体基材の製造方法 |
| JPH01157517A (ja) * | 1987-08-24 | 1989-06-20 | Canon Inc | 結晶の形成方法 |
| US5066616A (en) * | 1989-06-14 | 1991-11-19 | Hewlett-Packard Company | Method for improving photoresist on wafers by applying fluid layer of liquid solvent |
| US5153145A (en) * | 1989-10-17 | 1992-10-06 | At&T Bell Laboratories | Fet with gate spacer |
| US5202284A (en) * | 1989-12-01 | 1993-04-13 | Hewlett-Packard Company | Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2 |
| TW203148B (https=) * | 1991-03-27 | 1993-04-01 | American Telephone & Telegraph | |
| US5282925A (en) * | 1992-11-09 | 1994-02-01 | International Business Machines Corporation | Device and method for accurate etching and removal of thin film |
| US5721443A (en) * | 1995-07-13 | 1998-02-24 | Micron Technology, Inc. | NMOS field effect transistors and methods of forming NMOS field effect transistors |
| US5723352A (en) * | 1995-08-03 | 1998-03-03 | Taiwan Semiconductor Manufacturing Company | Process to optimize performance and reliability of MOSFET devices |
| US5719424A (en) * | 1995-10-05 | 1998-02-17 | Micron Technology, Inc. | Graded LDD implant process for sub-half-micron MOS devices |
| US6027957A (en) * | 1996-06-27 | 2000-02-22 | University Of Maryland | Controlled solder interdiffusion for high power semiconductor laser diode die bonding |
| US6074951A (en) * | 1997-05-29 | 2000-06-13 | International Business Machines Corporation | Vapor phase etching of oxide masked by resist or masking material |
| US6242785B1 (en) * | 1999-01-26 | 2001-06-05 | Advanced Micro Devices, Inc. | Nitride based sidewall spaces for submicron MOSFETs |
| US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
| US6617226B1 (en) * | 1999-06-30 | 2003-09-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US6570251B1 (en) * | 1999-09-02 | 2003-05-27 | Micron Technology, Inc. | Under bump metalization pad and solder bump connections |
| KR100431295B1 (ko) * | 2001-10-12 | 2004-05-12 | 주식회사 하이닉스반도체 | 반도체소자의 플러그 형성방법 |
| KR100406537B1 (ko) * | 2001-12-03 | 2003-11-20 | 주식회사 하이닉스반도체 | 반도체장치의 제조 방법 |
| US6617619B1 (en) * | 2002-02-04 | 2003-09-09 | Newport Fab, Llc | Structure for a selective epitaxial HBT emitter |
| KR100510518B1 (ko) * | 2003-01-30 | 2005-08-26 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 패키지 방법 |
| TWI225899B (en) * | 2003-02-18 | 2005-01-01 | Unitive Semiconductor Taiwan C | Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer |
| WO2004095559A1 (ja) * | 2003-04-22 | 2004-11-04 | Tokyo Electron Limited | シリコン酸化膜の除去方法及び処理装置 |
| KR100539278B1 (ko) * | 2003-09-22 | 2005-12-27 | 삼성전자주식회사 | 코발트 실리사이드막 형성 방법 및 반도체 장치의 제조방법. |
| US7247569B2 (en) * | 2003-12-02 | 2007-07-24 | International Business Machines Corporation | Ultra-thin Si MOSFET device structure and method of manufacture |
| JP4143584B2 (ja) * | 2004-09-01 | 2008-09-03 | 株式会社東芝 | 半導体装置の製造方法 |
| US7338894B2 (en) * | 2005-01-26 | 2008-03-04 | Freescale Semiconductor, Inc. | Semiconductor device having nitridated oxide layer and method therefor |
| US20070039924A1 (en) * | 2005-08-18 | 2007-02-22 | Tokyo Electron Limited | Low-temperature oxide removal using fluorine |
-
2005
- 2005-09-12 US US10/905,587 patent/US7705385B2/en not_active Expired - Fee Related
-
2006
- 2006-01-06 JP JP2006001706A patent/JP5270067B2/ja not_active Expired - Fee Related
- 2006-01-09 TW TW095100790A patent/TW200713464A/zh unknown
- 2006-01-09 TW TW102132073A patent/TWI496221B/zh not_active IP Right Cessation
- 2006-01-12 CN CNB2006100012856A patent/CN100570884C/zh not_active Expired - Fee Related
-
2008
- 2008-06-09 US US12/135,245 patent/US7888241B2/en not_active Expired - Fee Related
-
2010
- 2010-10-19 US US12/907,186 patent/US8900961B2/en not_active Expired - Fee Related
-
2011
- 2011-10-21 JP JP2011231718A patent/JP5388312B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20080242041A1 (en) | 2008-10-02 |
| JP2012069964A (ja) | 2012-04-05 |
| US7705385B2 (en) | 2010-04-27 |
| JP5270067B2 (ja) | 2013-08-21 |
| TWI496221B (zh) | 2015-08-11 |
| US8900961B2 (en) | 2014-12-02 |
| CN100570884C (zh) | 2009-12-16 |
| CN1933175A (zh) | 2007-03-21 |
| US20070059894A1 (en) | 2007-03-15 |
| US20110034000A1 (en) | 2011-02-10 |
| JP2007081361A (ja) | 2007-03-29 |
| JP5388312B2 (ja) | 2014-01-15 |
| US7888241B2 (en) | 2011-02-15 |
| TW201403719A (zh) | 2014-01-16 |
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