TW200711081A - A method of manufacturing a semiconductor packages and packages made - Google Patents

A method of manufacturing a semiconductor packages and packages made

Info

Publication number
TW200711081A
TW200711081A TW095106862A TW95106862A TW200711081A TW 200711081 A TW200711081 A TW 200711081A TW 095106862 A TW095106862 A TW 095106862A TW 95106862 A TW95106862 A TW 95106862A TW 200711081 A TW200711081 A TW 200711081A
Authority
TW
Taiwan
Prior art keywords
resin layer
packages
manufacturing
interconnect structure
contact means
Prior art date
Application number
TW095106862A
Other languages
English (en)
Chinese (zh)
Inventor
Veen Nicolaas Johannes Anthonius Van
Ronald Dekker
Coen C Tak
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW200711081A publication Critical patent/TW200711081A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H10P72/7418—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. a chip mounting substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW095106862A 2005-03-02 2006-03-01 A method of manufacturing a semiconductor packages and packages made TW200711081A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05101593 2005-03-02

Publications (1)

Publication Number Publication Date
TW200711081A true TW200711081A (en) 2007-03-16

Family

ID=36577514

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095106862A TW200711081A (en) 2005-03-02 2006-03-01 A method of manufacturing a semiconductor packages and packages made

Country Status (8)

Country Link
US (1) US20080150118A1 (https=)
EP (1) EP1856728B1 (https=)
JP (1) JP2008532307A (https=)
CN (1) CN100514591C (https=)
AT (1) ATE412251T1 (https=)
DE (1) DE602006003316D1 (https=)
TW (1) TW200711081A (https=)
WO (1) WO2006092754A2 (https=)

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CN100550367C (zh) * 2005-07-01 2009-10-14 皇家飞利浦电子股份有限公司 电子器件
CN100592513C (zh) * 2005-11-11 2010-02-24 皇家飞利浦电子股份有限公司 芯片组件和制造芯片组件的方法
JP4956128B2 (ja) * 2006-10-02 2012-06-20 ルネサスエレクトロニクス株式会社 電子装置の製造方法
US8093689B2 (en) * 2007-07-02 2012-01-10 Infineon Technologies Ag Attachment member for semiconductor sensor device
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
TW201114003A (en) * 2008-12-11 2011-04-16 Xintec Inc Chip package structure and method for fabricating the same
US8072041B2 (en) * 2009-04-08 2011-12-06 Finisar Corporation Passivated optical detectors with full protection layer
CN104597651B (zh) 2009-05-02 2017-12-05 株式会社半导体能源研究所 显示设备
US8212340B2 (en) * 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
JP5521862B2 (ja) * 2010-07-29 2014-06-18 三菱電機株式会社 半導体装置の製造方法
US10446442B2 (en) * 2016-12-21 2019-10-15 Globalfoundries Inc. Integrated circuit chip with molding compound handler substrate and method
KR20180136148A (ko) * 2017-06-14 2018-12-24 에스케이하이닉스 주식회사 범프를 구비하는 반도체 장치
DE102019100130B4 (de) * 2018-04-10 2021-11-04 Infineon Technologies Ag Ein halbleiterbauelement und ein verfahren zum bilden eines halbleiterbauelements
KR102435517B1 (ko) * 2018-04-12 2022-08-22 에스케이하이닉스 주식회사 칩 스택 패키지
KR102545168B1 (ko) * 2019-03-26 2023-06-19 삼성전자주식회사 인터포저 및 이를 포함하는 반도체 패키지

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2599893B1 (fr) * 1986-05-23 1996-08-02 Ricoh Kk Procede de montage d'un module electronique sur un substrat et carte a circuit integre
US5386623A (en) * 1990-11-15 1995-02-07 Hitachi, Ltd. Process for manufacturing a multi-chip module
US5336928A (en) * 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
EP1041624A1 (en) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
US6242282B1 (en) * 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6734534B1 (en) * 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US6720270B1 (en) * 2000-09-13 2004-04-13 Siliconware Precision Industries Co., Ltd. Method for reducing size of semiconductor unit in packaging process
US6586276B2 (en) * 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
JP4100936B2 (ja) * 2002-03-01 2008-06-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
WO2005117096A1 (ja) * 2004-05-31 2005-12-08 Sharp Takaya Electronics Industry Co., Ltd. 回路モジュールの製造方法、及びその方法により製造された回路モジュール

Also Published As

Publication number Publication date
US20080150118A1 (en) 2008-06-26
JP2008532307A (ja) 2008-08-14
CN100514591C (zh) 2009-07-15
WO2006092754A3 (en) 2007-01-18
CN101133484A (zh) 2008-02-27
DE602006003316D1 (de) 2008-12-04
EP1856728A2 (en) 2007-11-21
ATE412251T1 (de) 2008-11-15
WO2006092754A2 (en) 2006-09-08
EP1856728B1 (en) 2008-10-22

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