TW200701225A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
TW200701225A
TW200701225A TW095108542A TW95108542A TW200701225A TW 200701225 A TW200701225 A TW 200701225A TW 095108542 A TW095108542 A TW 095108542A TW 95108542 A TW95108542 A TW 95108542A TW 200701225 A TW200701225 A TW 200701225A
Authority
TW
Taiwan
Prior art keywords
level
memory device
semiconductor memory
reset
designated
Prior art date
Application number
TW095108542A
Other languages
English (en)
Inventor
Masaki Tsukude
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200701225A publication Critical patent/TW200701225A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
TW095108542A 2005-03-15 2006-03-14 Semiconductor memory device TW200701225A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005072314 2005-03-15
JP2006036729A JP2006294216A (ja) 2005-03-15 2006-02-14 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW200701225A true TW200701225A (en) 2007-01-01

Family

ID=37010129

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095108542A TW200701225A (en) 2005-03-15 2006-03-14 Semiconductor memory device

Country Status (4)

Country Link
US (2) US7301843B2 (zh)
JP (1) JP2006294216A (zh)
KR (1) KR20060100227A (zh)
TW (1) TW200701225A (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100834403B1 (ko) * 2007-01-03 2008-06-04 주식회사 하이닉스반도체 안정적인 셀프리프레쉬 동작을 수행하는 메모리장치 및셀프리프레쉬주기 제어신호 생성방법
JP4497184B2 (ja) * 2007-09-13 2010-07-07 ソニー株式会社 集積装置およびそのレイアウト方法、並びにプログラム
US20130002343A1 (en) * 2011-06-29 2013-01-03 Synopsys Inc. High voltage regulation in charge pumps
US8588022B2 (en) 2011-08-24 2013-11-19 Micron Technology, Inc. Memory refresh methods, memory section control circuits, and apparatuses
US8611169B2 (en) 2011-12-09 2013-12-17 International Business Machines Corporation Fine granularity power gating
US9183906B2 (en) 2012-10-02 2015-11-10 International Business Machines Corporation Fine granularity power gating
US9183917B1 (en) 2012-12-21 2015-11-10 Samsung Electronics Co., Ltd. Memory device, operating method thereof, and system having the memory device
KR20170008083A (ko) * 2015-07-13 2017-01-23 에스케이하이닉스 주식회사 리프레쉬 검증 회로, 반도체 장치 및 반도체 시스템
US9437284B1 (en) * 2015-12-02 2016-09-06 Vanguard International Semiconductor Corporation Memory devices and control methods thereof
US10068636B2 (en) * 2016-12-30 2018-09-04 Intel Corporation Apparatuses and methods for accessing and scheduling between a plurality of row buffers
JP6429260B1 (ja) * 2017-11-09 2018-11-28 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリおよびそのリフレッシュ方法
KR102225114B1 (ko) * 2019-06-18 2021-03-09 윈본드 일렉트로닉스 코포레이션 의사 스태틱 랜덤 액세스 메모리 및 그 데이터 기입 방법
DE102021205318A1 (de) * 2021-05-26 2022-12-01 Robert Bosch Gesellschaft mit beschränkter Haftung Speichervorrichtung und Verfahren zur Durchführung aufeinanderfolgender Speicherzugriffe

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3752288B2 (ja) 1995-12-11 2006-03-08 株式会社ルネサステクノロジ 半導体記憶装置
US5835401A (en) * 1996-12-05 1998-11-10 Cypress Semiconductor Corporation Dram with hidden refresh
US6005818A (en) * 1998-01-20 1999-12-21 Stmicroelectronics, Inc. Dynamic random access memory device with a latching mechanism that permits hidden refresh operations
JP4743999B2 (ja) 2001-05-28 2011-08-10 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6757784B2 (en) * 2001-09-28 2004-06-29 Intel Corporation Hiding refresh of memory and refresh-hidden memory
JP2003297080A (ja) * 2002-03-29 2003-10-17 Mitsubishi Electric Corp 半導体記憶装置
JP2003317472A (ja) * 2002-04-17 2003-11-07 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
US20080062776A1 (en) 2008-03-13
US7447098B2 (en) 2008-11-04
JP2006294216A (ja) 2006-10-26
KR20060100227A (ko) 2006-09-20
US20060209611A1 (en) 2006-09-21
US7301843B2 (en) 2007-11-27

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