WO2011157136A3 - 一种数据管理方法、装置及数据芯片 - Google Patents

一种数据管理方法、装置及数据芯片 Download PDF

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Publication number
WO2011157136A3
WO2011157136A3 PCT/CN2011/075026 CN2011075026W WO2011157136A3 WO 2011157136 A3 WO2011157136 A3 WO 2011157136A3 CN 2011075026 W CN2011075026 W CN 2011075026W WO 2011157136 A3 WO2011157136 A3 WO 2011157136A3
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WO
WIPO (PCT)
Prior art keywords
chip
data
written data
data management
mode
Prior art date
Application number
PCT/CN2011/075026
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English (en)
French (fr)
Other versions
WO2011157136A2 (zh
Inventor
魏华
郑勤
杜文华
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN2011800005353A priority Critical patent/CN102216911A/zh
Priority to PCT/CN2011/075026 priority patent/WO2011157136A2/zh
Publication of WO2011157136A2 publication Critical patent/WO2011157136A2/zh
Publication of WO2011157136A3 publication Critical patent/WO2011157136A3/zh
Priority to US13/483,331 priority patent/US20120311264A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Power Sources (AREA)

Abstract

本发明公开了一种数据管理方法、装置及数据芯片，其中，数据管理方法包括：接收写请求的写入数据；根据当前的数据管理模式，写入所述写入数据，其中，当所述数据管理模式为第一模式时，将写请求的写入数据存储在片内缓存中；当所述数据管理模式为第二模式时，将写请求的写入数据存储在所述片内缓存及片外存储芯片中；接收所述写入数据的读请求，根据所述读请求从所述片内缓存中搜索所述写入数据，如果无法从所述片内缓存中获得所述写入数据，则从所述片外存储芯片中获得所述写入数据，从而实现降低数据访问外存储芯片的功耗。
PCT/CN2011/075026 2011-05-31 2011-05-31 一种数据管理方法、装置及数据芯片 WO2011157136A2 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2011800005353A CN102216911A (zh) 2011-05-31 2011-05-31 一种数据管理方法、装置及数据芯片
PCT/CN2011/075026 WO2011157136A2 (zh) 2011-05-31 2011-05-31 一种数据管理方法、装置及数据芯片
US13/483,331 US20120311264A1 (en) 2011-05-31 2012-05-30 Data management method, device, and data chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/075026 WO2011157136A2 (zh) 2011-05-31 2011-05-31 一种数据管理方法、装置及数据芯片

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/483,331 Continuation US20120311264A1 (en) 2011-05-31 2012-05-30 Data management method, device, and data chip

Publications (2)

Publication Number Publication Date
WO2011157136A2 WO2011157136A2 (zh) 2011-12-22
WO2011157136A3 true WO2011157136A3 (zh) 2012-04-26

Family

ID=44746730

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/075026 WO2011157136A2 (zh) 2011-05-31 2011-05-31 一种数据管理方法、装置及数据芯片

Country Status (3)

Country Link
US (1) US20120311264A1 (zh)
CN (1) CN102216911A (zh)
WO (1) WO2011157136A2 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103605623A (zh) * 2013-10-31 2014-02-26 北京智谷睿拓技术服务有限公司 存储设备的读写控制方法和读写控制设备
CN106326141A (zh) * 2015-06-16 2017-01-11 中兴通讯股份有限公司 数据缓存处理方法及装置
CN107025184B (zh) * 2016-02-01 2021-03-16 深圳市中兴微电子技术有限公司 一种数据管理方法及装置
CN106569746A (zh) * 2016-11-01 2017-04-19 北京信安世纪科技有限公司 一种数据写入的方法及装置
US10740029B2 (en) * 2017-11-28 2020-08-11 Advanced Micro Devices, Inc. Expandable buffer for memory transactions
CN112804156A (zh) * 2019-11-13 2021-05-14 深圳市中兴微电子技术有限公司 一种拥塞避免方法和装置及计算机可读存储介质
CN111176582A (zh) * 2019-12-31 2020-05-19 北京百度网讯科技有限公司 矩阵存储方法、矩阵访问方法、装置和电子设备
CN111782578B (zh) * 2020-05-29 2022-07-12 西安电子科技大学 一种缓存控制方法、系统、存储介质、计算机设备及应用
CN114698391A (zh) * 2020-10-30 2022-07-01 深圳市大疆创新科技有限公司 数字管理单元和数字信号处理系统
CN116889024A (zh) * 2021-02-22 2023-10-13 华为技术有限公司 一种数据流传输方法、装置及网络设备
CN115327582B (zh) * 2022-10-13 2023-02-14 北京凯芯微科技有限公司 Gnss信号处理电路、方法和接收机

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276851A (en) * 1989-12-22 1994-01-04 Digital Equipment Corporation Automatic writeback and storage limit in a high-performance frame buffer and cache memory system
CN1171159A (zh) * 1994-12-23 1998-01-21 英特尔公司 具有减少功率操作特性的高速缓存一致性多道处理计算机系统
US6381190B1 (en) * 1999-05-13 2002-04-30 Nec Corporation Semiconductor memory device in which use of cache can be selected
CN1553496A (zh) * 2003-06-05 2004-12-08 中兴通讯股份有限公司 一种用于访问系统芯片外sdram的控制器及其实现方法
CN101246460A (zh) * 2008-03-10 2008-08-20 华为技术有限公司 缓存数据写入系统及方法和缓存数据读取系统及方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7562190B1 (en) * 2005-06-17 2009-07-14 Sun Microsystems, Inc. Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture
CN101621469B (zh) * 2009-08-13 2012-01-04 杭州华三通信技术有限公司 数据报文存取控制装置和方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276851A (en) * 1989-12-22 1994-01-04 Digital Equipment Corporation Automatic writeback and storage limit in a high-performance frame buffer and cache memory system
CN1171159A (zh) * 1994-12-23 1998-01-21 英特尔公司 具有减少功率操作特性的高速缓存一致性多道处理计算机系统
US6381190B1 (en) * 1999-05-13 2002-04-30 Nec Corporation Semiconductor memory device in which use of cache can be selected
CN1553496A (zh) * 2003-06-05 2004-12-08 中兴通讯股份有限公司 一种用于访问系统芯片外sdram的控制器及其实现方法
CN101246460A (zh) * 2008-03-10 2008-08-20 华为技术有限公司 缓存数据写入系统及方法和缓存数据读取系统及方法

Also Published As

Publication number Publication date
CN102216911A (zh) 2011-10-12
WO2011157136A2 (zh) 2011-12-22
US20120311264A1 (en) 2012-12-06

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