WO2005069148A3 - Memory management method and related system - Google Patents

Memory management method and related system Download PDF

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Publication number
WO2005069148A3
WO2005069148A3 PCT/IB2005/050123 IB2005050123W WO2005069148A3 WO 2005069148 A3 WO2005069148 A3 WO 2005069148A3 IB 2005050123 W IB2005050123 W IB 2005050123W WO 2005069148 A3 WO2005069148 A3 WO 2005069148A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
devices
data
memory devices
management method
Prior art date
Application number
PCT/IB2005/050123
Other languages
French (fr)
Other versions
WO2005069148A2 (en
Inventor
Richard M Miller-Smith
Original Assignee
Koninkl Philips Electronics Nv
Richard M Miller-Smith
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Richard M Miller-Smith filed Critical Koninkl Philips Electronics Nv
Publication of WO2005069148A2 publication Critical patent/WO2005069148A2/en
Publication of WO2005069148A3 publication Critical patent/WO2005069148A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The present invention provides for a memory management method and related system for use with a memory arrangement comprising a plurality of memory devices such as SDRAM chips which provide define a plurality of memory locations for the storage of data to be accessed, the method including the step of moving more frequently access data to common devices of the said plurality of memory devices so as to reduce the number of the said plurality of devices in which the more frequently accessed data is stored, thereby allowing for the power-saving mode to be initiated at memory devices within the said plurality of memory devices not including the said more frequently accessed data. Through such re-mapping of active memory pages into a reduced number of devices, as determined by the frequency with which the data is required, memory devices that are then devoid of such active page can be placed into, for example, a self-refresh or powered-down mode.
PCT/IB2005/050123 2004-01-13 2005-01-11 Memory management method and related system WO2005069148A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0400661.5 2004-01-13
GBGB0400661.5A GB0400661D0 (en) 2004-01-13 2004-01-13 Memory management method and related system

Publications (2)

Publication Number Publication Date
WO2005069148A2 WO2005069148A2 (en) 2005-07-28
WO2005069148A3 true WO2005069148A3 (en) 2006-02-23

Family

ID=31503818

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/050123 WO2005069148A2 (en) 2004-01-13 2005-01-11 Memory management method and related system

Country Status (2)

Country Link
GB (1) GB0400661D0 (en)
WO (1) WO2005069148A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8201004B2 (en) 2006-09-14 2012-06-12 Texas Instruments Incorporated Entry/exit control to/from a low power state in a complex multi level memory system
GB2426360A (en) * 2005-05-18 2006-11-22 Symbian Software Ltd Reorganisation of memory for conserving power in a computing device
TW200746161A (en) * 2005-12-21 2007-12-16 Nxp Bv Power partitioning memory banks
JP5111965B2 (en) * 2007-07-24 2013-01-09 株式会社日立製作所 Storage control device and control method thereof
US8166326B2 (en) * 2007-11-08 2012-04-24 International Business Machines Corporation Managing power consumption in a computer
US8041521B2 (en) 2007-11-28 2011-10-18 International Business Machines Corporation Estimating power consumption of computing components configured in a computing system
US8103884B2 (en) 2008-06-25 2012-01-24 International Business Machines Corporation Managing power consumption of a computer
US8078695B2 (en) 2008-07-16 2011-12-13 Sony Corporation Media on demand using an intermediary device to output media from a remote computing device
US8041976B2 (en) 2008-10-01 2011-10-18 International Business Machines Corporation Power management for clusters of computers
US8514215B2 (en) 2008-11-12 2013-08-20 International Business Machines Corporation Dynamically managing power consumption of a computer with graphics adapter configurations
GB2466264A (en) * 2008-12-17 2010-06-23 Symbian Software Ltd Memory defragmentation and compaction into high priority memory banks
US8738875B2 (en) * 2011-11-14 2014-05-27 International Business Machines Corporation Increasing memory capacity in power-constrained systems

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630097A (en) * 1991-06-17 1997-05-13 Digital Equipment Corporation Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses
US20030023825A1 (en) * 2001-07-30 2003-01-30 Woo Steven C Consolidation of allocated memory to reduce power consumption
US20030051104A1 (en) * 2001-09-07 2003-03-13 Erik Riedel Technique for migrating data between storage devices for reduced power consumption
JP2003108317A (en) * 2001-09-27 2003-04-11 Fujitsu Ltd Storage system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630097A (en) * 1991-06-17 1997-05-13 Digital Equipment Corporation Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses
US20030023825A1 (en) * 2001-07-30 2003-01-30 Woo Steven C Consolidation of allocated memory to reduce power consumption
US20030051104A1 (en) * 2001-09-07 2003-03-13 Erik Riedel Technique for migrating data between storage devices for reduced power consumption
JP2003108317A (en) * 2001-09-27 2003-04-11 Fujitsu Ltd Storage system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2003, no. 08 6 August 2003 (2003-08-06) *
V. DE LA LUZ, M. KANDEMIR AND I. KOLCU: "Automatic data migration for reducing energy consumption in multi-bank memory systems", PROCEEDINGS OF 39TH DESIGN AUTOMATION CONFERENCE 10-14 JUNE 2002 NEW ORLEANS, LA, USA, June 2002 (2002-06-01), Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ACM New York, NY, USA, pages 213 - 218, XP002340853, ISBN: 1-58113-461-4 *

Also Published As

Publication number Publication date
WO2005069148A2 (en) 2005-07-28
GB0400661D0 (en) 2004-02-11

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