TW200643971A - High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips - Google Patents

High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips

Info

Publication number
TW200643971A
TW200643971A TW095118524A TW95118524A TW200643971A TW 200643971 A TW200643971 A TW 200643971A TW 095118524 A TW095118524 A TW 095118524A TW 95118524 A TW95118524 A TW 95118524A TW 200643971 A TW200643971 A TW 200643971A
Authority
TW
Taiwan
Prior art keywords
interface circuit
read data
serial
circuit section
semiconductor memory
Prior art date
Application number
TW095118524A
Other languages
English (en)
Inventor
Peter Gregorius
Martin Streibl
Paul Wallner
Thomas Rickes
Original Assignee
Qimonda Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qimonda Ag filed Critical Qimonda Ag
Publication of TW200643971A publication Critical patent/TW200643971A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
TW095118524A 2005-06-15 2006-05-24 High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips TW200643971A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/152,769 US7184360B2 (en) 2005-06-15 2005-06-15 High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips

Publications (1)

Publication Number Publication Date
TW200643971A true TW200643971A (en) 2006-12-16

Family

ID=37513731

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095118524A TW200643971A (en) 2005-06-15 2006-05-24 High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips

Country Status (4)

Country Link
US (1) US7184360B2 (zh)
CN (1) CN1892894A (zh)
DE (1) DE102006025957A1 (zh)
TW (1) TW200643971A (zh)

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US20070076502A1 (en) * 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
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RU2486577C1 (ru) * 2009-06-10 2013-06-27 Шарп Кабусики Кайся Схема управления дисплеем и одноплатный модуль, включающий в себя такую схему
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TWI566256B (zh) * 2015-05-06 2017-01-11 瑞昱半導體股份有限公司 記憶體系統及其記憶體實體介面電路
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KR102684558B1 (ko) * 2016-12-28 2024-07-15 에스케이하이닉스 주식회사 반도체 장치 및 반도체 시스템
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Also Published As

Publication number Publication date
US7184360B2 (en) 2007-02-27
DE102006025957A1 (de) 2006-12-28
CN1892894A (zh) 2007-01-10
US20060285424A1 (en) 2006-12-21

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