TW200633383A - Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same - Google Patents
Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the sameInfo
- Publication number
- TW200633383A TW200633383A TW095104618A TW95104618A TW200633383A TW 200633383 A TW200633383 A TW 200633383A TW 095104618 A TW095104618 A TW 095104618A TW 95104618 A TW95104618 A TW 95104618A TW 200633383 A TW200633383 A TW 200633383A
- Authority
- TW
- Taiwan
- Prior art keywords
- pads
- semiconductor device
- chip package
- common function
- input buffers
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20050011540A KR100588337B1 (ko) | 2005-02-11 | 2005-02-11 | 동일한 기능의 복수개 패드를 채용한 반도체 장치 및 이를이용한 멀티 칩 패키지 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200633383A true TW200633383A (en) | 2006-09-16 |
Family
ID=36814843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095104618A TW200633383A (en) | 2005-02-11 | 2006-02-10 | Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same |
Country Status (3)
Country | Link |
---|---|
US (1) | US7518409B2 (zh) |
KR (1) | KR100588337B1 (zh) |
TW (1) | TW200633383A (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9202776B2 (en) * | 2006-06-01 | 2015-12-01 | Stats Chippac Ltd. | Stackable multi-chip package system |
KR100795027B1 (ko) * | 2007-03-12 | 2008-01-16 | 주식회사 하이닉스반도체 | 반도체 집적 회로 및 이를 포함하는 반도체 패키지 모듈 |
KR20090103600A (ko) * | 2008-03-28 | 2009-10-01 | 페어차일드코리아반도체 주식회사 | 전력 소자용 기판 및 이를 포함하는 전력 소자 패키지 |
JP5822370B2 (ja) * | 2011-07-05 | 2015-11-24 | インテル・コーポレーション | セルフディセーブルチップイネーブル入力 |
CN107564559B (zh) * | 2017-10-24 | 2023-09-26 | 长鑫存储技术有限公司 | 漏电流控制方法、节省静态漏电装置及半导体存储器 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG52794A1 (en) * | 1990-04-26 | 1998-09-28 | Hitachi Ltd | Semiconductor device and method for manufacturing same |
JP2526511B2 (ja) * | 1993-11-01 | 1996-08-21 | 日本電気株式会社 | 半導体装置 |
KR20000019885A (ko) | 1998-09-16 | 2000-04-15 | 윤종용 | 복수개의 본딩 패드 세트를 구비한 반도체장치 |
US6355980B1 (en) * | 1999-07-15 | 2002-03-12 | Nanoamp Solutions Inc. | Dual die memory |
KR100353810B1 (ko) * | 1999-11-12 | 2002-09-26 | 주식회사 하이닉스반도체 | 반도체 메모리 장치에 있어서 최적의 셋-업 및 홀드시간을 갖는 입력버퍼 |
KR100631910B1 (ko) * | 1999-12-13 | 2006-10-04 | 삼성전자주식회사 | 동일한 칩을 사용하는 멀티-칩 패키지 |
JP3955712B2 (ja) | 2000-03-03 | 2007-08-08 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2001345344A (ja) | 2000-05-31 | 2001-12-14 | Toshiba Corp | 高周波半導体装置 |
JP2003007963A (ja) | 2001-06-20 | 2003-01-10 | Hitachi Ltd | 半導体記憶装置および製造方法 |
US6714049B2 (en) * | 2001-08-10 | 2004-03-30 | Shakti Systems, Inc. | Logic state transition sensor circuit |
KR100422450B1 (ko) * | 2002-05-10 | 2004-03-11 | 삼성전자주식회사 | 반도체 메모리장치의 플립칩 인터페이스회로 및 그 방법 |
KR20040031995A (ko) | 2002-10-08 | 2004-04-14 | 주식회사 하이닉스반도체 | 반도체 장치의 멀티칩 패키지 방법 |
KR20040069392A (ko) * | 2003-01-29 | 2004-08-06 | 주식회사 하이닉스반도체 | 적층형 반도체 멀티 칩 패키지 |
KR100551072B1 (ko) * | 2003-12-29 | 2006-02-10 | 주식회사 하이닉스반도체 | 멀티-칩 패키지에서 입출력패드의 효율적인 멀티플렉싱이가능한 반도체 메모리 장치 |
-
2005
- 2005-02-11 KR KR20050011540A patent/KR100588337B1/ko not_active IP Right Cessation
-
2006
- 2006-02-10 US US11/352,175 patent/US7518409B2/en not_active Expired - Fee Related
- 2006-02-10 TW TW095104618A patent/TW200633383A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
KR100588337B1 (ko) | 2006-06-09 |
US7518409B2 (en) | 2009-04-14 |
US20060180913A1 (en) | 2006-08-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200717002A (en) | Electronic device having and interface supported testing mode | |
WO2010053821A3 (en) | Technique for interconnecting integrated circuits | |
TW200712518A (en) | Shared bond pad for testing a memory within a packaged semiconductor device | |
US6724237B2 (en) | Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity | |
ATE505764T1 (de) | Schnittstellenhalbleiterschaltanordnung für eine usb verbindung | |
TW200708750A (en) | Testable integrated circuit, system in package and test instruction set | |
TW200633383A (en) | Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same | |
GB2432759B (en) | Audio device | |
TW200634652A (en) | Double-sided electronic module for hybrid smart card | |
SG170099A1 (en) | Integrated circuit package system with warp-free chip | |
TW200706891A (en) | Semiconductor integrated circuit and method for testing connection state between semiconductor integrated circuits | |
WO2006051527A3 (en) | Integrated circuit die with logically equivalent bonding pads | |
JP5771486B2 (ja) | 半導体メモリチップ及びこれを用いるマルチチップパッケージ | |
WO2006071668A3 (en) | Pin electronics with high voltage functionality | |
TW200504934A (en) | Semiconductor integrated circuit device | |
ATE290744T1 (de) | Anpassbare chipkarte | |
WO2007067423A3 (en) | Integrated circuit with configurable bypass capacitance | |
KR20080068346A (ko) | 반도체 장치의 멀티패드구조 및 구성방법 | |
KR100568537B1 (ko) | 버퍼드 메모리 모듈 | |
CN108901122A (zh) | 一种内存卡磨损保护套 | |
JP2014099630A5 (zh) | ||
US8884679B2 (en) | Apparatus and method for high voltage switches | |
US7701041B2 (en) | Chip-packaging with bonding options having a plurality of package substrates | |
TW200644211A (en) | Semiconductor device and method of manufacturing the same | |
US20080003714A1 (en) | Chip-packaging with bonding options connected to a package substrate |