TW200631132A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same

Info

Publication number
TW200631132A
TW200631132A TW094141805A TW94141805A TW200631132A TW 200631132 A TW200631132 A TW 200631132A TW 094141805 A TW094141805 A TW 094141805A TW 94141805 A TW94141805 A TW 94141805A TW 200631132 A TW200631132 A TW 200631132A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
forming
connection hole
lower wire
manufacturing
Prior art date
Application number
TW094141805A
Other languages
English (en)
Chinese (zh)
Other versions
TWI299542B (enExample
Inventor
Shinichi Arakawa
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of TW200631132A publication Critical patent/TW200631132A/zh
Application granted granted Critical
Publication of TWI299542B publication Critical patent/TWI299542B/zh

Links

Classifications

    • H10W20/064
    • H10W20/01
    • H10D64/011
    • H10W20/034
    • H10W20/036
    • H10W20/037
    • H10W20/041
    • H10W20/0526
    • H10W20/054
    • H10W20/077
    • H10W20/081
    • H10W20/083
    • H10W20/084
    • H10W20/42
    • H10W20/425

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094141805A 2004-12-10 2005-11-29 Semiconductor device and method for manufacturing the same TW200631132A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004358140A JP2006165454A (ja) 2004-12-10 2004-12-10 半導体装置の製造方法および半導体装置

Publications (2)

Publication Number Publication Date
TW200631132A true TW200631132A (en) 2006-09-01
TWI299542B TWI299542B (enExample) 2008-08-01

Family

ID=36582864

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094141805A TW200631132A (en) 2004-12-10 2005-11-29 Semiconductor device and method for manufacturing the same

Country Status (4)

Country Link
US (2) US7416974B2 (enExample)
JP (1) JP2006165454A (enExample)
KR (1) KR20060065512A (enExample)
TW (1) TW200631132A (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8043484B1 (en) 2001-03-13 2011-10-25 Novellus Systems, Inc. Methods and apparatus for resputtering process that improves barrier coverage
US6764940B1 (en) 2001-03-13 2004-07-20 Novellus Systems, Inc. Method for depositing a diffusion barrier for copper interconnect applications
US7842605B1 (en) 2003-04-11 2010-11-30 Novellus Systems, Inc. Atomic layer profiling of diffusion barrier and metal seed layers
US8298933B2 (en) 2003-04-11 2012-10-30 Novellus Systems, Inc. Conformal films on semiconductor substrates
US7432195B2 (en) * 2006-03-29 2008-10-07 Tokyo Electron Limited Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features
US7855147B1 (en) * 2006-06-22 2010-12-21 Novellus Systems, Inc. Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer
US7473634B2 (en) * 2006-09-28 2009-01-06 Tokyo Electron Limited Method for integrated substrate processing in copper metallization
US7510634B1 (en) 2006-11-10 2009-03-31 Novellus Systems, Inc. Apparatus and methods for deposition and/or etch selectivity
US7569475B2 (en) * 2006-11-15 2009-08-04 International Business Machines Corporation Interconnect structure having enhanced electromigration reliability and a method of fabricating same
KR100795363B1 (ko) * 2006-11-24 2008-01-17 삼성전자주식회사 반도체 소자의 도전성 배선 및 이의 형성방법과 이를구비하는 플래시 메모리 장치 및 이의 제조 방법
WO2008074672A1 (en) * 2006-12-20 2008-06-26 Nxp B.V. Improving adhesion of diffusion barrier on cu containing interconnect element
KR100790452B1 (ko) * 2006-12-28 2008-01-03 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
JP5103914B2 (ja) * 2007-01-31 2012-12-19 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
US7682966B1 (en) 2007-02-01 2010-03-23 Novellus Systems, Inc. Multistep method of depositing metal seed layers
US7922880B1 (en) 2007-05-24 2011-04-12 Novellus Systems, Inc. Method and apparatus for increasing local plasma density in magnetically confined plasma
US7897516B1 (en) 2007-05-24 2011-03-01 Novellus Systems, Inc. Use of ultra-high magnetic fields in resputter and plasma etching
DE102007035834A1 (de) * 2007-07-31 2009-02-05 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit lokal erhöhtem Elektromigrationswiderstand in einer Verbindungsstruktur
US7846834B2 (en) * 2008-02-04 2010-12-07 International Business Machines Corporation Interconnect structure and method for Cu/ultra low k integration
US8017523B1 (en) 2008-05-16 2011-09-13 Novellus Systems, Inc. Deposition of doped copper seed layers having improved reliability
KR100997315B1 (ko) * 2008-07-15 2010-11-29 주식회사 동부하이텍 이미지 센서의 제조 방법
TWI394239B (zh) * 2008-12-17 2013-04-21 Univ Ishou The integrated circuit with the isolation layer of metal ion migration and its encapsulation structure
US8288276B2 (en) * 2008-12-30 2012-10-16 International Business Machines Corporation Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion
US8299567B2 (en) * 2010-11-23 2012-10-30 International Business Machines Corporation Structure of metal e-fuse
DE102016125299B4 (de) 2016-01-29 2024-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und Verfahren zu ihrer Herstellung
US10153351B2 (en) * 2016-01-29 2018-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
KR102493464B1 (ko) 2018-07-19 2023-01-30 삼성전자 주식회사 집적회로 장치 및 이의 제조 방법
US10580696B1 (en) * 2018-08-21 2020-03-03 Globalfoundries Inc. Interconnects formed by a metal displacement reaction
US11502000B2 (en) * 2020-08-24 2022-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Bottom lateral expansion of contact plugs through implantation
TWI844803B (zh) 2021-10-28 2024-06-11 鴻海精密工業股份有限公司 光子晶體面射型雷射裝置及光學系統
CN117199155B (zh) * 2023-11-06 2024-02-13 杭州特洛伊光电技术有限公司 一种波导型可见光及近红外光探测器结构与制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250432A (ja) 1988-08-12 1990-02-20 Toshiba Corp 半導体装置
JPH07297194A (ja) 1994-04-25 1995-11-10 Sony Corp マルチチャンバー装置及び半導体装置の製造方法
US6555465B2 (en) * 1997-12-05 2003-04-29 Yamaha Corp. Multi-layer wiring structure of integrated circuit and manufacture of multi-layer wiring
US6075291A (en) * 1998-02-27 2000-06-13 Micron Technology, Inc. Structure for contact formation using a silicon-germanium alloy
JP2001341977A (ja) 2000-06-01 2001-12-11 Ishikawajima Harima Heavy Ind Co Ltd ホイストクレーン
WO2006058034A2 (en) * 2004-11-22 2006-06-01 Intermolecular, Inc. Molecular self-assembly in substrate processing

Also Published As

Publication number Publication date
US7416974B2 (en) 2008-08-26
US7851924B2 (en) 2010-12-14
TWI299542B (enExample) 2008-08-01
US20060125100A1 (en) 2006-06-15
JP2006165454A (ja) 2006-06-22
US20080265418A1 (en) 2008-10-30
KR20060065512A (ko) 2006-06-14

Similar Documents

Publication Publication Date Title
TW200631132A (en) Semiconductor device and method for manufacturing the same
US10090486B2 (en) Frameless display device with concealed drive circuit board and manufacturing method thereof
SG169329A1 (en) Methods for fabricating and filling conductive vias and conductive vias so formed
TW200605242A (en) Wafer-level chip scale packaging method
WO2009004855A1 (ja) 配線基板の製造方法
TW200618227A (en) Structure of embedding chip in substrate and method for fabricating the same
TW200725709A (en) Semiconductor apparatus and making method thereof
TW200625559A (en) Wiring substrate for mounting semiconductors, method of manufacturing the same, and semiconductor package
TW200725803A (en) Via structure and process for forming the same
WO2004001837A3 (en) Methods of forming electronic structures including conductive shunt layers and related structures
JPH11233631A5 (enExample)
WO2008011687A3 (en) Conductive contacts on ge
TW200707754A (en) Wire structure, method of forming wire, thin film transistor substrate, and method of manufacturing thin film transistor substrate
WO2009155160A3 (en) Multi-layer thick metallization structure for a microelectronic device, integrated circuit containing same, and method of manufacturing an integrated circuit containing same
TW200710966A (en) Semiconductor device and method for production thereof
TW200503064A (en) Method for manufacturing semiconductor package
WO2008083145A3 (en) Control of standoff height between packages with a solder-embedded tape
WO2005101499A3 (en) Methods of forming solder bumps on exposed metal pads and related structures
TW200746330A (en) Microelectronic assembly with back side metallization and method for forming the same
TW200731537A (en) Semiconductor device and manufacturing method thereof
WO2009017271A3 (en) Metal-based package substrate, three-dimensional multi-layered package module using the same, and manufacturing method thereof
MY140754A (en) Connection board, and multi-layer wiring board, substrate for semiconductor package and semiconductor package using connection board, and manufacturing method thereof
TW201237972A (en) Chip package and method for forming the same
WO2004061952A3 (en) Method of forming a multi-layer semiconductor structure having a seamless bonding interface
WO2003095712A3 (en) Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees