TW200618093A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
TW200618093A
TW200618093A TW094126554A TW94126554A TW200618093A TW 200618093 A TW200618093 A TW 200618093A TW 094126554 A TW094126554 A TW 094126554A TW 94126554 A TW94126554 A TW 94126554A TW 200618093 A TW200618093 A TW 200618093A
Authority
TW
Taiwan
Prior art keywords
interlayer insulating
insulating film
semiconductor device
film
manufacturing semiconductor
Prior art date
Application number
TW094126554A
Other languages
English (en)
Chinese (zh)
Inventor
Takahito Nakajima
Yoshihiro Uozumi
Mikie Miyasato
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW200618093A publication Critical patent/TW200618093A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
TW094126554A 2004-08-10 2005-08-04 Method for manufacturing semiconductor device TW200618093A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004233405A JP2006054251A (ja) 2004-08-10 2004-08-10 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW200618093A true TW200618093A (en) 2006-06-01

Family

ID=35996822

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094126554A TW200618093A (en) 2004-08-10 2005-08-04 Method for manufacturing semiconductor device

Country Status (3)

Country Link
US (1) US20060051969A1 (https=)
JP (1) JP2006054251A (https=)
TW (1) TW200618093A (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4734090B2 (ja) * 2005-10-31 2011-07-27 株式会社東芝 半導体装置の製造方法
KR20100079221A (ko) * 2008-12-31 2010-07-08 주식회사 동부하이텍 반도체 소자의 구리 배선 형성 방법
US8222160B2 (en) * 2010-11-30 2012-07-17 Kabushiki Kaisha Toshiba Metal containing sacrifice material and method of damascene wiring formation
US10460984B2 (en) 2015-04-15 2019-10-29 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating electrode and semiconductor device
US9679807B1 (en) * 2015-11-20 2017-06-13 Globalfoundries Inc. Method, apparatus, and system for MOL interconnects without titanium liner
TW201939628A (zh) * 2018-03-02 2019-10-01 美商微材料有限責任公司 移除金屬氧化物的方法
JP7015754B2 (ja) * 2018-08-30 2022-02-03 ルネサスエレクトロニクス株式会社 半導体装置
CN112864086A (zh) * 2019-11-28 2021-05-28 长鑫存储技术有限公司 导电互连结构及其制备方法
CN113314457B (zh) 2020-02-27 2023-04-18 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
CN113380693A (zh) * 2020-03-10 2021-09-10 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
KR100221656B1 (ko) * 1996-10-23 1999-09-15 구본준 배선 형성 방법
US6417112B1 (en) * 1998-07-06 2002-07-09 Ekc Technology, Inc. Post etch cleaning composition and process for dual damascene system
JP3883706B2 (ja) * 1998-07-31 2007-02-21 シャープ株式会社 エッチング方法、及び薄膜トランジスタマトリックス基板の製造方法
TW503522B (en) * 2001-09-04 2002-09-21 Nanya Plastics Corp Method for preventing short circuit between metal conduction wires
US6812156B2 (en) * 2002-07-02 2004-11-02 Taiwan Semiconductor Manufacturing Co., Ltd Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing

Also Published As

Publication number Publication date
US20060051969A1 (en) 2006-03-09
JP2006054251A (ja) 2006-02-23

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