TW200612705A - Method and apparatus to set a tuning range for an analog delay - Google Patents
Method and apparatus to set a tuning range for an analog delayInfo
- Publication number
- TW200612705A TW200612705A TW094124818A TW94124818A TW200612705A TW 200612705 A TW200612705 A TW 200612705A TW 094124818 A TW094124818 A TW 094124818A TW 94124818 A TW94124818 A TW 94124818A TW 200612705 A TW200612705 A TW 200612705A
- Authority
- TW
- Taiwan
- Prior art keywords
- delay
- fine
- delay line
- coarse
- analog
- Prior art date
Links
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000000977 initiatory effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
- H03H11/265—Time-delay networks with adjustable delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/897,166 US7138845B2 (en) | 2004-07-22 | 2004-07-22 | Method and apparatus to set a tuning range for an analog delay |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200612705A true TW200612705A (en) | 2006-04-16 |
TWI271979B TWI271979B (en) | 2007-01-21 |
Family
ID=35045104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094124818A TWI271979B (en) | 2004-07-22 | 2005-07-22 | Method and apparatus to set a tuning range for an analog delay |
Country Status (6)
Country | Link |
---|---|
US (2) | US7138845B2 (zh) |
EP (1) | EP1769581A1 (zh) |
JP (1) | JP2008507921A (zh) |
KR (1) | KR101080547B1 (zh) |
TW (1) | TWI271979B (zh) |
WO (1) | WO2006012464A1 (zh) |
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US7685456B1 (en) | 2003-07-30 | 2010-03-23 | Marvell Israel (Misl) Ltd. | DDR interface bus control |
DE10345489B3 (de) * | 2003-09-30 | 2005-04-14 | Infineon Technologies Ag | Vorrichtung zur Verwendung bei der Synchronisation von Taktsignalen, sowie Taktsignal-Synchronisationsverfahren |
US7149145B2 (en) * | 2004-07-19 | 2006-12-12 | Micron Technology, Inc. | Delay stage-interweaved analog DLL/PLL |
US7345933B1 (en) * | 2005-01-13 | 2008-03-18 | Marvell Semiconductor Israel Ltd. | Qualified data strobe signal for double data rate memory controller module |
US7227395B1 (en) * | 2005-02-09 | 2007-06-05 | Altera Corporation | High-performance memory interface circuit architecture |
US8130889B2 (en) | 2005-04-04 | 2012-03-06 | Texas Instruments Incorporated | Receive timing manager |
US7639769B2 (en) * | 2005-04-21 | 2009-12-29 | Agere Systems Inc. | Method and apparatus for providing synchronization in a communication system |
US7571406B2 (en) * | 2005-08-04 | 2009-08-04 | Freescale Semiconductor, Inc. | Clock tree adjustable buffer |
US7285996B2 (en) * | 2005-09-30 | 2007-10-23 | Slt Logic, Llc | Delay-locked loop |
US7671647B2 (en) * | 2006-01-26 | 2010-03-02 | Micron Technology, Inc. | Apparatus and method for trimming static delay of a synchronizing circuit |
JP2008136030A (ja) * | 2006-11-29 | 2008-06-12 | Matsushita Electric Ind Co Ltd | クロックタイミング調整方法及び半導体集積回路 |
KR100919243B1 (ko) * | 2007-01-17 | 2009-09-30 | 삼성전자주식회사 | 주파수 대역에 적응적인 코오스 락 타임을 갖는 dll회로 및 이를 구비하는 반도체 메모리 장치 |
US7928607B2 (en) | 2007-03-29 | 2011-04-19 | Lamar Technologies Llc | Aircraft power system and apparatus for supplying power to an aircraft electrical system |
KR100856070B1 (ko) * | 2007-03-30 | 2008-09-02 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그의 구동방법 |
KR100891335B1 (ko) * | 2007-07-02 | 2009-03-31 | 삼성전자주식회사 | 비트 에러율 측정을 수행 할 수 있는 클럭 발생 장치 |
JP2009177778A (ja) * | 2008-01-25 | 2009-08-06 | Elpida Memory Inc | Dll回路及びこれを用いた半導体装置、並びに、dll回路の制御方法 |
US8032778B2 (en) | 2008-03-19 | 2011-10-04 | Micron Technology, Inc. | Clock distribution apparatus, systems, and methods |
EP2267898A1 (en) * | 2008-04-11 | 2010-12-29 | Fujitsu Limited | Phase controller, phase controlling printed circuit board and controlling method |
KR101027676B1 (ko) * | 2008-06-26 | 2011-04-12 | 주식회사 하이닉스반도체 | 위상 동기 장치 |
KR20100129017A (ko) * | 2009-05-29 | 2010-12-08 | 칭화대학교 | 지연 동기 루프 및 이를 포함하는 전자 장치 |
US8683098B2 (en) | 2010-03-29 | 2014-03-25 | Intel Corporation | Method and apparatus for minimizing within-die variations in performance parameters of a processor |
TWI418137B (zh) | 2010-12-24 | 2013-12-01 | Via Tech Inc | 電壓控制振盪器 |
US8890627B2 (en) | 2010-12-24 | 2014-11-18 | Via Technologies, Inc. | Voltage controlled oscillator |
CN102035471B (zh) * | 2011-01-05 | 2014-04-02 | 威盛电子股份有限公司 | 电压控制振荡器 |
ITTO20110254A1 (it) * | 2011-03-24 | 2012-09-25 | Onetastic S R L | Metodo e sistema per controllare e stabilizzare la frequenza di un segnale generato da un oscillatore di tipo controllabile |
US8779816B2 (en) * | 2012-06-20 | 2014-07-15 | Conexant Systems, Inc. | Low area all digital delay-locked loop insensitive to reference clock duty cycle and jitter |
US9106400B2 (en) * | 2012-10-23 | 2015-08-11 | Futurewei Technologies, Inc. | Hybrid timing recovery for burst mode receiver in passive optical networks |
US9224444B1 (en) * | 2014-10-24 | 2015-12-29 | Xilinx, Inc. | Method and apparatus for VT invariant SDRAM write leveling and fast rank switching |
US10250242B2 (en) * | 2016-04-01 | 2019-04-02 | Integrated Device Technology, Inc. | Arbitrary delay buffer |
JP6870518B2 (ja) * | 2017-07-25 | 2021-05-12 | セイコーエプソン株式会社 | 集積回路装置、物理量測定装置、電子機器及び移動体 |
CN109088634B (zh) * | 2018-07-13 | 2022-03-29 | 东南大学 | 一种低相噪宽频带微波频率源电路 |
KR20210140875A (ko) * | 2020-05-14 | 2021-11-23 | 삼성전자주식회사 | 멀티 위상 클록 생성기, 그것을 포함하는 메모리 장치, 및 그것의 멀티 위상클록 생성 방법 |
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JPH021620A (ja) * | 1987-11-30 | 1990-01-05 | Toshiba Corp | 電圧制御発振回路 |
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CN1393992A (zh) * | 2001-07-02 | 2003-01-29 | 朗迅科技公司 | 包含反馈回路的延迟补偿电路 |
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-
2004
- 2004-07-22 US US10/897,166 patent/US7138845B2/en active Active
-
2005
- 2005-07-21 KR KR1020077004215A patent/KR101080547B1/ko active IP Right Grant
- 2005-07-21 EP EP05773401A patent/EP1769581A1/en not_active Ceased
- 2005-07-21 JP JP2007522775A patent/JP2008507921A/ja active Pending
- 2005-07-21 WO PCT/US2005/025962 patent/WO2006012464A1/en active Application Filing
- 2005-07-22 TW TW094124818A patent/TWI271979B/zh active
-
2006
- 2006-08-07 US US11/500,204 patent/US7274239B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7274239B2 (en) | 2007-09-25 |
US7138845B2 (en) | 2006-11-21 |
JP2008507921A (ja) | 2008-03-13 |
TWI271979B (en) | 2007-01-21 |
EP1769581A1 (en) | 2007-04-04 |
US20060017480A1 (en) | 2006-01-26 |
US20060273836A1 (en) | 2006-12-07 |
KR101080547B1 (ko) | 2011-11-04 |
WO2006012464A1 (en) | 2006-02-02 |
KR20070045276A (ko) | 2007-05-02 |
WO2006012464B1 (en) | 2006-04-06 |
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