TW200531578A - Circuit board structure and method for fabricating the same - Google Patents

Circuit board structure and method for fabricating the same Download PDF

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TW200531578A
TW200531578A TW93105505A TW93105505A TW200531578A TW 200531578 A TW200531578 A TW 200531578A TW 93105505 A TW93105505 A TW 93105505A TW 93105505 A TW93105505 A TW 93105505A TW 200531578 A TW200531578 A TW 200531578A
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Taiwan
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layer
circuit board
plated
patent application
scope
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TW93105505A
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Chinese (zh)
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TWI226808B (en
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Bin-Yang Chen
Chih-Liang Chu
Hsin-Ku Huang
Wei-Cheng Huang
Xian-Zhang Wang
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Phoenix Prec Technology Corp
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Abstract

A circuit board structure and a method for fabricating the same are proposed, wherein a core substrate formed with a metal layer on surfaces thereof and a plurality of plated through holes therein is provided. A conductive layer is formed on the surface of the terminal portions of the plated through holes, and a patterned circuit layer is formed on the core substrate by patterning the metal layer. An insulating layer is respectively formed on the surface of circuit layer with a plurality of openings, wherein at least an opening on one side of circuit board is formed to expose the terminal portion of the plated through hole and the remaining openings on the other side of circuit board are covered by a resist layer. After a metal layer is formed on the plated through hole within the opening, the resist layer is removed. By the arrangement, the metal layer can be selectively formed on the partial plated through holes for electrical connection pads.

Description

200531578 五、發明說明(1) 【發明所屬之技術領域】 本發明係關於一種電路板 電路板中利用電鍍導通孔結才籌 之電路板結構及其製法。 【先前技術】 及其製法’尤指一種於多層 以導電連接上、下層線路層 隨著電子產業的蓬勃發展,電子產品亦逐漸邁入多功 能、高性能的研發趨勢。為滿足半導體封裝件高積集度( Integration)及微型化(Miniaturi zati〇n)的封裝需求, 以供更多主、被動元件及線路載接,承載半導體晶片之電 鲁板亦逐漸由雙層板演變成多層板(Multi —layer b〇ard) 俾在有限的空間下,運用層間連接技術(Interlayer c ο η n e c t i ο η)來擴大電路板上可供利用的線路佈局面積, 藉此配合高線路密度之積體電路(Integrated circuit)需 要’以在相同電路板單位面積下容納更多數量的線路及元 件0 為因應微處理器、晶片組與繪圖晶片等高效能晶片之 運异需要’電路板亦需提昇其傳遞晶片訊號、改善頻寬、 控制阻抗等功能,來成就高I / Q數封裝件的發展。然而, |符合半導體封裝件輕薄短小、多功能、高速度及高頻化 P開發方向,電路板已朝向細線路及小孔徑發展。現有電 路板製程從傳統1〇〇微米之線路尺寸··包括導線寬度(Une width)、線路間距(Space)及深寬比(Aspect rati〇) 等,縮減至3 0微米以下,並持續朝向更小的線路精度進行 研發。 又200531578 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a circuit board structure using a plated via hole junction in a circuit board and a manufacturing method thereof. [Previous technology] and its manufacturing method ', especially a multi-layer conductive connection between upper and lower circuit layers. With the vigorous development of the electronics industry, electronic products have gradually entered a multi-functional, high-performance research and development trend. In order to meet the packaging requirements of high integration and miniaturization of semiconductor packages, for more active and passive components and circuit connections, the electrical board carrying semiconductor wafers has also gradually changed from a double layer The board evolved into a multi-layer board (Multi-layer b〇ard) 俾 In a limited space, the use of interlayer connection technology (Interlayer c ο η necti ο η) to expand the available circuit layout area on the circuit board, thereby matching high Integrated circuit with circuit density needs to 'accommodate a larger number of circuits and components in the same unit area of the circuit board. 0 is a circuit that responds to the needs of high-performance chips such as microprocessors, chip sets, and graphics chips.' The board also needs to improve its functions of transmitting chip signals, improving bandwidth, and controlling impedance to achieve the development of high I / Q number packages. However, in line with the development direction of semiconductor packages, thin and short, multifunctional, high speed and high frequency, circuit boards have been developed towards fine lines and small apertures. The existing circuit board manufacturing process has been reduced from the traditional 100 micron line size, including wire width (Une width), line spacing (Space), and aspect ratio (Aspect rati〇), etc., to less than 30 microns, and continue to move towards more R & D with small line accuracy. also

200531578 五、發明說明(2) 為提高電路板之佈線精密度’業界發展出一種增層技 術(B u i 1 d - u p),亦即在一核心電路板(C〇 r e c i r c u i t b o a r d )表面利用線路增層技術交互堆疊多層絕緣層及線路 層,並於該絕緣層中開設導電盲孔(C ο n d u c ΐ i v e v i a)以供 上下層線路之間電性連接。其中,線路增層製程係影響電 路板線路密度的關鍵,依照現行技術,業者多以增層製程 來製作多層電路板。 請參閱第1 A至1 C圖,係採用一例如半加成法( Semi-additive process, SAP)之線路增層製程,首先, 提供一核心電路板1 0,並在其表面形成一絕緣層1 1,利用 雷射鑽孔(Laser dr i 1 1 ing)技術於該絕緣層1 1上形成開孔 1 1 0,以連通該核心電路板1 0之内層線路層1 2 (如第1 A圖所 示)。接著,於該絕緣層11上以無電解鍍銅方式形成一導 電晶種層1 3,在該晶種層1 3上施加一圖案化阻層ΐ 4後進行 電鍍,以於該晶種層1 3表面形成圖案化線路層1 5 (如第1 B 圖所示)。之後,剝離該阻層1 4並進行蝕刻,以移除先前 覆蓋於阻層1 4下之晶種層1 3 (如第ΐ c圖所示);如此,運用 此等步驟重複形成絕緣層及增層線路層,即製成一具有多 層線路結構之電路板。 惟,按一般習用藉由增層方式所製作之多層電路板, 若電子訊號欲由電路板上層傳送至下層時,該訊號必須從 上部增層線路層、上部線路層間之導電盲孔、而至核心電 路板上層線路層,再穿過該核心電路板内部之電鍵導通孔 (Plated through hole,PTH)、核心電路板下層線路層、200531578 V. Description of the invention (2) In order to improve the precision of the wiring of the circuit board, the industry has developed a layering technology (Bui 1 d-up), that is, using a circuit on the surface of a core circuit board to add layers. The technology alternately stacks multiple insulation layers and circuit layers, and opens conductive blind holes (C ο nduc ΐ ivevia) in the insulation layer for the electrical connection between upper and lower lines. Among them, the process of increasing the layer thickness of the circuit is the key to affecting the density of the circuit board. According to the current technology, many manufacturers use the increasing layer process to make multilayer circuit boards. Please refer to FIGS. 1A to 1C, which uses a layer-adding process such as a semi-additive process (SAP). First, a core circuit board 10 is provided, and an insulating layer is formed on the surface. 1 1. Use laser dr i 1 1 ing technology to form an opening 1 1 0 in the insulating layer 1 1 to communicate with the inner circuit layer 1 2 of the core circuit board 10 (such as the first A As shown). Next, a conductive seed layer 13 is formed on the insulating layer 11 by electroless copper plating, and a patterned resist layer ΐ 4 is applied on the seed layer 13 to perform electroplating on the seed layer 1. 3 Patterned circuit layer 1 5 is formed on the surface (as shown in Fig. 1B). After that, the resist layer 14 is peeled off and etched to remove the seed layer 1 3 previously covered under the resist layer 14 (as shown in FIG. Ϊ́c). In this way, using these steps to repeatedly form the insulating layer and Adding a circuit layer is to make a circuit board with a multilayer circuit structure. However, in the conventional multi-layer circuit board produced by the build-up method, if the electronic signal is to be transmitted from the upper layer of the circuit board to the lower layer, the signal must be from the upper build-up circuit layer, the conductive blind hole between the upper circuit layers, to The core circuit board has an upper circuit layer, and then passes through a keyed through hole (PTH) inside the core circuit board, the lower circuit layer of the core circuit board,

17659 全懋.ptd 第11頁 200531578 五、發明說明(3) 下部增層線路 電路板下層。 串擾(Cross-輪品質。另, 而於後續在該 製作其圖案化 (Pad)空間,^ 不僅浪費電路 因為線路佈局 >運用的靈活 再者,或 ’惟在該電鍍 具電鍍導通孔 後續在該電鍍 通孔之塞孔樹 製程中,金屬 ,由於該金屬 常由於該金屬 -藉由例如蚀刻 •之精度困擾 而由於可 腳化特性的等 路板製程彳占有 積體電路製程 層間之導電盲孔及下部增層線路層,方抵達 訊號傳遞路徑過長,易造成電感增強而導致 • t a 110或雜訊(N〇 i s e)產生,損及電性傳 由於核心電路板中形成有多數電鍵導通孔, 核心電路板上、下表面所形成之增層線路層 線路層時,必須自電鍍導通孔延伸出連接塾 |以形成導電盲孔(Conductive Via/, 士 板佈線面積,不利於微型化封裝趨勢 °此 時要閃避電鍍導通孔位置而影響到$ ’更會 J電路士 度。 %板窆 有直接 導通孔 之整體 導通孔 脂上形 層受塞 層係同 層之厚 等圖案 ,而無 縮小積 封裝件 封裝成 已縮小 在電鍍 上欲直 電路板 上形成 成一足 導通孔上形成導電f 接形成導 表面上形 導電盲孔 夠厚度之 影響而產 於該電路 或厚度不 孔樹脂 時形成 度過厚 化製程中,形成 法形成一縝密之 體電路(I C )面積 已曰漸成為封裝 本的2 0 %至5 0 %, 至0 · 0 9 // m且封 電盲 成一 ,因 金屬 生裂 板整 均等 導電 細線 且具 市場 因此 裝尺 孔時, 金屬層 而需在 層,以 損甚4 體表兩 問題, 線路及 路結構 有局密 上的主 在半導 寸亦不 孔 式 須先在 >而為供避免- 分 % 因 後續 惟 導 此 度與多後,且士 趙晶片: 接17659 Quan 懋 .ptd Page 11 200531578 V. Description of the invention (3) Lower layer-added circuit The lower layer of the circuit board. Crosstalk (Cross-wheel quality. In addition, in the subsequent production of its patterned (Pad) space, ^ not only waste the circuit because of the circuit layout > flexible use of the layout, or 'only in the plating plated through hole In the process of plugging the tree of the plated-through hole, the metal, because the metal is often troubled by the precision of the metal-for example, the equalization board process that can be pinned due to the pinnability of the circuit, and the conductive blindness between the layers of the integrated circuit process The hole and the lower layer increase the layer of the signal. The signal transmission path is too long, which can easily lead to increased inductance and ta 110 or noise. Damage to the electrical transmission is caused by the formation of the majority of the keys in the core circuit board. Hole, the core layer on the upper and lower surface of the circuit layer, the circuit layer must be extended from the plated through hole to form a connection 塾 | to form a conductive blind via (Conductive Via /, taxi board wiring area, not conducive to miniaturized packaging Trend ° At this time, it is necessary to avoid the position of the plated through hole and affect the circuit quality. The plate is blocked by the upper layer of the entire through hole grease with direct through holes. The layer is a pattern of the same layer thickness, and the non-reduced product package is packaged to have been reduced. On the electroplated circuit board, a conductive via is formed on the circuit board to form a sufficient conductive hole. The conductive conductive hole formed on the conductive surface has a sufficient thickness. Produced in the circuit or the thickness of the non-porous resin is too thick, the formation method to form a dense body circuit (IC) area has gradually become 20% to 50% of the package, to 0 · 0 9 // m and the electrical seal are integrated into one, because the metal raw split plate is uniformly conductive thin wires and has a market. Therefore, the metal layer must be on the layer to damage the two surface problems. The circuit and road structure are confidential. The master on the semi-conductor is also non-porous and must first be in> for the sake of avoidance-cent %% due to subsequent guidance, and after more and more, and Shi Zhao chip:

to

17659 全想.ptd 第12頁 200531578 五、發明說明(4) 幾乎與晶片同大(約僅為晶片之1. 2倍)時,如何開發可與 其搭配的細線路(F i n e c i r c u i t )與高線路密度之電路板結 構,同時不致提高過多製造成本,無疑是半導體產業乃至 其他相關電子產業進入下一世代技術之重要研發課題。 【發明内容】 鑒於以上所述習知技術之缺點,本發明之主要目的在 於提供一種電路板結構及其製法,係可直接在電鍍導通孔 上形成電性連接端,同時提供電路板其餘電性連接端與導 電線路具縝密之細線路結構。 本發明之再一目的在於提供一種電路板結構及其製法 ,藉以縮短導電盲孔佈線空間,並供該導電盲孔鍍層與電 鍍導通孔形成較佳之電性連接關係。 本發明之又一目的在於提供一種電路板結構及其製法 ,藉以縮短訊號傳輸路徑,以避免串擾、雜訊之產生而進 一步提昇電路板之電性品質。 本發明之又一目的在於提供一種電路板結構及其製法 ,藉以擴大電路板的線路佈局面積,並且提高層間線路( Interlayer circuits )之佈局靈活性。 為達成上述及其他目的,本發明揭露一種電路板結構 之製法,係包括:提供一芯層板,該芯層板表面具有金屬 層,且形成有多數之電鍍導通孔;於顯露出該芯層板之電 鍍導通孔端部表面形成導電層;圖案化該芯層板表面之金 屬層以形成一圖案化線路結構;於該線路結構上覆蓋一絕 緣層,共使該絕緣層形成有複數個開口 ,且至少一開口係17659 All thoughts. Ptd Page 12 200531578 V. Description of the invention (4) When it is almost the same size as the chip (about 1.2 times that of the chip), how to develop a fine circuit (Finecircuit) and high line density that can be used with it The circuit board structure without increasing excessive manufacturing costs is undoubtedly an important R & D issue for the semiconductor industry and other related electronics industries to enter the next generation of technology. [Summary of the Invention] In view of the shortcomings of the conventional technology described above, the main object of the present invention is to provide a circuit board structure and a manufacturing method thereof, which can directly form an electrical connection end on a plated through hole, while providing the remaining electrical properties of the circuit board. The connection end and the conductive circuit have a fine and thin circuit structure. Another object of the present invention is to provide a circuit board structure and a manufacturing method thereof, so as to shorten the wiring space of a conductive blind hole, and to provide the conductive blind hole plating layer and the plated through hole to form a better electrical connection relationship. Another object of the present invention is to provide a circuit board structure and a manufacturing method thereof, so as to shorten a signal transmission path to avoid crosstalk and noise generation and further improve the electrical quality of the circuit board. Another object of the present invention is to provide a circuit board structure and a manufacturing method thereof, so as to enlarge the circuit layout area of the circuit board and improve the layout flexibility of interlayer circuits. In order to achieve the above and other objectives, the present invention discloses a manufacturing method of a circuit board structure, which includes: providing a core board, the surface of the core board having a metal layer, and forming a plurality of plated through holes; and the core layer is exposed A conductive layer is formed on the end surface of the plated via hole of the board; the metal layer on the surface of the core board is patterned to form a patterned circuit structure; an insulating layer is covered on the circuit structure to form a plurality of openings in the insulating layer. , And at least one opening is

17659 全懋.ptd 第13頁 200531578 五、發明說明(5) 外露出該電鍍導通孔端部,並形成一阻層以覆蓋住另一表 面其餘開口;於外露出該絕緣層開口之電鍍導通孔端部形 成一金屬層;以及移除該阻層。如此,即可選擇性在部分 之電鍍導通孔上直接形成一供後續作用為電性連接端之金 屬層。之後,復可在顯露出該絕緣層開口之線路結構部分 (即供後續作為該電路板與外部電性導接之電性連接端) 表面上形成一金屬保護層,俾供該電路板得以有效與導電 元件電性連接,而該絕緣層即可為一拒鲜層。 該電鍍導通孔端部表面上之導電層可透過直接鍍覆方 _ (Direct plating,DP)以在該電鍵導通孔之塞孔絕緣 部分形成一例如鈀之導電膜,或利用化學沈積方式以在該 電鍍導通孔之塞孔絕緣部分形成一例如銅之導電膜;之後 亦或可利用電鍍方式於該芯層板整體表面形成一金屬薄層 ,俾於後續得以透過電鍍方式而在該電鍍導通孔之端部上 直接形成一作為電性連接端之金屬層,復可利用電鍍導線 或化學沈積等方式,以在外露出圖案化絕緣層(如拒銲層 )之電性連接端上形成金屬保護層,以保護該電性連接端 避免受外界環境侵害,並提供其與導電元件(如銲線、錫 .球、或金屬凸塊等)間良好之電性連接。此外,在該電鍍 _通孔之端部形成電性連接端後,亦可作為後續線路增層 結構中承接導電盲孔之用,俾得以直接在電鍍導通孔上直 接形成導電盲孔,以縮短導電途徑,且有效增加線路佈設 空間,提升線路佈局靈活度,之後,復可持續進行線路增 層製程,俾形成一具有多層線路結構之電路板。17659 Quan 懋 .ptd Page 13 200531578 V. Description of the Invention (5) The end of the plated through hole is exposed, and a resistance layer is formed to cover the remaining opening on the other surface; the plated through hole is exposed to the insulation layer opening. Forming a metal layer at the end; and removing the resist layer. In this way, a metal layer can be selectively formed directly on some of the plated through holes for subsequent use as an electrical connection terminal. After that, a metal protective layer can be formed on the surface of the circuit structure part (that is, the electrical connection terminal for the subsequent electrical connection between the circuit board and the outside) that exposes the opening of the insulation layer, so that the circuit board can be effectively used. It is electrically connected to the conductive element, and the insulating layer can be a fresh-repelling layer. The conductive layer on the surface of the end of the plated via hole can be formed by direct plating (DP) to form a conductive film such as palladium on the plug insulating portion of the key via hole, or by chemical deposition to A conductive film, such as copper, is formed in the plug hole insulation portion of the plated through hole; afterwards, a thin metal layer may be formed on the entire surface of the core board by electroplating, which can be subsequently plated through the plated through hole by electroplating. A metal layer as an electrical connection terminal is directly formed on the end portion, and a metal protective layer can be formed on the electrical connection end of the patterned insulating layer (such as a solder resist layer) by using electroplated wires or chemical deposition. In order to protect the electrical connection end from the external environment, and to provide a good electrical connection between it and conductive elements (such as welding wires, tin balls, or metal bumps, etc.). In addition, after the electrical connection end is formed at the end of the plated-through hole, it can also be used to receive conductive blind holes in the subsequent layer buildup structure, so that conductive blind holes can be directly formed directly on the plated through-holes to shorten Conductive pathway, and effectively increase the wiring layout space, improve the flexibility of the layout of the circuit, and then continue to carry out the process of adding layers to form a circuit board with a multilayer circuit structure.

17659 全懋.ptd 第14頁 200531578 、發明說明(6) 亦即’透過上述製程 層覆蓋住欲形成細線路之 孔之端部形成金屬層,而 線路之製程,同時^ 由在電鑛導通孔上;;: 盲孔所需之電性連接端之 有效提升線路佈線之资 此外,經前述製程^ 係包括:一芯層板,其 數貫穿該芯層板之電鍍導 具有多數之導電線路與電 性連接端係形成於該電鍍 形成在該線路結構上,該 出該電性連接端,且至^ 部之電性連接端;以及一 絕緣層開口之電性連接端 成如段製程之多層電路板 因此’藉由本發明之 性在部分欲形成電性連接 性連接端,以供後續接置 其它電子元件(半導體晶 可於該電鍍導通孔上之電 構之導電盲孔,以減少習 via)時’所需延伸出連接 ,本發明係預先 區域,再選擇性 不致影響其餘線 一步應用在線路 之電性連接端, 設置與接線所佔 〇 本發明亦揭示出 表面形成有圖案 通孔,其中,該 鍍導通孔電性導 導通孔上;一圖 絕緣層形成有複 一開口係對應至 金屬保護層,係 上表面。另,該 〇 電路板結構及其 端之電鍍導通孔 有導電元件,俾 片或電路板)之 性連接端直接形 知形成導電盲孔 墊(Pad)之空間 利用拒銲層及阻 於部分電錢導通 路佈局空間與細 增層製程中,藉 以減少承接導電 電路板空間,俾 一種電路板結構 化線路結構與多 圖案化線路結構 通,而至少一電 案化絕緣層,係 數個開口以外露 該電鍍導通孔端 形成於外露出該 芯層板可為一完 製法,係可選擇 上直接形成該電 提供該電路板與 電性導接,亦或 成有線路增層結 ( Conductive 藉以增加佈線 17659 全懋.ptd17659 Quan 懋 .ptd Page 14 200531578, description of the invention (6) That is, 'the metal layer is formed by covering the end of the hole where the fine circuit is to be formed through the above process layer, and the process of the circuit is上 : ;: The electrical connection terminals required for blind holes effectively improve the wiring of the circuit. In addition, the aforementioned process ^ includes: a core board, the number of which runs through the core board has a large number of conductive lines and The electrical connection end is formed on the circuit structure formed by the electroplating, the electrical connection end is out, and the electrical connection end to ^; and the electrical connection end of an insulation layer opening is a multi-layered process. The circuit board therefore 'uses the nature of the present invention to form electrical connection terminals in some parts for subsequent connection of other electronic components (semiconductor crystals can be electrically conductive blind holes on the electroplated vias to reduce the habit of via ) When the connection needs to be extended, the present invention is a pre-area, and then the selectivity does not affect the remaining wires in one step applied to the electrical connection end of the line, and the installation and wiring account. The invention also reveals the surface Patterned into a through hole, wherein the plated vias of electrically conductive vias; FIG insulating layer is formed with a double opening system corresponds to a metallic protective layer was formed on the surface. In addition, the circuit board structure and its plated through holes have conductive elements, cymbals, or circuit boards. The sexual connection ends of the circuit board are directly shaped to form a conductive blind hole pad (Pad). In the layout space of the money conduction path and the thin layer increasing process, in order to reduce the space for receiving conductive circuit boards, a circuit board structured circuit structure is connected to a multi-patterned circuit structure, and at least one electrically-insulated insulation layer is exposed. The electroplated via hole end is formed to expose the core layer board. It can be a finished method. It is optional to directly form the electricity to provide the circuit board with electrical conduction, or to add a layer to increase the wiring. 17659 Full 懋 .ptd

第15頁 200531578 五、發明說明(7) 路密度與靈活性,並可縮短導電路徑,減少電感、串擾及 雜訊產生;此外,該電鍍導通孔上之電性連接端係於製程 中獨立形成,而不影響該電路板導電線路之製程,藉以避 免習知技術中在電鍍導通孔上欲形成電性連接端時,必需 在整體電路板上形成一厚度過厚或厚度不均之金屬層,導 致後續在圖案化製程中形成導電線路及電性連接端之精度 困擾,而無法形成一具細線路結構之電路板等缺失,而得 以提供一具細線路(F i n e c i r c u i t)與高佈線密度之電路 板。 _實施方式】 以下係藉由特定的具體實施例說明本發明之實施方式 ,熟習此技藝之人士可由本說明書所揭示之内容輕易地瞭 解本發明之其他優點與功效。本發明亦可藉由其他不同的 具體實施例加以施行或應用,本說明書中的各項細節亦可 基於不同觀點與應用,在不悖離本發明之精神下進行各種 修飾與變更。 以下即以第2A圖至第2K圖詳細說明本發明之電路板結 構及其製法之較佳實施例。其中,須注意的是,該等圖式 均為簡化之示意圖,僅以示意方式說明本發明之電路板架 •。惟該等圖式僅顯示與本發明有關之元件,其所顯示之 元件非為實際實施時之態樣,其實際實施時之元件數目、 形狀及尺寸比例為一種選擇性之設計,且其元件佈局型態 可能更行複雜。 如第2A及2B圖所示,首先,提供一表面形成有金屬薄Page 15 200531578 V. Description of the invention (7) Circuit density and flexibility, and can shorten the conductive path, reduce inductance, crosstalk and noise generation; In addition, the electrical connection ends on the plated vias are formed independently in the manufacturing process Without affecting the manufacturing process of the conductive circuit of the circuit board, in order to avoid the formation of electrical connection ends on the plated through holes in the conventional technology, it is necessary to form a metal layer with an excessively thick or uneven thickness on the entire circuit board. As a result, the precision of the conductive lines and electrical connection ends in the subsequent patterning process is troubled, and a circuit board with a fine circuit structure cannot be formed, so that a circuit with fine circuits and high wiring density can be provided. board. _Embodiment] The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. Hereinafter, the preferred embodiments of the circuit board structure and the manufacturing method of the present invention will be described in detail with reference to FIGS. 2A to 2K. Among them, it should be noted that these drawings are simplified schematic diagrams, and the circuit board frame of the present invention is only illustrated schematically. However, the drawings only show the elements related to the present invention. The elements shown are not the actual implementation. The number, shape, and size ratio of the elements during actual implementation are an optional design. The layout pattern may be more complicated. As shown in Figures 2A and 2B, first, a surface is provided with a thin metal

17659 全懋.ptd 第16頁 200531578 五、發明說明(8) 層之芯層板2 0,該芯層板2 0亦可為一完成前處理之多層電 路板。於本實施例之圖式中,該芯層板2 0係由一絕緣層 2 0 0及形成於該絕緣層2 0 0表面之金屬薄層2 0 1所構成;復 以機械或雷射鑽孔等方式於該芯層板2 0中鑽設多個貫穿孔 2 0 2 (如第2 B圖所示)。其中,該絕緣層2 0 0可為環氧樹脂 (Epoxy resin)、聚乙醯胺(Polyimide)、氰酉旨(17659 Quan 懋 .ptd Page 16 200531578 V. Description of the invention (8) The core board 20 is a layer, and the core board 20 can also be a multi-layer circuit board with pre-processing completed. In the drawing of this embodiment, the core layer board 20 is composed of an insulating layer 200 and a thin metal layer 2 01 formed on the surface of the insulating layer 200; further, a mechanical or laser drill is used. A plurality of through holes 2 0 2 are drilled in the core layer plate 20 in a manner such as holes (as shown in FIG. 2B). The insulating layer 200 may be epoxy resin, polyimide, cyanocyanine (

Cyanate Ester)、破璃纖維、雙順丁烯二酸醯亞胺/三氮 阱(Bismaleimide Triazine,BT)或混合環氧樹脂與玻璃 纖維之F R 5材質所製成,該金屬薄層2 0 1—般係以導電性較 佳之銅(Cu )為主,以作為訊號傳遞的導線材料,且該金屬 薄層2 0 1可先壓合或沉積於該絕緣層2 0 0上,或使用樹脂壓 合銅(Resin coated copper, R C C)予以製作。本實施例 採用一樹脂壓合銅箔(RCC)為例進行說明。 如第2C圖所示,接著,利用物理氣相沈積(PVD)、 化學氣相沈積(CVD)、無電電鍍或化學沈積等方式,例 如滅鑛(Sputtering)、蒸鑛(Evaporation)、電弧蒸 氣沈積(Arc vapor deposit ion)、離子束濺鍍(Ion beam sputter ing)、雷射熔散沈積(La s e r ab 1 a t i on deposition)、電漿促進之化學氣相沈積或無電電鑛等, 以於該芯層板2 0及其貫穿孔2 0 2表面形成一導電層(未圖示 ),俾藉由該導電層作為電流傳導路徑,以在該芯層板2 0 表面上以及於該貫穿孔2 0 2孔壁上電鍍形成有一具足夠厚 度之金屬層203。 如第2 D圖所示,復以一填充材2 0 4 (如油墨樹脂等)填Cyanate Ester), broken glass fiber, bismaleimide / imide / triazine (BT) or FR 5 material mixed with epoxy resin and glass fiber, the metal thin layer 2 0 1 -Generally, copper (Cu) with better conductivity is used as the wire material for signal transmission, and the thin metal layer 2 01 can be laminated or deposited on the insulating layer 2 0 or resin pressure Resin coated copper (RCC). This embodiment is described by using a resin laminated copper foil (RCC) as an example. As shown in Figure 2C, next, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition are used, such as sputtering, evaporation, and arc vapor deposition. (Arc vapor deposit ion), ion beam sputtering (Ion beam sputter ing), laser fusing deposition (La ser ab 1 ati on deposition), plasma-assisted chemical vapor deposition or electroless ore, etc. A conductive layer (not shown) is formed on the surface of the core layer board 20 and the through hole 2, and the conductive layer is used as a current conduction path to form a conductive layer on the surface of the core board 20 and the through hole 2. A metal layer 203 having a sufficient thickness is electroplated on the wall of the hole. As shown in Figure 2D, fill with a filling material 2 0 4 (such as ink resin)

17659 全懋.ptd 第17頁 200531578 五、發明說明(9) 滿該貫穿孔2 0 2之殘留空隙,俾形成一電鍍導通孔(PTH) 2 0 5,藉以電性導通該芯層板2 0上下表面之金屬層2 0 3。 如第2 E圖所示,於顯露出該芯層板2 0之電鍍導通孔 20 5端部表面形成一導電層。其玎透過無電電鍍等方式先 在該芯層板2 0之表面形成一導電層(未圖示),俾藉由該導 電層作為電流傳導路徑,以在該芯層板2 0表面(包含該電 鍍導通孔2 0 5之填充材2 0 4端部)上電鍍形成一例如銅(cu ) 之導電薄層21 (厚度通常可為3至10# m)。此外,如第2E, 圖所示,亦可於該芯層板20上進行直接鍍覆方式(Direct _1 at ing, DP)等製程,以在該芯層板之表面上形成一例如 鈀(P d )之導電膜2 0 3 a,再經化學剝除製程,以使該鈀金屬 層依附於該電鍵導通孔2 0 5之填充材2 0 4端部表面;亦或進 行化學銅等製程,以使該電鍍導通孔2 0 5之填充材2 0 4端部 表面覆蓋一導電膜203a。 其中,該電鍍導通孔20 5之填充 材20 4端部表面所形成之導電薄層21或導電膜203a,主要 係作為電流傳導路徑,俾於後續進行電鍍製程時,得以選 擇性在該電鍍導通孔2 0 5上形成有電鍍金屬層。以下後續 製程說明,主要係以在該芯層板2 0上形成一例如銅(c u )之 導電薄層2 1加以説明,而於該電鍍導通孔2 0 5之填充材2 0 4 囑部表面形成可如鈀或鋼之導電膜2 0 3 a,其後續製程係相 近於以下所述之製程步驟,故於此不再多所贅述,先予敘 明。 如第2 F圖所示,進行線路圖案化製程,以於該芯層板 表面之金屬層以形成一圖案化線路結構。其係可於該芯層17659 Quan 懋 .ptd Page 17 200531578 V. Description of the invention (9) The residual void of the through hole 2 0 2 is filled, and a plated through hole (PTH) 2 0 5 is formed, thereby electrically conducting the core board 2 0 Upper and lower surface metal layers 2 0 3. As shown in FIG. 2E, a conductive layer is formed on the surface of the end of the plated-through hole 20 5 where the core layer board 20 is exposed. First, a conductive layer (not shown) is formed on the surface of the core board 20 by electroless plating or the like, and the conductive layer is used as a current conduction path to cover the surface of the core board 20 (including the A conductive thin layer 21 (thickness may generally be 3 to 10 # m), such as copper (cu), is electroplated on the end portion of the filling material 204 of the plated-through hole 2 0 5. In addition, as shown in FIG. 2E, a process such as a direct plating method (Direct _1 at ing, DP) can also be performed on the core board 20 to form, for example, palladium (P d) the conductive film 203a, and then undergo a chemical stripping process so that the palladium metal layer adheres to the end surface of the filling material 204 of the key via 205; or a process such as chemical copper is performed, A conductive film 203a is covered on the surface of the end of the filling material 204 of the plated-through hole 205. Among them, the conductive thin layer 21 or conductive film 203a formed on the end surface of the filling material 20 4 of the plated through hole 20 5 is mainly used as a current conduction path, and can be selectively conducted in the plated conductive during subsequent plating processes. A plated metal layer is formed on the holes 2 0 5. The following description of the subsequent process is mainly based on forming a conductive thin layer 21 such as copper (cu) on the core layer board 20, and filling the surface of the filling material 2 0 4 on the plated through hole 2 0 5 A conductive film 203a, which can be made of palladium or steel, is formed. The subsequent process is similar to the process steps described below, so it will not be described in detail here. As shown in FIG. 2F, a circuit patterning process is performed to form a patterned circuit structure on the metal layer on the surface of the core board. It can be in the core layer

17659 全懋.ptd 第18頁 200531578 五'發明說明(10) —— 板20上形成一例如乾膜或光阻之阻層(未圖示),並經過晛 光(Exposure)、顯影(DeVei〇pment)等製程,以使該阻/ 形成有多數開口以外露出該芯層板20之表面金屬層,^ 由蝕刻製程以移除未為該阻層所覆蓋之金屬層部分,藉^ 形成一圖案化線路結構2 2,其中,該圖案化線路結構&可 包含有多數細線路結構。 1 如第2 G圖所示,於該線路結構2 2上覆蓋一絕緣層2 3, 並使該絕緣層2 3形成有複數個開口 2 3 0,且至少一開口 2 3 〇 係外露出該電鍍導通孔2 0 5端部。其中,該絕緣層2 3之材 質可為一例如綠漆之拒銲層,而該些絕緣層開口 2 3 〇即用 以外露出後續形成電性連接端之部份電路板導電線路。 如第2 Η圖所示,形成一阻層2 4以覆蓋住未外露出該電 鍍導通孔2 0 5端部之部分絕緣層開口 2 3 0。該阻層2 4可為_ 乾膜或光阻,以供後續進行電鍍製程時作為電鍍阻層之用 〇 如第2 I圖所示,於外露出該絕緣層開口 2 3 0之電鍍導 通孔20 5端部形成一金屬層25。其可透過電鍍導線等方式 ,以在未被該阻層2 4所覆蓋住之部分絕緣層開口 2 3 0中之 電鍍導通孔20 5上形成一電鍍金屬層25,如此,即可選擇 性在部分之電鍍導通孔2 0 5上直接形成一供後續作用為電 性連接端之金屬層2 5。其中,由於該電錢金屬層2 5僅係選 擇性形成於部分該電鍍導通孔2 0 5上,因此除了可在電鍍 導通孔2 0 5上形成有電性連接端外,忠層板其餘區域上之 圖案化線路可保有較細緻之線路結構。17659 Quan 懋 .ptd Page 18 200531578 Five 'invention description (10)-a resist layer (not shown) such as a dry film or a photoresist is formed on the board 20, and it is subjected to exposure, development (DeVei). pment) and other processes so that the barrier / formation has a majority of the openings to expose the surface metal layer of the core layer board 20, and an etching process is performed to remove a portion of the metal layer that is not covered by the barrier layer to form a pattern by ^ The patterned circuit structure 22 may include a plurality of fine circuit structures. 1 As shown in FIG. 2G, an insulating layer 2 3 is covered on the circuit structure 22, and the insulating layer 23 is formed with a plurality of openings 2 3 0, and at least one opening 2 3 0 is exposed to the outside. Ends of the plated-through holes 205. Wherein, the material of the insulating layer 23 may be a solder resist layer such as green paint, and the insulating layer openings 2 3 0 are used to expose part of the conductive circuit of the circuit board that subsequently forms the electrical connection end. As shown in FIG. 2 (a), a resist layer 24 is formed to cover a part of the insulation layer opening 230 which does not expose the end of the plated-through hole 205. The resist layer 24 can be a dry film or a photoresist, which can be used as a plating resist layer in the subsequent plating process. As shown in FIG. 2I, the plating vias of the insulating layer opening 2 3 0 are exposed outside. A metal layer 25 is formed at the end of 20 5. It can form a plated metal layer 25 on the plated through hole 20 5 in the part of the insulation layer opening 2 3 0 which is not covered by the resist layer 24 by using a plating wire or the like. A metal layer 25 is directly formed on a part of the plated-through hole 25 for subsequent use as an electrical connection end. Among them, since the electric money metal layer 25 is selectively formed only on a part of the plated through-holes 205, in addition to the electrical connection ends that can be formed on the plated through-holes 205, the rest of the layered board The patterned circuit above can maintain a more detailed circuit structure.

17659 全懋.ptd 第19頁 200531578 五、發明說明(π) 如第2 J圖所示,在該電鐘導通孔2 0 5上形成金屬層2 5 後,即可將該阻層2 4移除,俾將該芯層板表面之圖案化線 路結構中欲作為電性連接端之部分(包含選擇性形成在該 電鍍導通孔上之金屬層2 5)顯露於該絕緣層(如拒銲層)2 3 之開口 2 3 0 ◦ 如第2 K圖所示,之後,復可在顯露出該絕緣層開口 2 3 0 之導電金屬(即供後續作為該電路板與外部電性導接之電 性連接端)表面上形成一金屬保護層2 6。其可藉由電鍍導 線方式以於顯露出該絕緣層開口 2 3 0之導電金屬上表面形 _ 一例如鎳/金之金屬保護層2 6,俾藉由該金屬保護層2 6 提供電性連接端有效與導電元件(如銲線、錫球、或金屬 凸塊等)電性連接。當然,於電性連接端上形成金屬保護 層之方式,並非以前述之電鍍導線方式為限,另可採用化 學沈積(如化學鎳/金製程)等方式形成,惟該金屬保護層 之形成方式,僅係用以例示而非用以限定本發明之可實施 範疇。 此外,請參閱第2 K ’圖,其係如先前第2 E ’圖所示,在 該電鍍導通孔2 0 5之填充材2 0 4端部表面形成如鈀之導電膜 時,復經由前述製程以選擇性在部分電鍍導通孔2 0 5上形 费供後續作用為電性連接端之金屬層2 5,並在顯露出絕緣 層(拒銲層)開口 2 3 0之電性連接端上表面形成有金屬保護 層2 6,以製得一電路板。 因此,上述本發明之電路板結構之製程,主要係在該 電鍵導通孔之端部表面上透過直接鍵覆方式(Direct17659 Quan 懋 .ptd Page 19 200531578 V. Description of the invention (π) As shown in Figure 2J, after the metal layer 2 5 is formed on the electrical clock via 2 0 5, the resistive layer 2 4 can be moved. In addition, the part of the patterned circuit structure on the surface of the core board that is to be used as an electrical connection terminal (including the metal layer 25 selectively formed on the plated through hole) is exposed to the insulating layer (such as a solder resist layer). ) 2 3 of the opening 2 3 0 ◦ As shown in Figure 2K, after that, the conductive metal of the opening 2 3 0 of the insulating layer can be exposed (that is, for subsequent electrical connection between the circuit board and the external electrical connection) Sexual connection end) a metal protective layer 26 is formed on the surface. It can be formed on the top surface of the conductive metal by exposing the opening 2 3 0 of the insulating layer by electroplated wires. A metal protective layer such as nickel / gold 2 6 can provide electrical connection through the metal protective layer 2 6. The terminal is effectively electrically connected to a conductive element (such as a wire, a solder ball, or a metal bump, etc.). Of course, the method of forming a metal protective layer on the electrical connection end is not limited to the aforementioned electroplated wire method. It can also be formed by chemical deposition (such as chemical nickel / gold process), but the method of forming the metal protective layer , It is only for the purpose of illustration, not to limit the implementable scope of the present invention. In addition, please refer to Fig. 2K ', which is shown in the previous Fig. 2E'. When a conductive film such as palladium is formed on the end surface of the filling material 2 0 4 of the plated through hole 2 0 5, it passes through the foregoing The manufacturing process selectively forms part of the plated through-holes 2 0 5 for subsequent use as the metal layer 25 of the electrical connection end, and on the electrical connection end which exposes the insulating layer (solder resist) opening 2 3 0 A metal protective layer 26 is formed on the surface to prepare a circuit board. Therefore, the above-mentioned manufacturing process of the circuit board structure of the present invention is mainly performed by direct bonding on the end surface of the key via hole (Direct

17659 全懋.ptd 第20頁 200531578 五、發明說明(12) plat ing, DP)或化學沈積方式以使該電鍍導通孔之塞孔絕 緣部分覆蓋一例如鈀或銅之導電膜,亦或經由電鍍方式形 成一導電薄層,俾得利用電鍍導線以選擇性在該電鍍導通 孔之端部上形成電性連接端,復可藉由電鍍導線或化學沈 積等方式’以在外露出圖案化絕緣層(如拒鲜層)之電性 連接端上形成金屬保護層,以保護該電性連接端避免受外 界環境侵害,並提供其與導電元件(如銲線、錫球、或金 屬凸塊等)間良好之電性連接。 請參閱第2 K及2 K ’圖所示,透過前述製程,本發明亦 揭示一種電路板結構,係包括有一芯層板2 0,其表面形成 有圖案化線路結構2 2與多數貫穿該芯層板2 0之電鍍導通孔 2 0 5,其中,該圖案化線路結構2 2具有多數之導電線路與 電鍍導通孔電性導通,而至少一電性連接端係形成於該電 鍍導通孔2 0 5上;一圖案化絕緣層2 3,係形成在該線路結 構2 2上,該絕緣層2 3形成有複數個開口 2 3 0以外露出該電 性連接端,且至少一開口 2 3 0係對應至該電鍍導通孔2 0 5端 部之電性連接端;以及一金屬保護層2 6,係形成於外露出 該絕緣層開口 2 3 0之電性連接端表面。 因此,本發明係可選擇性於部分電鍍導通孔上直接形 成電性連接端,且預先利用阻層覆蓋住先前製程中所形成 之細線路結構,而不致影響其餘線路佈局空間與細線路之 製程,亦即,該電鍍導通孔上之電性連接端係於其餘同層 線路結構形成後再予製作,且該電性連接端即可作為電路 板後續接置導電元件用。17659 Quan 懋 .ptd Page 20 200531578 V. Description of the invention (12) plat ing (DP) or chemical deposition method so that the plug insulating part of the plated through hole is covered with a conductive film such as palladium or copper, or by electroplating A conductive thin layer is formed by using electroplated wires to selectively form electrical connection ends on the ends of the plated vias. The patterned insulation layer can be exposed to the outside by electroplating wires or chemical deposition ( (Such as antirefreshment layer) to form a metal protective layer on the electrical connection end to protect the electrical connection end from the external environment, and provide a space between it and conductive components (such as solder wires, solder balls, or metal bumps, etc.) Good electrical connection. Please refer to FIG. 2K and 2K ′. Through the foregoing process, the present invention also discloses a circuit board structure, which includes a core layer board 20, and a patterned circuit structure 22 is formed on the surface, and most of the cores run through the core. The plated-through holes 2 0 5 of the layer plate 20, wherein the patterned circuit structure 22 has most of the conductive lines and the plated-through holes electrically connected, and at least one electrical connection end is formed in the plated-through holes 2 0 5; a patterned insulating layer 23 is formed on the circuit structure 22, the insulating layer 23 is formed with a plurality of openings 2 3 0 to expose the electrical connection terminal, and at least one opening 2 3 0 is The electrical connection end corresponding to the end of the plated through hole 205; and a metal protective layer 26 is formed on the surface of the electrical connection end which exposes the opening 230 of the insulation layer. Therefore, the present invention can selectively form an electrical connection end directly on a part of the plated through-holes, and use a resistive layer to cover the fine line structure formed in the previous process in advance without affecting the remaining line layout space and the process of the fine line. That is, the electrical connection ends on the plated through-holes are made after the rest of the same layer circuit structure is formed, and the electrical connection ends can be used as subsequent connection of conductive elements on the circuit board.

17659 全懋.ptd 第21頁 200531578 五、發明說明(13) 此外’如第3圖所示,方γ爲9 π + 之端部形成有電性連接端後,亦曰 之電鍵導通孔3匕5 m承接導電盲孔32用,:得::: =線路增層結構 上形成導電“L32,如此,;可: = = ;導通孔305 ”增加線路佈設空間,提升:ς:局、電=,J =進行線路增…,俾形成-具有多I線:;構: 鼴^ =本發明先前之圖示係以雙層板作為1明太芥 _之製程亦可應用於多層 =:=為祝明,本發 係可為一已完成前p制 ’、 則圖式之該芯層板 一具多層線路社構^ ^ ^之夕層板,即可依前述製程形成 應用本發明前m!板’如第4A圖及切圖所示,係為 ,以及具六層線==仔之具四層線路結構之電路板40A 非侷限於前述之;:構之電路板4〇β。當然本發明之應用 用於任一具多;:二蛀四層、或六層電路板,實際係可應 因此,藉構之電路板。 性在部分欲形電路板結構及其製法,係可選擇 性連接端,以ί連接端之電鍍導通孔上直接形成該電 • 仏後續接置有導電元件以提供該電路板與其 千(半導體晶片或電路板)之電性導接,亦4可 Γίϊ;!通孔上之電性連接端直接形成有線路增層i構 ^ ¥ ’ M及減少習知形成導電盲孔(Conductive17659 Quan 懋 .ptd Page 21 200531578 V. Description of the invention (13) In addition, as shown in Fig. 3, an electrical connection end is formed at the end of the square γ of 9 π +, which is also referred to as a conductive via of a key. For 5 m to accept conductive blind holes 32, we have ::: = a conductive "L32" is formed on the layer buildup structure of the circuit, so :; = =; vias 305 "increase the wiring layout space and enhance: ς: bureau, electrical = , J = Line increase ..., 俾 formation-with multiple I lines :; Structure: 鼹 ^ = The previous illustration of the present invention uses a double-layer board as a 1-mustard _ process can also be applied to multiple layers =: = wishes It is clear that the present system can be a pre-made p ', and the core board of the diagram has a multilayer circuit structure. It can be formed in accordance with the foregoing process to apply the pre-m! Board of the present invention. As shown in FIG. 4A and the cut view, the circuit board 40A having a four-layer circuit structure with six-layer wires == is not limited to the foregoing; the structure of the circuit board 4β. Of course, the application of the present invention is applicable to any two-to-four-layer or six-layer circuit board. Therefore, the circuit board can be constructed accordingly. In the structure of part-shaped circuit board and its manufacturing method, it is optional to connect the end, and the electrical connection is formed directly on the plated through hole of the connection end. 仏 The conductive element is subsequently connected to provide the circuit board and its semiconductor (semiconductor wafer). Or circuit board) electrical connection, also can be Γίϊ ;! The electrical connection end on the through hole is directly formed with a line build-up structure ^ ¥ 'M and reduce the conventional formation of conductive blind holes (Conductive

Via日守’所需延伸出連接墊(Pad)之空間,藉以增加佈線 路岔度與靈活性,並可縮短導電路徑,減少電感、串擾及Via Ri Shou ’needs to extend the space of the connection pad (Pad), in order to increase the degree of routing and flexibility, and shorten the conductive path, reduce inductance, crosstalk and

17659 全懋.ptd17659 Full 懋 .ptd

IH 第22頁 200531578 五、發明說明(14) 雜訊產生;此外,該電鍍導通孔上之電性連接端於製程中 係獨立形成,而不影響該電路板導電線路之製程,藉以避 免習知技術中在電鍍導通孔上欲形成電性連接端時,必需 在整體電路板上形成一厚度過厚或厚度不均之金屬層,導 致後續在圖案化製程中形成導電線路及電性連接端之精度 困擾,而無法形成一細線路結構等缺失,俾提供一具細線 路(Fine Circuit)與高佈線密度之電路板。 以上所述僅為本發明之較佳實施例而已,並非用以限 定本發明之實質技術内容範圍,本發明之實質技術内容係 廣義地定義於下述之申請專利範圍中,任何他人完成之技 術實體或方法,若是與下述之申請專利範圍所定義者係完 全相同,亦或為同一等效變更,均將被視為涵蓋於此申請 專利範圍中。IH Page 22 200531578 V. Explanation of the invention (14) Noise is generated; in addition, the electrical connection ends of the plated through holes are formed independently during the manufacturing process, without affecting the manufacturing process of the conductive circuit of the circuit board, so as to avoid habituation In the technology, when an electrical connection terminal is to be formed on a plated-through hole, a metal layer with an excessively thick or uneven thickness must be formed on the entire circuit board, which leads to the subsequent formation of conductive lines and electrical connection terminals in the patterning process. Accuracy is troubled, and a thin circuit structure cannot be formed. Therefore, a circuit board with fine circuits and high wiring density is provided. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of patent applications described below, and any technology completed by others. Entities or methods that are completely the same as those defined in the scope of patent application described below, or the same equivalent changes, will be considered to be covered by this patent application scope.

17659 全懋.ptd 第23頁 200531578 圖式簡單說明 【圖式簡單說明】 第1 A圖至第1 C圖係習知之半加成法製程流程示意圖; 第2 A圖至第2 K圖係本發明之電路板結構製法之製程剖 面示意圖; 第2 E ’圖及第2 K ’圖係本發明之電路板結構製法另一實 施悲樣之剖面不意圖, 第3圖係本發明之電路板結構製法應用於增層結構之 剖面示意圖;以及 第4A圖及第4B圖係本發明之電路板結構製法應用於多 0板之剖面示意圖。 10 核心電路板 11 絕緣層 1 10 開孔 12 内層線路層 13 晶種層 14 阻層 15 圖案化線路層 20 芯層板 #)0 絕緣層 201 金屬薄層 2 0 2 貫穿孔 2 0 3 金屬層 2 0 3a 導電膜17659 Quan 懋 .ptd Page 23 200531578 Simple description of the drawings [Simplified illustration of the drawings] Figures 1 A to 1 C are the conventional semi-additive process flow diagrams; Figures 2 A to 2 K are the original Schematic cross-sectional view of the invention's circuit board structure manufacturing method; Figures 2E 'and 2K' are schematic diagrams of another embodiment of the circuit board structure manufacturing method of the present invention, and Figure 3 is a circuit board structure of the present invention. A schematic sectional view of the manufacturing method applied to the build-up structure; and FIGS. 4A and 4B are schematic sectional views of the manufacturing method of the circuit board structure of the present invention applied to the multi-board. 10 Core circuit board 11 Insulation layer 1 10 Opening hole 12 Inner circuit layer 13 Seed layer 14 Resistance layer 15 Patterned circuit layer 20 Core board #) 0 Insulation layer 201 Thin metal layer 2 0 2 Through hole 2 0 3 Metal layer 2 0 3a conductive film

17659 全懋.ptd 第24頁 20053157817659 Full 懋 .ptd Page 24 200531578

圖式簡單說明 204 填 充 材 205 電 鍍 導 通 子L 21 導 電 薄 層 22 線 路 結 構 23 絕 緣 層 230 開 π 24 阻 層 25 金 屬 層 26 金 屬 保 護 層 30 芯 層 板 305 電 鍍 導 通 孔 31 線 路 增 層 結構 32 導 電 盲 孔 40A 四 層 電 路 板 40B 六 層 電 路 板 17659 全懋.ptd 第25頁Brief description of the drawing 204 Filler material 205 Plating conductor L 21 Conductive thin layer 22 Circuit structure 23 Insulation layer 230 Open π 24 Resistive layer 25 Metal layer 26 Metal protective layer 30 Core board 305 Plating via 31 Circuit build-up structure 32 Conductive Blind hole 40A Four-layer circuit board 40B Six-layer circuit board 17659 Full 懋 .ptd Page 25

Claims (1)

200531578 六、申請專利範圍 ‘ 1. 一種電路板結構之製法,係包括: 提供一芯層板,該芯層板表面具有金屬層,且該 芯層板形成有多數之電鍍導通孔; 於顯露出該芯層板之電鍍導通孔端部表面形成導 電層; 圖案化該芯層板表面之金屬層以形成一圖案化線 路結構; 於該線路結構上覆蓋一絕緣層,並使該絕緣層形 成有複數個開口,且至少一開口係外露出該電鍍導通 _孔端部;以及 於外露出該絕緣層開口之電鍍導通孔端部形成一 金屬層以作為電性連接端。 2. 如申請專利範圍第1項之電路板結構之製法,其中,該 電鍍導通孔端部表面上之導電層係透過直接鍍覆方式 (Direct plating, DP)形成。 3. 如申請專利範圍第1項之電路板結構之製法,其中,該 電鍍導通孔内部復以一填充材填滿其殘留空隙。 4. 如申請專利範圍第1項之電路板結構之製法,其中,該 電鍍導通孔端部表面上之導電層係利用化學沈積方式 ⑩形成。 5 ·如申請專利範圍第4項之電路板結構之製法,其中,該 電鍍導通孔端部表面上之導電層其材質可為銅及鈀之 其中一者。 6.如申請專利範圍第1項之電路板結構之製法,其中,該200531578 VI. Scope of patent application 1. A method for manufacturing a circuit board structure includes: providing a core board, the core board having a metal layer on the surface, and the core board formed with a large number of plated through-holes; A conductive layer is formed on an end surface of the plated via hole of the core board; a metal layer on the surface of the core board is patterned to form a patterned circuit structure; an insulating layer is covered on the circuit structure, and the insulating layer is formed with A plurality of openings, and at least one of the openings exposes the end of the plated via hole; and a metal layer is formed at the end of the plated via hole which exposes the opening of the insulating layer as an electrical connection end. 2. For the method for manufacturing a circuit board structure according to item 1 of the patent application, wherein the conductive layer on the surface of the end of the plated-through hole is formed by direct plating (DP). 3. For example, the method for manufacturing a circuit board structure according to the scope of the patent application, wherein a plating material is used to fill the remaining gaps in the plating vias. 4. For the method for manufacturing a circuit board structure according to item 1 of the patent application, wherein the conductive layer on the surface of the end of the plated-through hole is formed by chemical deposition. 5. The manufacturing method of the circuit board structure according to item 4 of the scope of patent application, wherein the material of the conductive layer on the surface of the end of the plated through hole may be one of copper and palladium. 6. As for the manufacturing method of the circuit board structure according to the scope of patent application item 1, wherein, the 17659 全懋.ptd 第26頁 200531578 六、申請專利範圍 電鍍導通孔端部表面上之導電層係利用無電電鍍方式 形成。 7. 如申請專利範圍第4或6項之電路板結構之製法,其中 ,該電鍍導通孔端部表面上之導電層係作為電流導通 路徑,以在該電鍍導通孔端部上形成電鍍金屬層。 8. 如申請專利範圍第1項之電路板結構之製法,其中,該 芯層板表面錯該導電層作為電流傳導路徑’以在該芯 層板表面上電鍍形成一導電薄層。 9. 如申請專利範圍第1項之電路板結構之製法,其中,該 芯層板可為一樹脂壓合銅箔(R C C)。 1 0 .如申請專利範圍第1項之電路板結構之製法,其中,該 芯層板可為一完成前段製程之多層電路板。 11.如申請專利範圍第1項之電路板結構之製法,其中,該 絕緣層為一拒鮮層。 1 2 .如申請專利範圍第1項之電路板結構之製法,其中,該 電鍍導通孔端部外露出絕緣層後,並形成一阻層以覆 蓋住電路板另一表面其餘開口。 1 3 .如申請專利範圍第1 2項之電路板結構之製法,其中, 於外露出該絕緣層開口之電鍍導通孔端部形成一金屬 層以作為電性連接端後,移除該阻層。 1 4 .如申請專利範圍第1項之電路板結構之製法,其中,可 在顯露出該絕緣層開口之電性連接端表面上形成金屬 保護層。 1 5 .如申請專利範圍第1 4項之電路板結構之製法,其中,17659 Quan 懋 .ptd Page 26 200531578 6. Scope of Patent Application The conductive layer on the surface of the end of the plated-through hole is formed by electroless plating. 7. If the method of manufacturing a circuit board structure according to item 4 or 6 of the application for a patent, wherein the conductive layer on the surface of the end of the plated via is used as a current conduction path to form a plated metal layer on the end of the plated via . 8. The manufacturing method of the circuit board structure according to the first patent application scope, wherein the surface of the core board is offset from the conductive layer as a current conduction path 'to form a conductive thin layer on the surface of the core board by electroplating. 9. For the method for manufacturing a circuit board structure according to item 1 of the patent application scope, wherein the core board may be a resin laminated copper foil (RCC). 10. If the method of manufacturing a circuit board structure according to item 1 of the scope of the patent application, the core board may be a multi-layer circuit board that has completed the previous process. 11. The method for manufacturing a circuit board structure according to item 1 of the patent application scope, wherein the insulation layer is a freshness-preventing layer. 12. The method for manufacturing a circuit board structure according to item 1 of the scope of patent application, wherein after the end of the plated via hole is exposed with an insulating layer, a resist layer is formed to cover the remaining opening on the other surface of the circuit board. 1 3. According to the method for manufacturing a circuit board structure according to item 12 of the scope of patent application, wherein a metal layer is formed at the end of the plated through hole exposing the opening of the insulating layer as an electrical connection end, and the resist layer is removed. . 14. The method of manufacturing a circuit board structure according to item 1 of the scope of patent application, wherein a metal protective layer may be formed on the surface of the electrical connection end that exposes the opening of the insulating layer. 1 5. The manufacturing method of the circuit board structure according to item 14 of the scope of patent application, wherein: 17659 全懋.ptd 第27頁 200531578 六、申請專利範圍 該金屬保護層為錄/金金屬層。 1 6 .如申請專利範圍第1 4項之電路板結構之製法,其中, 該金屬保護層係可利用電鍍導線及化學沈積方式之其 中一者加以形成。 1 7 .如申請專利範圍第1項之電路板結構之製法,其中,該 電鍍導通孔上之金屬層係作用為電性連接端,其係選 擇性形成於部分電鍍導通孔上,且預先利用阻層覆蓋 住形成細線路之區域。 1 8 .如申請專利範圍第1或1 7項之電路板結構之製法,其中 φ ,該電性連接端即可作為電路板後續接置導電元件用 〇 1 9 .如申請專利範圍第1或1 7項之電路板結構之製法,其中 ,該電性連接端可作為後續線路增層結構中承接導電 盲孔之用,俾得以在電鍍導通孔上形成導電盲孔,以 縮短導電途徑,增加線路佈設空間,與提升線路佈局 靈活度。 2 0 . —種電路板結構,係包括: 一芯層板,其表面形成有圖案化線路結構與多數 貫穿該芯層板之電鍍導通孔,該圖案化線路結構具有 _ 多數之導電線路與電鍍導通孔電性導通,而至少一電 性連接端係形成於該電鍍導通孔上; 一圖案化絕緣層,係形成在該線路結構上,俾使 該絕緣層形成有複數個開口以外露出該電性連接端, 且至少一開口係對應至該電鍍導通孔端部之電性連接17659 Quan 懋 .ptd Page 27 200531578 6. Scope of Patent Application The metal protective layer is a metal / gold metal layer. 16. The method for manufacturing a circuit board structure according to item 14 of the scope of patent application, wherein the metal protective layer can be formed by using one of a plating wire and a chemical deposition method. 17. According to the method for manufacturing a circuit board structure according to item 1 of the scope of patent application, wherein the metal layer on the plated through hole functions as an electrical connection end, it is selectively formed on part of the plated through hole and is used in advance. The barrier layer covers the area where the fine lines are formed. 1 8. If the method of manufacturing a circuit board structure according to item 1 or 17 of the scope of patent application, where φ, the electrical connection end can be used as a subsequent connection of conductive components on the circuit board. 9 If the scope of patent application is 1 or 17. The method for manufacturing a circuit board structure according to item 17, wherein the electrical connection end can be used to receive conductive blind holes in a subsequent layer build-up structure, so that conductive blind holes can be formed on the plated through holes to shorten the conductive path and increase Line layout space, and improve the flexibility of line layout. 2 0. A circuit board structure including: a core board, a patterned circuit structure and a plurality of plated vias penetrating through the core board are formed on the surface, and the patterned circuit structure has a majority of conductive circuits and plating The via is electrically conductive, and at least one electrical connection end is formed on the plated via; a patterned insulation layer is formed on the circuit structure, so that the insulation layer is formed with a plurality of openings to expose the electrical And the at least one opening corresponds to the electrical connection of the end of the plated through hole. 17659 全懋.ptd 第28頁 200531578 六、申請專利範圍 端;以及 一金屬保護層,係形成於外露出該圖案化絕緣層 開口之該電性連接端表面。 2 1 .如申請專利範圍第2 0項之電路板結構,其中,該芯層 板可為一樹脂壓合銅箱(RCC)。 2 2 .如申請專利範圍第2 0項之電路板結構,其中,該芯層 板可為一完成前段製程之多層電路板。 2 3 ,如申請專利範圍第2 0項之電路板結構,其中,該絕緣 層為拒銲層。 2 4 .如申請專利範圍第2 0項之電路板結構,其中,該電性 連接端即可作為電路板後續接置導電元件用。 2 5 .如申請專利範圍第2 0項之電路板結構,其中,該電鍍 導通孔上之電性連接端係於其餘同層線路結構形成後 再予製作。 2 6 .如申請專利範圍第2 0或2 5項之電路板結構,其中,該 電鍍導通孔上之電性連接端係選擇性形成於部分電鍍 導通孔上,而不致影響其餘圖案化線路結構之製程。 2 7 .如申請專利範圍第2 0項之電路板結構,其中,該金屬 保護層為鎳/金金屬層。17659 Quan 懋 .ptd Page 28 200531578 VI. Scope of patent application; and a metal protective layer formed on the surface of the electrical connection end which exposes the opening of the patterned insulating layer. 2 1. The circuit board structure according to item 20 of the patent application scope, wherein the core board may be a resin-compressed copper box (RCC). 2 2. If the circuit board structure of item 20 of the patent application scope, wherein the core board can be a multi-layer circuit board that has completed the previous process. 23, The circuit board structure according to item 20 of the patent application scope, wherein the insulating layer is a solder resist layer. 24. For example, the circuit board structure of the 20th in the scope of patent application, wherein the electrical connection end can be used as a subsequent connection of the circuit board to conductive elements. 25. The circuit board structure according to item 20 of the scope of patent application, wherein the electrical connection ends on the plated through-holes are made after the formation of the rest of the same layer circuit structure. 2 6. If the circuit board structure of the patent application scope item 20 or 25, wherein the electrical connection end on the plated through hole is selectively formed on part of the plated through hole without affecting the remaining patterned circuit structure The process. 27. The circuit board structure according to item 20 of the patent application scope, wherein the metal protective layer is a nickel / gold metal layer. 17659全懋.ptd 第29頁17659 懋 .ptd Page 29
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