TW200522808A - Printed circuit board and package having oblique vias - Google Patents

Printed circuit board and package having oblique vias Download PDF

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Publication number
TW200522808A
TW200522808A TW093105841A TW93105841A TW200522808A TW 200522808 A TW200522808 A TW 200522808A TW 093105841 A TW093105841 A TW 093105841A TW 93105841 A TW93105841 A TW 93105841A TW 200522808 A TW200522808 A TW 200522808A
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TW
Taiwan
Prior art keywords
pcb
package
hole
holes
signal
Prior art date
Application number
TW093105841A
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English (en)
Inventor
Han Kim
Bong-Kyu Choi
Dae-Cheol Seo
Heung-Kyu Kim
Sang-Kab Park
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Samsung Electro Mech
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Publication date
Application filed by Samsung Electro Mech filed Critical Samsung Electro Mech
Publication of TW200522808A publication Critical patent/TW200522808A/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09836—Oblique hole, via or bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Description

200522808 玖、發明說明： 【發明所屬之技術領域】 發明領域 本發明係大致有關於一種具有通孔之印刷電路板與封 5裝體且，特別是有關於一種具有傾斜通孔之印刷電路板與 封裝體，且该等通孔係相對在該印刷電路板與該封裝體中 之電路層表面傾斜以減少高頻損失。 先前技術之說明 10 一通孔表示在多層印刷電路板(PCB)與一封裝中之多 層間之電氣訊號的連接路徑，且基本上是被用來連接形成 在一雙側PCB中之頂與底面上之電路。通常，這種通孔之 形成方式疋形成一孔且電鍍該孔之内壁以透過該孔連接一 PCB之頂與底面。 15 以往，該孔係使用一機械鑽孔之方式形成，但近來已 開始使用雷射鑽孔。 這種通孔可以分成以下類型：完全穿過且連接全部層 之電鍍穿孔（PTH)型通孔，穿過並連接内層之填隙式通孔 (IVH)型通孔’及在其一部份被堵塞之埋入式通孔或盲通 20 孔。 此外’尚有具有一直徑小於1〇〇μπι之微通孔，一具有 一填充有銅之銅填充通孔，及一具有多數垂直地相互上下 積層之積層通孔。 不論通孔之種類為何，在習知積體電路(IC)封裝體或 200522808 PCB中使用之該等通孔之結構均垂直於電路層之表面。 因此，電力或訊號之路徑係由導電線與_或多個以直 角幫，曲數次以由-PCB或-1C封裝體中之—點傳送電力或 訊號至另一點的組合形成。 5 帛顯示在先前技射，-如巾央處理單元(cp_ 繪圖晶片組之高性能產品用之倒裝晶片接合封裝體i2〇，且 該倒裝晶片接合封裝體120係安裝在一pCB主機板1〇〇上。 請參閱約圖，電力與接地線係包含在一 pcB主機板 100中，且-倒裝晶片接合封裝體12〇之基板透過球接合no ίο與該pcb主機板100連接，並且一晶片14〇透過焊料凸塊接 合130安裝在該倒裝晶片接合封裝體12〇之基板上。 第1圖更包括多數微通孔160，一具有供電力或訊號流 動之階狀路徑的交錯通孔170,及一具有多數互相上下積層 之微通孔的積層通孔180。 15 如第1圖所示，為了將電力或訊號由該晶片140傳送至 該PCB主機板1〇〇，該電力或訊號之路徑係由導電線與以直 角彎曲數次之通孔的組合形成。
該電力或訊號之路徑由導電線與以直角彎曲數次之通 孔的組合形成以將電力或訊號由該晶片14〇傳送至該pCB 20主機板100之主要原因是習知通孔結構係與訊號線垂直而 與該等通孔之種類無關。 因此，该電力或訊號之路徑係由導電線與以直角彎曲 數次之通孔的組合形成，以將電力或訊號由該晶片140傳送 至該PCB主機板100，因而產生由數位訊號之高速所產生之 200522808 南頻損失。 該高頻損失是一種當一高頻通過一電路或裝置時所產 生之損失(例如，插入損失），當一電子裝置之工作頻率增高 8寸’该損失會增加，而這會破壞一訊號之傳送特性。 5 因此，為了以一高頻在一 1C封裝體或一 PCB中適當地 傳送電力或訊號，將高頻損失減至最少是很重要的。例如， 一目前所使用之CPU係在由2S3GHz之頻帶中操作，但是， 未來該CPU之操作頻率將會增加至1〇至2〇(}112或更大以有 效地執行其功能。 10 當該操作頻率增加時，由於該高頻損失，該習知通孔 結構會限制該1C封裝體或PCB之工作頻率的範圍。 此外，未來使用高頻之電子產品將會增加，且減少在 該等通孔中之高頻損失之需求亦會增加。 在圖式中，第2a與3a圖顯示習知通孔結構，且第知圖 15 顯示在習知通孔結構中之電場分布。 另外，第5圖顯示在由〇至10她之頻帶範圍中使用散 射參數之(S參數)之習知通孔的損失值。第5圖顯示當該綠 數之數值(db)以對數值減少時，高頻損失減少。 C發明内容】 20 發明概要 因此，本發明係欲解決發生在先前技術中之前述問題 而作成者，且本發明之目的是提供—種可減少高頻損失之 通孔結構。 為了達成上述目的’本發明提供-種PCB或IC封裝 200522808 體，该PCB或1C封裝體包括一絕緣層、多數電路層與一或 多個通孔’該等通孔係相對該等電路層傾斜地形成且構成 為相對訊號與電力傳輸之方向具有鈍角。 此外’本發明提供^4pC]^IC封裝體，該^^或]^ 5封裝體包括-或多個通孔，該等通孔係傾斜地形成以相對 就與電力傳輸之方向具有鈍角。 圖式簡單說明 本發明之Θ述與其他目的、特徵與優點將可配合附圖 由以下詳細說明更清楚地了解，其中： 第1圖顯不在先前技術中，一如中央處理單元(cpu)或 '會圖晶片組之南性能產品用之倒裝晶片接合封裝體，且該 倒裝晶片接合封裝體係安裝在一主機板上； 第2a圖顯示一習知通孔結構· 第2b圖顯示本發明之傾斜通孔結構； 5 第如圖顯示一習知積層通孔結構； 第3b圖顯示本發明之積層通孔結構； 第4a圖顯包含習知傾斜通孔之咖抓封裝體之一 部份中之電場分布； 第4b圖顯示包含本發明之傾斜通孔之pCB*IC封裝體 20 之一部份中之電場分布； 第5圖顯不包含本發明之傾斜通孔之pCBiIC封裝體 之一部份中之S參數； 第6圖是顯不包含本發明之傾斜通孔之？(：3或1(：封裝 體之橫截面圖； 200522808 第7a圖顯示在本發明之實施例中，一安裝在包括一傾 斜交錯通孔之PCB主機板上且供如CPU或繪圖晶片組之高 性能產品用之倒裝晶片接合封裝體； 第7b圖顯示在本發明之另一實施例中，一安裝在包括 5 一傾斜通孔之PCB主機板上且供如CPU或繪圖晶片組之高 性能產品用之倒裝晶片接合封裝體；及 第7c圖顯示在本發明之又一實施例中，一安裝在包括 一傾斜積層通孔之PCB主機板上且供如CPU或繪圖晶片組 之高性能產品用之倒裝晶片接合封裝體。 10 【實施方式】 較佳實施例之說明 以下將參照其中在不同圖式中使用相同之標號表示相 同或類似構件的圖式。 本發明之實施例係參照之第2a至7c圖詳細說明如下。 15 第2a至2b圖分別顯示通孔210a與210b，且該等通孔 210a與210b分別連接形成在一 PCB之上表面上之訊號線 200a與200b及形成在該PCB之下表面上之訊號線220a與 220b。 第2a圖顯示一垂直連接於該等訊號線200a與200b之通 20 孔結構，如先前技術之說明中所述，該習知通孔結構是造 成南頻損失之主因。 即，一訊號與電力之傳輸路徑之突然彎曲會在該突然 彎曲之部份中造成電磁雜訊且阻礙一訊號與電力之傳輸。 特別地，前述問題會在頻率變高時變得更為嚴重。依此觀 200522808 點，第2b圖顯示本發明之改良通孔結構。 在本發明之改良通孔結構中，該通孔係傾斜地形成， 使同頻之流動可以平順地進行，因此，相較於習知通孔結 構，可減少高頻損失。 5 第3&至31)圖顯示在積層之多層PCB中的通孔結構。 第3a圖顯示在一習知多層pCB中之積層通孔結構，其 中一通孔垂直地形成在一單層PCB中，且接著多數通孔排 列且互相上下積層以連接一形成在一 PCB之上表面上之訊 號線300a與-形成在该PCB之下表面上之訊號線3施。 10 ㈣地，在第3a®所示之軌結射，該等通孔係垂 直地形成在多數層中且以一曲折之方式互相連接。因為該 等通孔係垂直地形成在該等層中，這結構具有無法減少高 頻損失之限制。 第3b圖顯示一形成在多數層上之多層導電通孔結構， 15且該多層導電通孔結構可連接_形成在之上表面上 之訊號線鳩與-形成在該PCB之下表面上之訊號^ Λ ΛΙΐΚ o 是互 有欵 第 在第3b圖所示之通孔結構中，由於基本上形成的 相上下積層之傾斜魏而㈣直通孔，朗孔結 地減少高頻損失。 第4a至4b圖顯示電場之分布。 第4a圖顯示在—習知垂直通孔結構中之電場分布 扑圖顯示在本發明之傾斜通孔結構之電場分布。 明所 請參閱該等圖式，與習知通孔結構相較，在本於 20 200522808 提供之傾斜通孔結構中之電場之數值減少，且在由箭號所 示之部份中之電場分布亦減少。 第5圖是一顯示依據頻率之8參數以確認高頻損失之減 少的圖。 5 由〇至10GHz之頻帶係沿著X軸繪出，且該等S參數之值 係以對數值沿著Y軸繪出。在由0至頻帶中，相較 於習知通孔結構’本發明之通孔結構可減少平均大於2〇db 之高頻損失。 第6至7c圖顯示其中傾斜通孔6〇4應用在pCB上之例 10 子。 清參閱第6圖，該PCB包括傾斜地形成在一銅覆蓋積層 (CCL)601上之傾斜通孔6〇4，且一鋼電鍍層6〇5係形成在該 傾斜通孔604上以提供導電性。 第7a圖顯示在本發明之一實施例中，一安裝在包括一 15傾斜父錯通孔iPCB主機板上且供如一CPU或繪圖晶片組 之南性旎產品用之倒裝晶片接合封裝體。第7b圖顯示在本 發明之另一實施例中，一安裝在包括-傾斜微通孔之PCB 主機板上且供如一 C P U或繪圖晶片組之高性能產品用之倒 裝晶片接合封裝體。第7c圖顯示在本發明之又-實施例 20中’一安裝纟包括-傾斜積層通孔之pCB主機板上且供如 /CPU或㈣晶片組之高性能產品狀倒裝晶片接合封裝 體。 在第7a圖中，該交錯通孔75〇係傾斜地形成並相對電力 或訊號之流動具有鈍角以防止高頻損失。 11 200522808 當該電力或訊號由一晶片740流至該PCB主機板7〇〇 時，該交錯通孔750使該電力或訊號可沿著一傾斜路徑# 動，因此當施加高頻時可防止高頻損失。 在第7b圖中，該微通孔760係傾斜地形成並相對電力< 5 訊號之流動具有鈍角以防止高頻損失。 在第7c圖中，該積層通孔770係傾斜地形成並相對電力 或訊號之流動具有鈍角以防止高頻損失。 同時，當以一般之方式製成一PCB時，電路之圖案係 形成在一銅板上，藉此形成該PCB之内與外層。但是，最 10 近使用一聚合物或一玻璃纖維將光學波導管插入一pCb中 並以光之形式接收與傳送訊號。該PCB係被稱為一光電式 電路板(EOCB)。 本發明之通孔可以應用於一般之通孔與使用在該 EOCB中之光學通孔兩者。 15 此外’目前之行動訊號端子必須迷你化與輕量化以支 持高速、高容量之通訊且便於攜帶。 另外’在該等行動訊號端子中使用之構件已發展出來 以實現極度迷你化與複雜之功能，且對於該等行動訊號端 子之發展’相關構件亦已快速地發展出來以實現用以將多 20數裸晶片安裝在一低溫共燒陶瓷(LTCC)上之多晶片模組。 該LTCC係藉由使用一在大約800至1000 °C之低溫下共 少70陶竟與金屬之方法來形成一基板而製成，該基板之形成 之方式係將具有低熔點之玻璃與陶瓷混合以形成具有適當 介電常數之未處理片，再將一導電糊印刷在該未處理片上 12 200522808 並且將多數印有導電糊之未處理片互相上下積層。本發明 之傾斜通孔結構可以使用在使用該1；1^(：：之基板中。 如前所述，該傾斜通孔結構可以使用在具有習知垂直 通孔結構之基板以及該pCB中以減少高頻損失。 本發明可有效地克服在高頻時由於數位訊號之高速所 產生之訊號障礙。 此外，本發明可有效減少在採用一通孔結構之IC封裝 體或PCB之通孔中所產生之高頻損失，藉此改善在高頻帶 中之訊號傳送效能。 雖然在此已為了說明而揭露本發明之數個較佳實施 例，但是所屬技術領域中具有通常知識者應可了解在不偏 離在以下申請專利範圍所揭露之本發明之範疇與精神之情 形下可具有各種修改例、增添例與替代例。 【圖式簡單說明】 第1圖顯示在先前技術中，一如中央處理單元(cpu)或 、、曰圖晶片組之咼性能產品用之倒裝晶片接合封裝體，且該 倒裝晶片接合封裝體係安裝在一主機板上； 第2a圖顯示一習知通孔結構； 第2b圖顯示本發明之傾斜通孔結構； 第3a圖顯示一習知積層通孔結構； 第3b圖顯示本發明之積層通孔結構； 第4a圖顯示包含習知傾斜通孔之pCB4IC封裝體之一 部份中之電場分布； 第4b圖顯示包含本發明之傾斜通孔之pCB4IC封裝體 13 200522808 之一部份中之電場分布； 第5圖顯示包含本發明之傾斜通孔之PCB或1C封裝體 之一部份中之S參數； 第6圖是顯示包含本發明之傾斜通孔之1>€^或1(：：封裝 5 體之橫截面圖； 第7a圖顯示在本發明之實施例中，一安裝在包括一傾 斜父錯通孔之PCB主機板上且供如cpu或繪圖晶片組之高 性能產品用之倒裝晶片接合封裝體； 第7b圖顯示在本發明之另一實施例中，一安裝在包括 10 一傾斜通孔之PCB主機板上且供如cpu或繪圖晶片組之高 性能產品用之倒裝晶片接合封裝體；及 第7c圖顯示在本發明之又一實施例中，一安裝在包括 一傾斜積層通孔之pCB主機板上且供如CPU或繪圖晶片組 之南性能產品用之倒裝晶片接合封裝體。 15 14 200522808 【圖式之主要元件代表符號表】 100.. .PCB主機板 110…球接合 120.. .倒裝晶片接合封裝體 130···焊料凸塊接合 140.. .晶片 160···微通孔 170.. .交錯通孔 180…積層通孔 200a，200b…訊號線 210a，210b···通孔 220a，220b…訊號線 300a，300b…訊號線 330a，330b…訊號線 601.. .銅覆蓋積層 604…傾斜通孔 605…銅電鍵層 700.. .PCB主機板 740.. .晶片 750…交錯通孔 760…微通孔 770…積層通孔

Claims (1)

  1. 200522808 拾、申請專利範圍： 1. 一種印刷電路板(PCB)，包含： 一絕緣層； 多數電路層；及 5 一或多個通孔，係相對該等電路層傾斜地形成且構 成為相對訊號與電力傳輸之方向具有鈍角。 2. —種積體電路(1C)封裝體，包含：
    一絕緣層； 多數電路層；及 10 一或多個通孔，係相對該等電路層傾斜地形成且構 成為相對訊號與電力傳輸之方向具有鈍角。 3. —種PCB，包含： 一或多個通孔，該等通孔係傾斜地形成以相對訊號 與電力傳輸之方向具有鈍角。 15 4. 一種1C封裝體，包含：
    一或多個通孔，該等通孔係傾斜地形成以相對訊號 與電力傳輸之方向具有鈍角。 16
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US20050139390A1 (en) 2005-06-30
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CN1638611A (zh) 2005-07-13
DE102004012810A1 (de) 2005-07-28

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