TW200509229A - Method for fabricating dual-metal gate device - Google Patents
Method for fabricating dual-metal gate deviceInfo
- Publication number
- TW200509229A TW200509229A TW093104923A TW93104923A TW200509229A TW 200509229 A TW200509229 A TW 200509229A TW 093104923 A TW093104923 A TW 093104923A TW 93104923 A TW93104923 A TW 93104923A TW 200509229 A TW200509229 A TW 200509229A
- Authority
- TW
- Taiwan
- Prior art keywords
- over
- area
- gate
- sacrificial layer
- conductor material
- Prior art date
Links
- 239000002184 metal Substances 0.000 title abstract 3
- 229910052751 metal Inorganic materials 0.000 title abstract 3
- 239000004020 conductor Substances 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 239000003989 dielectric material Substances 0.000 abstract 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/400,896 US6972224B2 (en) | 2003-03-27 | 2003-03-27 | Method for fabricating dual-metal gate device |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200509229A true TW200509229A (en) | 2005-03-01 |
TWI337377B TWI337377B (en) | 2011-02-11 |
Family
ID=32989311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093104923A TWI337377B (en) | 2003-03-27 | 2004-02-26 | Method for fabricating dual-metal gate device |
Country Status (7)
Country | Link |
---|---|
US (2) | US6972224B2 (zh) |
EP (1) | EP1611612A4 (zh) |
JP (1) | JP2007524992A (zh) |
KR (1) | KR20050112114A (zh) |
CN (1) | CN100495685C (zh) |
TW (1) | TWI337377B (zh) |
WO (1) | WO2004095527A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI421980B (zh) * | 2007-06-29 | 2014-01-01 | Freescale Semiconductor Inc | 用於形成雙金屬閘極結構之方法 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040212025A1 (en) * | 2003-04-28 | 2004-10-28 | Wilman Tsai | High k oxide |
US20040256679A1 (en) * | 2003-06-17 | 2004-12-23 | Hu Yongjun J. | Dual work function metal gates and method of forming |
US7129182B2 (en) * | 2003-11-06 | 2006-10-31 | Intel Corporation | Method for etching a thin metal layer |
US7064050B2 (en) * | 2003-11-28 | 2006-06-20 | International Business Machines Corporation | Metal carbide gate structure and method of fabrication |
KR100598033B1 (ko) * | 2004-02-03 | 2006-07-07 | 삼성전자주식회사 | 반도체 소자의 듀얼 게이트 산화막 형성 방법 |
US8404594B2 (en) * | 2005-05-27 | 2013-03-26 | Freescale Semiconductor, Inc. | Reverse ALD |
JP2006332400A (ja) * | 2005-05-27 | 2006-12-07 | Nec Corp | 薄膜半導体装置およびその製造方法 |
US20060289948A1 (en) * | 2005-06-22 | 2006-12-28 | International Business Machines Corporation | Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof |
KR100688555B1 (ko) * | 2005-06-30 | 2007-03-02 | 삼성전자주식회사 | Mos트랜지스터를 구비하는 반도체 소자 및 그 제조 방법 |
KR100697694B1 (ko) * | 2005-08-02 | 2007-03-20 | 삼성전자주식회사 | 듀얼 게이트를 갖는 반도체 장치 및 그 제조 방법 |
US8178401B2 (en) * | 2005-08-25 | 2012-05-15 | Freescale Semiconductor, Inc. | Method for fabricating dual-metal gate device |
US20070048920A1 (en) * | 2005-08-25 | 2007-03-01 | Sematech | Methods for dual metal gate CMOS integration |
US7332433B2 (en) * | 2005-09-22 | 2008-02-19 | Sematech Inc. | Methods of modulating the work functions of film layers |
US7432164B2 (en) * | 2006-01-27 | 2008-10-07 | Freescale Semiconductor, Inc. | Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same |
KR100827435B1 (ko) * | 2006-01-31 | 2008-05-06 | 삼성전자주식회사 | 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법 |
US7445976B2 (en) * | 2006-05-26 | 2008-11-04 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device having an interlayer and structure therefor |
EP1914800A1 (en) * | 2006-10-20 | 2008-04-23 | Interuniversitair Microelektronica Centrum | Method of manufacturing a semiconductor device with multiple dielectrics |
EP1928021A1 (en) * | 2006-11-29 | 2008-06-04 | Interuniversitair Microelektronica Centrum (IMEC) | Method of manufacturing a semiconductor device with dual fully silicided gate |
KR100814372B1 (ko) | 2007-01-24 | 2008-03-18 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US7582521B2 (en) * | 2007-05-04 | 2009-09-01 | Texas Instruments Incorporated | Dual metal gates for mugfet device |
US7666730B2 (en) | 2007-06-29 | 2010-02-23 | Freescale Semiconductor, Inc. | Method for forming a dual metal gate structure |
JP2009021550A (ja) * | 2007-07-12 | 2009-01-29 | Panasonic Corp | 半導体装置の製造方法 |
US20090134469A1 (en) * | 2007-11-28 | 2009-05-28 | Interuniversitair Microelektronica Centrum (Imec) Vzw | Method of manufacturing a semiconductor device with dual fully silicided gate |
JP2009170841A (ja) * | 2008-01-21 | 2009-07-30 | Toshiba Corp | 半導体装置の製造方法 |
US7867839B2 (en) * | 2008-07-21 | 2011-01-11 | International Business Machines Corporation | Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors |
US7838908B2 (en) * | 2009-01-26 | 2010-11-23 | International Business Machines Corporation | Semiconductor device having dual metal gates and method of manufacture |
US8288296B2 (en) | 2010-04-20 | 2012-10-16 | International Business Machines Corporation | Integrated circuit with replacement metal gates and dual dielectrics |
US8941184B2 (en) | 2011-12-16 | 2015-01-27 | International Business Machines Corporation | Low threshold voltage CMOS device |
CN104347511B (zh) * | 2013-08-07 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
US10276562B2 (en) | 2014-01-07 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with multiple threshold voltage and method of fabricating the same |
TWI660465B (zh) * | 2017-07-28 | 2019-05-21 | 新唐科技股份有限公司 | 半導體元件及其製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6123363A (ja) * | 1984-07-11 | 1986-01-31 | Toshiba Corp | 半導体装置およびその製造方法 |
JPS62265752A (ja) * | 1986-05-14 | 1987-11-18 | Pioneer Electronic Corp | インバ−タ |
JP2000332125A (ja) * | 1999-05-18 | 2000-11-30 | Nec Corp | 半導体装置及びその製造方法 |
JP2001284466A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6444512B1 (en) | 2000-06-12 | 2002-09-03 | Motorola, Inc. | Dual metal gate transistors for CMOS process |
JP2002198441A (ja) * | 2000-11-16 | 2002-07-12 | Hynix Semiconductor Inc | 半導体素子のデュアル金属ゲート形成方法 |
US6410376B1 (en) * | 2001-03-02 | 2002-06-25 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration |
KR100399356B1 (ko) * | 2001-04-11 | 2003-09-26 | 삼성전자주식회사 | 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법 |
KR100426441B1 (ko) * | 2001-11-01 | 2004-04-14 | 주식회사 하이닉스반도체 | 반도체 소자의 시모스(cmos) 및 그의 제조 방법 |
KR20050098879A (ko) * | 2003-02-03 | 2005-10-12 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 반도체 장치 및 반도체 장치의 제조 방법 |
-
2003
- 2003-03-27 US US10/400,896 patent/US6972224B2/en not_active Expired - Lifetime
-
2004
- 2004-02-13 CN CNB2004800083780A patent/CN100495685C/zh not_active Expired - Fee Related
- 2004-02-13 JP JP2006508738A patent/JP2007524992A/ja active Pending
- 2004-02-13 WO PCT/US2004/004326 patent/WO2004095527A2/en active Application Filing
- 2004-02-13 KR KR1020057018193A patent/KR20050112114A/ko not_active Application Discontinuation
- 2004-02-13 EP EP04711210A patent/EP1611612A4/en not_active Withdrawn
- 2004-02-26 TW TW093104923A patent/TWI337377B/zh not_active IP Right Cessation
-
2005
- 2005-08-25 US US11/211,798 patent/US20050282326A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI421980B (zh) * | 2007-06-29 | 2014-01-01 | Freescale Semiconductor Inc | 用於形成雙金屬閘極結構之方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI337377B (en) | 2011-02-11 |
WO2004095527A3 (en) | 2007-03-29 |
CN101027771A (zh) | 2007-08-29 |
EP1611612A4 (en) | 2007-12-05 |
CN100495685C (zh) | 2009-06-03 |
JP2007524992A (ja) | 2007-08-30 |
US20040191974A1 (en) | 2004-09-30 |
US6972224B2 (en) | 2005-12-06 |
KR20050112114A (ko) | 2005-11-29 |
WO2004095527A2 (en) | 2004-11-04 |
EP1611612A2 (en) | 2006-01-04 |
US20050282326A1 (en) | 2005-12-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |