TW200423334A - Multi-chips package - Google Patents
Multi-chips package Download PDFInfo
- Publication number
- TW200423334A TW200423334A TW092109654A TW92109654A TW200423334A TW 200423334 A TW200423334 A TW 200423334A TW 092109654 A TW092109654 A TW 092109654A TW 92109654 A TW92109654 A TW 92109654A TW 200423334 A TW200423334 A TW 200423334A
- Authority
- TW
- Taiwan
- Prior art keywords
- chip
- dam
- patent application
- scope
- item
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Description
200423334 五、發明說明(1) (一)、【發明所屬之技術領域】 本發明是有關於一種多晶片封裝體,特別 種旎夠防止連接晶片與載板間凸塊破壞之多二 7曰曰斤封裝體 【先前技術】 隨著 體在許多 兩個或兩 之運作速 之長度而 最常 片封裝體 同載板之 接一般係 多晶片封 面積會隨 微小化以及高運作速度 電子裝置越來越吸引人 個以上之晶片組合在單 度。此外,多晶片封裝 降低訊號延遲以及存取 見的多晶片封裝體為並 ’其係將兩個以上之晶 主要安裝面。晶片與共 糟由打線法(wire bond 裝體之缺點為封裝效率 著晶片數目的增加而增 需求的增加,多 。多晶片封裝體 一封裝體中,來 體可減少晶片間 時間。 排式(side-by-side)多 片彼此並排地安 同載板上導電線 1 n g)達成。然而 太低’因為該共 加。 晶片封裝 可藉由將 提升系統 連接線路 曰曰 裝於一共 路間之連 該並排式 同載板之 因此半導體業界開發出一多晶片封裝體之設計(參昭 圖1),其特徵在於提供-第-晶片110覆晶接合於一具有 -開口122之載板120上表面124,再將一第二晶片13〇容置 於載板120之開口122中,並與上述之第一晶片ιι〇覆晶接 合。-般而言,第一晶片11〇與第二晶片13〇可分別為記憶 晶片及邏輯晶片,如此可將第__晶片! i Q與第二晶片i 3〇之 訊號於封裝體内先行整合後,再經由載板12〇下表面126之 鮮球1 28與外界電性連接。如此之封褒體設計不僅能減少封 200423334
裝體之厚度,更可提升晶片之運算及傳輸效能。然而,由 於第一晶片1 1 0與載板1 2 0間係以導電凸塊1 6 0電性連接,而 載板120之熱膨脹係數(約為16 X 10-6ppm/ t)遠大於第一曰 片11 0之熱膨脹係數(約為4 X 1 〇-6 p p m / °c ),敌封裝體進行相 關測試或進行運作時,常因為熱膨脹係數之差異,造成連 接第一晶片110與載板120間導電凸塊160之破壞。 有鑑於此,為避免前述多晶片封裝體之缺點,以提升 多晶片封裝體中之晶片效能,實為一重要的課題。 (三)、【發明内容】 有鑑於上述課題,本發明之目的係提供一種多晶片封 裝體’其係在載板上之晶片週邊之外圍設置一攔壩,並藉 由攔壩之支撐而於該晶片背面設置一散熱片。同時,於該 攔壩所包圍之區域中填充底膠,以使底膠、散熱片及攔壤 所組合而成之加勁結構,能對設置於載板上之晶片與載板 間提供一限制熱形變之能力,以避免連接設置於載板上方 之晶片與載板間之導電凸塊之破壞。 緣是,為了達成上述目的,本發明係提供一種多晶片 封裝體,主要包含一載板、一第一晶片、一第二晶片、一 攔壩、一散熱片、一底膠與複數個導電凸塊。第一晶片係 藉複數個導電凸塊覆晶接合於載板之上表面,而第二晶片 係容置於載板之開口中’且與第一晶片覆晶接合。再者, 该攔壩係用以支撑該散熱片以使散熱片能固定設置於該第 一晶片之背面。此外,填充底膠於攔壩、散熱片、載板上
200423334 五、發明說明(3) " -------— 表面及載板開口所宗益 勺 曰 ^疋義之填充底膠空間中,以使底膠至少 八。 曰曰片 第二晶片、複數個導電凸塊及載板之一部 ti '虎^底膠係與散熱片及攔壩相接合,故能藉由散熱 一曰U膠與攔壩所形成之加勁結構,❿同時限制載板與第 一 之熱形變,以避免連接第一晶片與載板之導電凸塊 之破壞。 、: 斤述本發明之多晶片封裝體主要係利用由散熱 曰&膠與攔壩所形成之加勁結構,以提供對載板與第一 =片之熱形變限制之能力,以避免連接第一晶片與載板之 V電凸塊之破壞。另外,由於散熱片係設置於第一晶片背 面’故亦能提升封裝體之散熱效能。 (四)、【實施方式】 以下將參照相關圖式,說明依本發明較佳實施例之多 晶片封裝體。 圖2係繪示本發明較佳實施例之多晶片封裝體。本發明 之多晶片封裝體至少包含一第一晶片21〇、載板22〇、一第 二晶片2 3 0、一攔壩240、一散熱片250、一底膠260與複數 個第一導電凸塊270及第二導電凸塊280。其中,第一晶片 210係藉複數個第一導電凸塊270覆晶接合於載板220之上表 面2 24,而第二晶片2 3 0係容置於載板2 2 0之開口 222中,且 藉由複數個第二導電凸塊2 80與第一晶片210之主動表面212 覆晶接合。同時,利用一黏著層(導熱膠)2 9 0將散熱片2 5 〇 同時黏著於第一晶片210之背面2 14及設置於載板22 0上表面
200423334 五、發明說明(4) "" 226之棚墙240上。再者,攔壩24〇、散熱片25〇、載板上表 面224及載板開口 22 2可定義一底膠填充空間3〇〇用以填充一 底膠2 60 ,使至少複數個第一導電凸塊27〇、第二導電凸塊 280被底膠2 6 0所包覆之,且使底膠26〇與散熱片25〇及攔壩 240相接合,故能藉由散熱片25〇、底膠26()與攔壩24〇所形 成加勁結構,同時限制載板2 2 〇與第一晶片2 1 〇之熱形變,
以進一步避免連接載板22〇與第一晶片21〇間之第一導電凸 塊2 70,因載板2 2 0與第一晶片21〇之熱膨脹係數不匹配效應 而破壞。此外,該載板220之下表面22Θ可設置有複數個銲 球228,用以與外界電性導通。值得注意的是,該攔壩24〇 可為一膠體,利用點滞之方式形成於載板220上並環繞於第 一晶片210之週邊設置,故搁壩240可為一環形攔壩。此 外,該攔壩2 4 0亦可為複數個條狀攔壩設置於第一晶片2 J 〇 週邊之外圍。再者,上述之底膠亦可以其他之封膠材料替 代之,如環氧膠。 承上所述’當第一晶片210之厚度較大或其尺寸較大 時’散熱片250可選擇其熱膨脹係數較接近載板220埶臌勝 係數之材質。反之,當第-晶片m之厚度較薄或尺寸較服小 時,散熱片2 5 0可選擇其熱膨脹係數較接近晶片熱膨脹係數 之材質。故散熱片2 5 0之熱膨脹係數係介於晶片之熱膨服係 數與載板2 2 0之熱膨脹係數之間。由於散熱片2 5 0之熱膨脹' 係數係介於載板2 2 0與晶片之熱膨脹係數之間,且藉由散熱 片、底膠及攔壩所組合而成加勁結構,可限制載板2 2 〇與第 一晶片2 1 0之熱形變外,以進一步避免連接第一晶片2 J 〇與
200423334
五、發明說明(5) 載板220之第—導電凸塊27〇之破壞。值得注意的是, 熱片250係為—平面板,且該散熱片25〇之材質可包含— 金屬或一銘金屬,故散熱片除可配合底膠與攔壩組合^ 勁結構外,更可藉其有較大之導熱面積及導熱能力二 封裝體之散熱效能。 升 於本實施例之詳細說明中所提出之具體的實施例僅為 了易於說明本發明之技術内容,而並非將本發明狹義地限 制於該實施例,因此,在不超出本發明之精神及以下申請 專利範圍之情況,可作種種變化實施。
200423334 圖式簡單說明 (五)、【圖式簡單說明】 圖1為一示意圖,顯示習知一種多晶片封裝體的剖面示 意圖。 圖2為一示意圖,顯示本發明較佳實施例之多晶片封裝 體之剖面 示意 圖 0 元件符號 說明 : 110 、210 第 一 晶 片 120 > 220 載 板 122 > 222 開 V 124 、224 載 板 上 表 面 126 ^ 226 載 板 下 表 面 128 ^ 228 銲 球 130 ^ 230 第 二 晶 片 212 第 一 晶 片 之 主 動表面 214 第 一 晶 片 之 背 面 240 攔 壩 250 散 埶 片 260 底 膠 270 第 一 導 電 凸 塊 280 第 二 導 電 凸 塊 290 黏 著 層(導熱膠) 300 底 膠 填 充 空 間
第11頁
Claims (1)
- 200423334 六、申請專利範圍 1 · 一種多晶片封裝體,包含: 二載板,具有—上表面、—下表面及一開口; -第-晶片’具有一主動表面、—背面,其 係藉複數個第一導電凸堍鱼兮恭化 、〜第一日曰片 人m 載板之該上表面覆晶接 口 ,且该第一晶片係覆蓋該開口; 一晶片,其中該第二晶片係藉複數個第二導電凸塊盥 該第一晶片之該主動表面覆晶接合; /、 二,壩,該攔壩係設置於該載板上表面;以及 一散熱片’該散熱片係設置於該第一晶片之該背面且盥該 攔壩相接合。 ~ 2.如申請專利範圍第1項所述之多晶片封裝體,其中該散熱 片與該第一晶片間更設置一黏著層。 3 ·如申請專利範圍第3項所述之多晶片封裝體,其中該黏著 層係為一導熱膠。 4 ·如申請專利範圍第1項所述之多晶片封裝體,其中該攔 壩、該散熱片、該載板上表面及該載板開口係形成一空 間’該空間中係填充一封膠材料。 5·如申請專利範圍第4項所述之多晶片封裝體,其中該封膠 材料係為一底膠。 第12頁 200423334 六、申請專利範圍 6·如申請專利範圍第4項所述之多晶片封裝體,其中該底膠 係至少包覆該第一晶片、該第一導電凸塊、該第二導電凸 塊、該載板上表面,且與該散熱片及該攔壩相接合。 7·如申請專利範圍第1項所述之多晶片封裝體,其中該散熱 片之材質係包含銅金屬。 8 ·如申請專利範圍第1項所述之多晶片封裝體,其中該散熱 片之材質係包含铭金屬。 9 ·如申請專利範圍第1項所述之多晶片封裝體,其中該散熱 片係為一平面板。 1 0.如申請專利範圍第1項所述之多晶片封裝體,其中該攔 壩係為一膠體。 11.如申請專利範圍第1項所述之多晶片封裝體,其中該攔 壩係為一環狀。 1 2.如申請專利範圍第1項所述之多晶片封裝體,其中該攔 壩係環繞該第一晶片之週邊設置。 1 3.如申請專利範圍第1項所述之多晶片封裝體,其中該載 板之該下表面更具有一鮮球。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092109654A TWI231977B (en) | 2003-04-25 | 2003-04-25 | Multi-chips package |
US10/820,854 US20040212069A1 (en) | 2003-04-25 | 2004-04-09 | Multi-chips stacked package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092109654A TWI231977B (en) | 2003-04-25 | 2003-04-25 | Multi-chips package |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200423334A true TW200423334A (en) | 2004-11-01 |
TWI231977B TWI231977B (en) | 2005-05-01 |
Family
ID=33297680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092109654A TWI231977B (en) | 2003-04-25 | 2003-04-25 | Multi-chips package |
Country Status (2)
Country | Link |
---|---|
US (1) | US20040212069A1 (zh) |
TW (1) | TWI231977B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105793979A (zh) * | 2013-12-27 | 2016-07-20 | 英特尔公司 | 光电子封装组件 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930378B1 (en) * | 2003-11-10 | 2005-08-16 | Amkor Technology, Inc. | Stacked semiconductor die assembly having at least one support |
JP2005197491A (ja) * | 2004-01-08 | 2005-07-21 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US7038321B1 (en) * | 2005-04-29 | 2006-05-02 | Delphi Technologies, Inc. | Method of attaching a flip chip device and circuit assembly formed thereby |
US7528474B2 (en) * | 2005-05-31 | 2009-05-05 | Stats Chippac Ltd. | Stacked semiconductor package assembly having hollowed substrate |
TWI268628B (en) * | 2005-08-04 | 2006-12-11 | Advanced Semiconductor Eng | Package structure having a stacking platform |
KR100712549B1 (ko) * | 2006-01-31 | 2007-05-02 | 삼성전자주식회사 | 패키지 리드를 포함하는 멀티 스택 패키지 |
US20080197468A1 (en) * | 2007-02-15 | 2008-08-21 | Advanced Semiconductor Engineering, Inc. | Package structure and manufacturing method thereof |
DE102007007503A1 (de) * | 2007-02-15 | 2008-08-21 | Robert Bosch Gmbh | Bauelementanordnung |
US8916958B2 (en) * | 2009-04-24 | 2014-12-23 | Infineon Technologies Ag | Semiconductor package with multiple chips and substrate in metal cap |
CN102556938B (zh) * | 2011-12-27 | 2015-07-15 | 三星半导体(中国)研究开发有限公司 | 芯片叠层封装结构及其制造方法 |
KR101923535B1 (ko) | 2012-06-28 | 2018-12-03 | 삼성전자주식회사 | 패키지 온 패키지 장치 및 이의 제조 방법 |
US8742597B2 (en) * | 2012-06-29 | 2014-06-03 | Intel Corporation | Package substrates with multiple dice |
KR20140006587A (ko) * | 2012-07-06 | 2014-01-16 | 삼성전자주식회사 | 반도체 패키지 |
KR20150028031A (ko) * | 2013-09-05 | 2015-03-13 | 삼성전기주식회사 | 인쇄회로기판 |
US9269700B2 (en) | 2014-03-31 | 2016-02-23 | Micron Technology, Inc. | Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods |
CN103904066A (zh) * | 2014-04-04 | 2014-07-02 | 华进半导体封装先导技术研发中心有限公司 | 一种倒装芯片堆叠封装结构及封装方法 |
US11139282B2 (en) * | 2018-07-26 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and method for manufacturing the same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5909056A (en) * | 1997-06-03 | 1999-06-01 | Lsi Logic Corporation | High performance heat spreader for flip chip packages |
US6092281A (en) * | 1998-08-28 | 2000-07-25 | Amkor Technology, Inc. | Electromagnetic interference shield driver and method |
US6369448B1 (en) * | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
KR100559664B1 (ko) * | 2000-03-25 | 2006-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
JP2002033411A (ja) * | 2000-07-13 | 2002-01-31 | Nec Corp | ヒートスプレッダ付き半導体装置及びその製造方法 |
-
2003
- 2003-04-25 TW TW092109654A patent/TWI231977B/zh not_active IP Right Cessation
-
2004
- 2004-04-09 US US10/820,854 patent/US20040212069A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105793979A (zh) * | 2013-12-27 | 2016-07-20 | 英特尔公司 | 光电子封装组件 |
Also Published As
Publication number | Publication date |
---|---|
US20040212069A1 (en) | 2004-10-28 |
TWI231977B (en) | 2005-05-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9666571B2 (en) | Package-on-package structures | |
US6369448B1 (en) | Vertically integrated flip chip semiconductor package | |
TWI231977B (en) | Multi-chips package | |
TWI225292B (en) | Multi-chips stacked package | |
US20140151880A1 (en) | Package-on-package structures | |
US7446409B2 (en) | Cavity-down multiple-chip package | |
US5838545A (en) | High performance, low cost multi-chip modle package | |
US20060091560A1 (en) | Multi-chip stack package | |
TW557556B (en) | Window-type multi-chip semiconductor package | |
KR102170197B1 (ko) | 패키지 온 패키지 구조들 | |
TWI225693B (en) | Multi-chips package | |
TWI229434B (en) | Flip chip stacked package | |
TWI225291B (en) | Multi-chips module and manufacturing method thereof | |
TWI231983B (en) | Multi-chips stacked package | |
TW578282B (en) | Thermal- enhance MCM package | |
TWI230447B (en) | Multi-chips package | |
KR20090022771A (ko) | 스택 패키지 | |
US20070284756A1 (en) | Stacked chip package | |
TWI711131B (zh) | 晶片封裝結構 | |
TW200423363A (en) | Multi-chips stacked package | |
CN219575614U (zh) | 封装结构 | |
KR20060133800A (ko) | 칩 스택 패키지 | |
TW200423332A (en) | Flip chip package | |
KR20030048250A (ko) | 멀티칩 패키지 | |
TWI239081B (en) | Multi-chip package structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |