TWI239081B - Multi-chip package structure - Google Patents

Abstract

A multi-chip package structure comprises a substrate, a chip supporting element, and a plurality of chips. The chip supporting element has a plurality of supporting surfaces and is disposed on the substrate. The plurality of chips are disposed on the plurality of supporting surfaces respectively and electrically connected to a plurality of pads of the substrate so as to electrically connect with an external circuit therethrough.

Description

1239081

[Technical field to which the invention belongs] More particularly, the present invention relates to a multi-chip package structure and a multi-chip package structure having a wafer carrier. [Previous technology] Chip miniaturization Due to the increasing thinness and shortness of electronic products and the packaging that provides external circuit connections, the protection of semiconductor structures also requires thinness and shortness. With miniaturization and increased demand for high operating speeds, multiple chips 2 Made in many electronic devices is becoming increasingly attractive. A multi-chip package structure can be obtained by combining two or more chips (such as a processor (pr0ces ^ r), memory, and related logic unit (10gic)) in a single package. In the structure, the limitation of the system operating speed is minimized. In addition, the multi-chip package structure can shorten the length of the inter-chip soldering circuit and reduce the signal delay and access time. The most common multi-chip package structure is side-by-side ^ — "— ^^) # The chip package structure is to mount two or more wafers side by side on the main mounting surface of a common substrate. The connection between the chip and the conductive lines on the common substrate is generally achieved by wire bonding. However, it should not

The disadvantage of the row-type multi-chip package structure is that the packaging efficiency is too low, because the area of the common substrate will increase as the number of chips increases. Therefore, the semiconductor industry has developed a stacked wafer package structure 10, which generally includes two wafers 1 2, 1 4 stacked on top of each other (as shown in FIG. 1). A substrate 1 § the upper surface. There is an adhesive layer 20 between the sheets 1, 2, and 14. The wafers 1, 2, and 4 are each using bonding wires.

00698.ptd page 7 1239081

(bonding wire) 22, 24 are electrically connected to a plurality of wire-bonding pads 26 on the upper surface of the substrate 18. A plurality of solder ball pads 28 are provided on the lower surface of the substrate 18, which are a plurality of wire bonding pads 26 electrically connected to the upper surface of the substrate 18. Each solder ball pad 28 is provided with a solder ball 30 for electrical connection with the outside. A part of the upper surface of the wafers 1 2, 1 4, the bonding wires 2 2, 2 4 and the side substrate 18 is covered by a package 32. However, when the wafers stacked on each other in the stacked wafer package structure 10 have the same size, the 'upper wafer 14 will hinder the wiring operation of the lower wafer 12'. In addition, in order to increase the operating speed and function of the electronic device, the chip 14 is connected to the other chip 34, as shown in FIG. The wafer 34 is fixed to the wafer 14 by an adhesive layer 36, and is electrically connected to a wire bonding pad 26 on the upper surface of the substrate 18 by a bonding wire 38. However, it should be understood that when the number of wafer stacks of the far-stacked chip package structure 10 increases, the inverse connection with μ is relatively long and higher, and more efficient. In addition, the higher sealing reduces the packaging efficiency, so the package structure solves the problem more. The layer chip 34 is increased to this place. This will increase the length and the thickness of the gel when the conductive seal of the path type is encapsulated, so that the rate (packaging 'the present invention mentions') not only increases the multi-chip packaging wire bonding pad 2 The soldering line of 6 soldering line, which is used for wiring, the more likely it is that the punching path type wire is enough to cover the wire and efficiency) 〇A package height and line 38 with a multi-chip package structure is provided. Length and high difficulty. For example, the more the industry is, the easier it is to wire sweep existing and stacked wafers, which need to be stacked, thus reducing the number of wafer carriers. The number of wafers in the manufacturing line is limited by the southern limit of the wire. Q

1239081

[Summary of the Invention] The object of the present invention is to provide a multi-chip package structure that uses a plurality of chip carriers to be placed thereon, thereby increasing the number of multi-chips and simultaneously solving the multi-chip package structure. The surface 'sets a plurality of wafers with the number of wafers in the package structure, and the wafer support is limited by 1¾ degree and the height of the wire. ΪThe multi-chip package structure of the present invention' includes-substrate,-on-chip, and 1 is: Wafers, the wafer carrier is provided on the substrate: there are a plurality of bearing surfaces for carrying the wafers, and the mother wafer is electrically connected to a plurality of circuit contacts on the substrate, and A multi-chip package structure according to the present invention with the plurality of circuit contacts and an external circuit contact is characterized in that the carrier has a plurality of carrier surfaces for carrying a plurality of effectively achieving a multi-chip package. purpose. ^ In order to make the above and other objects, features, and advantages of the present invention more apparent ', the following detailed description will be given with reference to the accompanying drawings. [Embodiment] As shown in FIG. 3, it is a schematic side view for explaining an f-chip package structure according to an embodiment of the present invention. The figure shows a multi-chip package structure 100 'which includes a substrate 102 and a wafer carrier 104 disposed thereon. The wafer carrier 104 has a bottom surface 106 and a top surface ^^ surface 108 And the four oblique sides 110a, 110b, 110c, and 110d, as shown in FIG. 4 ', are schematic diagrams showing the top surface of the wafer carrier 104. The carrier 104 is disposed on the upper surface 112 of the substrate through the bottom surface 106.

1239081 V. Description of the invention (4)-set on the area 107, and the four oblique side surfaces ii〇a, ii〇b, no oc and 1 1 〇d, and the top surface 1 08, preferably each setting There is a chip labeled 114a, 114b, 114c, 114d, and 114e, as shown in Figures 3 and 4. 118. The plurality of plated-through lines of the substrate 102 and the plurality of second circuits connected to the wafers 114a, 1 14b, 1 14c, 1 1d, and 1 14e are connected to the substrate through a plurality of bonding wires 11 16 respectively. The plurality of first circuit contacts on 1 〇 丨 8 are electrically connected ', and the plurality of first circuit contacts 丨 8 are arranged on the periphery of the setting area 107 and below the substrate 102 The plurality of second circuit contacts on the surface 120 are electrically connected to each other. Preferably, the electrical connection between the plurality of first circuit contacts 11 8 and the plurality of second circuit contacts 1 2 2 | the method is that a plurality of plated-through lines (not (Shown) to complete 'and the plurality of second circuit contacts 丨 2 2 are used to be electrically connected to an external circuit (not shown). Preferably, a solder ball 123 is formed on each of the second circuit contacts 122 and is electrically connected to the external circuit through the solder ball 123. Therefore, the chips U4a, 1 14b, 1 i4c, 1 14d, and 1 1 4e are connected by the plurality of bonding wires 丨 6 'the plurality of first circuit contacts 1 22 and the plurality of solder balls 23 The formed electrical path is electrically connected to an external circuit. Furthermore, the plurality of chips can be electrically connected to each other by a wire bonding method. • In another embodiment of the present invention, the wafers 114a, 114b, 114 =, U4d, and 114e can be separately placed on the four oblique sides by f Hp chip 丨 丨 a , N ob, n oc, 丨 丨 d, and the top surface 108 are shown in FIGS. 4 and 5. In this embodiment, the wafer support

1239081 V. Description of the invention (5) The carrier 10 is provided with a plurality of plated-through circuits (not shown), and one end of the money-pass circuit of the carrier 104 is electrically connected to the chips n 4a , 14b, 114c, 114d, and 14e first solder ball structures 124, and the other end is penetrated to the bottom surface of the carrier 104, and is used to electrically connect a plurality of second solder ball structures 124 1 26; In addition, the plurality of wafers can be electrically connected to each other by electrically connecting plated through holes (not shown) between the bearing surfaces. In this embodiment, the first circuit contact 丨 丨The 8 series is disposed on the substrate 107, and the plurality of second solder ball structures 26 are electrically connected to the plurality of first circuit contacts 11 8 through the substrate 1 〇2. The electrical paths formed by the plurality of plated-through lines (not shown), the plurality of second circuit contacts 1 2 2 and ^ the plurality of solder balls 1 2 3 are connected to an external circuit. In the embodiment shown in FIG. 5, the multi-chip package structure further includes a package body 1 2 8. The package body 1 2 8 is used for covering. Wafer carrier 104, the plurality of wafers 114a, 114b, 114c, 114d, and 114e, the plurality of first circuit contacts 118, and a portion of the upper surface of the substrate 102. Multi-chip package structure according to the present invention The wafer carrier can be realized by a heat sink to improve the heat generated by the multiple wafers of the multi-chip package structure. The carrier can also be realized by a substrate, wherein the substrate can be reinforced with glass fiber BT (bismaleimide- triazine) tree

Yue Yue 'or FR-4 fiberglass reinforced epoxy resin. In addition, the substrate can also be made of a ceramic substrate. A feature of the present invention is that a plurality of wafers are arranged in one

00698. ptd Page 11 1239081 V. Description of the invention (β) '' '" On a wafer carrier having a plurality of bearing surfaces, to achieve the purpose of multi-chip packaging. As shown in FIG. 6, it is a schematic top view of a wafer carrier according to another embodiment of the present invention. The wafer carrier 200 has a top surface 210a and five oblique side surfaces 2101), 21〇. c, 210d, 21oe, and 210f, and these surfaces are preferably capable of carrying at least six wafers thereon. As shown in FIG. 7, it is a schematic top view of a wafer carrier according to another embodiment of the present invention. The wafer carrier 300 has a top surface 3 1 〇a and six oblique side surfaces 310b, 31. 〇c, 310d, 310e, 310f, and 310g, and these watches can carry at least seven chips on it. Although the present invention has been disclosed in the foregoing embodiment, it is not used in the present invention. Anyone skilled in the art can make various changes and modifications without departing from the scope of the present invention. It shall be subject to the definition in the appended patent application scope. "Xi Siwei

00698. ptd Page 12 1239081 Brief description of the drawings [Simplified description of the drawings] Figure 1 is a schematic diagram of a stacked chip package structure of one of the prior art. FIG. 2 is a schematic diagram of another stacked chip package structure of the prior art. FIG. 3 is a schematic side view of a multi-chip package structure according to an embodiment of the present invention. Figure 4 is a schematic top view of the wafer carrier in Figure 3. Figure 5 is a schematic side view of a multi-chip package structure according to another embodiment of the present invention. Figure 6 is a schematic top view of a wafer carrier according to another embodiment of the present invention. Fig. 7 is a schematic top view of a wafer carrier according to another embodiment of the present invention. Description of drawing number: 10 stacked chip package structure 12 wafer 14 wafer 16 adhesive layer 18 substrate 20 adhesive layer 22 bonding wire _ 00698. ptd page 13 1239081

Brief description of the drawing 24 bonding wire 26 wire bonding 塾 28 solder ball pad 30 solder ball 32 package body 34 chip 36 adhesive layer 38 bonding wire 100 multi-chip package structure 102 substrate 104 wafer carrier 106 bottom surface 107 setting area 108 top surface 110a, ll〇b, lioc, ii〇d Beveled side 112 upper surface 114a, 114b, 114c, 114d, 114e chip 116 fresh line 118 circuit contact 120 lower surface 122 second circuit contact 123 solder ball 124 One solder ball structure 126 Second solder ball structure 128 Package 200 Top surface of wafer carrier 210a 210b, 210c, 210d, 210e, 210f Beveled surface 300 Top surface of wafer carrier 310a 310b, 310c, 310d, 310e > 310f ^ 31 〇g slant side table

Claims (1)

1239081 " ^ 一 ——___ VI. Scope of Patent Application '1. A multi-chip package structure, which includes ... a substrate having an upper surface, the upper surface having a setting area and a plurality of first A circuit contact; a wafer carrier having a bottom surface and a plurality of bearing surfaces, and the wafer carrier is provided on the setting area through the bottom surface; and a plurality of wafers are disposed on the The plurality of bearing surfaces are electrically connected to each of the first circuit contacts. 2 'The multi-chip package structure according to item 1 of the scope of patent application, wherein at least one wafer is disposed on each of the plurality of j bearing surfaces. 3. The multi-chip package structure according to item 1 of the scope of patent application, wherein the plurality of bearing surfaces include a top surface and at least four oblique side surfaces. 4. The multi-chip package structure according to item 3 of the patent application scope, wherein at least one chip is disposed on each of the top surface and the at least four oblique side surfaces. " 5. The multi-chip package structure according to item 1 of the scope of patent application, wherein the wafer «I carrier is made of a substrate, and the substrate material is made of glass fiber reinforced BT (bismaleimide-triazine) resin, FR- 4 A group of glass fiber reinforced epoxy resins and ceramic substrates | ' 1239081 VI. Patent application scope 6. The multi-chip package structure according to item 1 of the patent application scope, wherein the wafer carrier is made of a heat sink. 7. The multi-chip package structure according to item 1 of the scope of patent application, wherein the substrate further has a lower surface, and the lower surface has a plurality of second circuit contacts electrically connected to the plurality of first circuit contacts for electrical connection. 8. The multi-chip package structure according to item 7 of the scope of the patent application, wherein each of the second circuit contacts is formed with a solder ball, respectively, for electrically connecting to the external circuit. 9 The multi-chip package structure according to item 1 of the scope of patent application, wherein the plurality of first circuit contacts are located at the periphery of the setting area, and the chip is electrically connected to the substrate by wire bonding A plurality of first circuit contacts. 10. The multi-chip package structure according to item 1 of the scope of patent application, wherein the plurality of chips are electrically connected to each other by wire bonding. 11. The multi-chip package structure according to item 1 of the scope of the patent application, wherein the plurality of first circuit contacts are located on the setting area, and the bearing surface has a plurality of post-plated through lines, and the chip is formed by the Crystal (flip chin 1239081 The method is electrically connected to the through line, and is electrically connected to a plurality of ore lines, and the first circuit contacts are plated on the substrate. ^ The multi-chip package structure of item 11 of the patent scope of I 1 Ming, wherein the bottom surface of the crystal said shepherd # has a plurality of solder balls' and the plurality of key bonds = ^ is electrically conductive by the plurality of solder balls The first circuit contacts are connected to the substrate. 13. The multi-chip package structure according to item} of the patent application scope, wherein the chip carrier has a plurality of plated-through lines electrically connected to the plurality of load-bearing surface gates, and the plurality of chips are connected by the plurality of chips. Key-to-line circuits are electrically connected to each other. 14. The multi-chip package structure according to item 1 of the scope of the patent application, further comprising a shot body 'the packaging system covers the wafer carrier, the plurality of wafers, the plurality of first circuit contacts, and the substrate. Part of the top surface. 00698.ptd p. 17