KR19990028206U - Stacked Semiconductor Packages - Google Patents

Abstract

The present invention discloses a stacked semiconductor package using a substrate. The stacked semiconductor package of the present invention includes an insulating substrate. The insulating substrate has a square bottom plate and a pair of sidewalls formed perpendicular to the bottom plate along a pair of opposite edges of the bottom plate. On the bottom plate of the substrate, a semiconductor chip having a plurality of bonding pads on the top is placed. A plurality of inner leads are formed on the substrate so as to reach adjacent edges of the semiconductor chip from upper portions of both sidewall surfaces of the substrate. Solder balls are disposed on the bottom surface of the substrate, and are electrically connected to the inner leads through wires formed on the bottom plate, thereby providing a path for electrical connection with an external printed circuit board. Bonding pads of the semiconductor chip and the inner leads are electrically connected by wires. In addition, a protective layer made of a molding compound is formed on an upper portion of the portion including the first connection means, the inner leads, and the semiconductor chip. The stacked semiconductor package of the present invention is a stacked package in which at least two semiconductor packages having the above-described configuration are stacked, and a second connection electrically connecting the inner leads of the selected semiconductor package and the out leads of the remaining semiconductor package. It further comprises means.

Description

Stacked Semiconductor Packages

The present invention relates to a semiconductor package, and more particularly, to a stacked semiconductor package having a stacked structure and having a chip scale size.

Package diversification, miniaturization and multipinning are underway. In order to meet the demands of electronic devices such as small size, light weight, high speed, and high performance, semiconductor packages have been continuously developed in various forms. In addition, the proper use of the semiconductor package corresponding to the use of the electronic device becomes important. Logic semiconductors, such as central processing units (CPUs) and on-demand semiconductors (ASICs), require more multi-output pins as their functions become more advanced. The System On Silicon mindset pushes the growth of semiconductor chip sizes and pushes the size of packages. In addition to the above-mentioned problems, problems of package electrical characteristics and heat dissipation due to the higher signal transfer speed of the chip have become important issues in the structural design of the package. Packages corresponding to these include pin grid arrays (PGAs), ball grid arrays (BGAs), multi chip modules (MCMs), and quad flat packages (QFPs). There is an improvement type. For memory semiconductor products, the miniaturization and thinning of packages are the center of development. As a memory, there is a strong demand for packaging a large capacity semiconductor chip with high density. From this point of view, a thin Small Outerlead Package (TSOP) with a 1.0 mm package thickness, Ultra Thin Small Outerlead Package (UTSOP) or a vertical surface is further thinned to a 0.5 mm thickness. Package Vertical Packages (SVPs) have been developed. These packages are mounted at high density on a printed board to realize high density of the entire memory module.

In order to realize a noise resistant package at low cost, a plastic package having a multilayer lead frame has been developed. For low noise, inductance reduction is essential. However, the lead frame of this plastic package has a large parasitic inductance because it is a single metal plate. When noise occurs, the ceramic multilayer package is used to separate the power supply layer or the ground layer and lower the parasitic inductance to reduce the electromagnetic inductive effects generated between the wirings. However, the ceramic package has the advantage of low noise, but also has the disadvantage of high manufacturing cost.

1 is a schematic cross-sectional view of a stacked package according to a conventional embodiment.

Referring to FIG. 1, a conventional stacked package stacks a package such as SOP or TSOP and electrically connects respective corresponding out leads by a solder joint using a guide 6. . 1 and 1 'are semiconductor chips, 2 and 2' are wires, 3 and 3 'are outlead, 4 and 4' are pads on which the semiconductor chips 1 and 1 'are placed, respectively, 5 and 5 'Represents the substrate, and 7 and 7' represent the body of the package.

However, the conventional laminated package described above has a complicated process by connecting the corresponding leads to each other by solder joints and has a problem in reliability at the solder joint portion. In addition, by using a package of the same type as the TSOP, the package occupies a large area on the external printed circuit board, which makes it difficult to reduce the size and thickness of the product. In addition, it has a disadvantage that signal transmission is slower than stacking chip size packages. In addition, the package of the above structure has to be equipped with a heat sink (Heat sink, or Heat spreader) for the release of heat generated during operation, there is a problem that the manufacturing cost is significantly increased.

Accordingly, an object of the present invention is to provide a stacked semiconductor package capable of improving the signal transfer speed between stacked packages and reducing the area occupied by the package to be close to the chip size.

1 is a cross-sectional view of a stacked semiconductor package according to a conventional embodiment.

2 is a partial cross-sectional view of a stacked semiconductor package according to an embodiment of the present invention.

3 is a cross-sectional view of a stacked semiconductor package using the semiconductor package of FIG. 2.

4 is a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention.

5 is a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention.

6 is a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10, 30, 50: semiconductor chip 12, 32: bonding pad

14, 34: substrate 16, 36: wiring

18, 38: inner lead 20: connecting member

22, 42: molding compound 24, 44: wire

26, 46: solder ball

According to an aspect of the present invention, a laminated semiconductor package includes an insulating substrate having a rectangular bottom plate and a pair of sidewalls formed to be perpendicular to the bottom plate along a pair of opposite edges of the bottom plate; A semiconductor chip disposed on a bottom plate of the substrate and having a plurality of bonding pads thereon; A plurality of inner leads formed on the substrate to reach adjacent edges of the semiconductor chip from an upper portion of each sidewall surface; An outer lead attached to a bottom surface of the substrate and electrically connected to the inner leads through wirings formed on the bottom plate, the outer leads for electrical connection with an external printed circuit board; First connecting means for electrically connecting the bonding pads of the semiconductor chip and the inner leads; And a protective layer formed on an upper portion of the portion including the first connecting means, the inner leads, and the semiconductor chip to protect the first connecting means, the inner leads, and the semiconductor chip. A stacked package in which at least two packages are stacked, the package further includes second connecting means for electrically connecting the inner leads of one of the semiconductor packages selected from the semiconductor packages and the out leads of the remaining semiconductor chips. The out leads use solder balls and are integrated with the substrate.

According to another aspect of the present invention, a laminated semiconductor package includes an insulating substrate having a rectangular bottom plate and a pair of sidewalls formed to be perpendicular to the bottom plate along a pair of opposite edges of the bottom plate; A semiconductor chip disposed on a bottom plate of the substrate and having a plurality of bonding pads thereon; A plurality of inner leads formed on the substrate to reach adjacent edges of the semiconductor chip from an upper portion of each sidewall surface; An outer lead attached to a bottom surface of the substrate and electrically connected to the inner leads through wirings formed on the bottom plate, the outer leads for electrical connection with an external printed circuit board; First connecting means for electrically connecting the bonding pads of the semiconductor chip and the inner leads; And a protective layer formed on an upper portion of the portion including the first connecting means, the inner leads, and the semiconductor chip to protect the first connecting means, the inner leads, and the semiconductor chip. A first semiconductor package having at least one package stacked thereon;

A semiconductor chip having a plurality of bonding pads; A plurality of leads including an inner lead electrically connected to bonding pads of the semiconductor chip, and an outer lead extending from the inner lead to protrude outwardly; Third connecting means for electrically connecting the inner lead and the bonding pads of the semiconductor chip; And at least one second semiconductor package including an insulative body portion surrounding the third connecting means, the inner lead, and the portion including the semiconductor chip.

The second semiconductor package is stacked on the first semiconductor package, and the second connecting means of the second semiconductor package and the out lead of the first semiconductor package are electrically connected to each other. Here, it is preferable that solder balls are used for the out leads of the first semiconductor package, and more preferably, the solder balls are used in an integrated state with the substrate.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

<Example 1>

FIG. 2 is a partial cross-sectional view of a stacked semiconductor package according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating a configuration of a stacked package formed by using the semiconductor package of FIG. 2 as a lower layer package.

2 and 3, the stacked semiconductor package of the present invention is a quad flat type and includes an insulating substrate 14. The insulating substrate 14 has a rectangular bottom plate and a pair of sidewalls formed perpendicular to the bottom plate along a pair of opposite edges of the bottom plate. On the bottom plate of the substrate 14, a semiconductor chip 10 having a plurality of bonding pads 12 thereon is placed. A plurality of inner leads 18 are formed on the substrate so as to reach adjacent edges of the semiconductor chip from the tops of both sidewall surfaces of the substrate 14. Solder balls 26 are disposed on the bottom surface of the substrate, and the inner leads 18 and the solder balls 26 are electrically connected to each other through wires 16 formed on the substrate 14 to form an external printed circuit. Provides a path for electrical connection with the substrate. The bonding pads 12 and the inner leads 18 of the semiconductor chip 10 are electrically connected by wires 24. The wire 24 is preferably bonded to a portion of the inner lead 18 formed on the bottom surface to which the semiconductor chip is attached. In addition, a protective layer 22 made of a molding compound such as a soluble epoxy resin or a curable epoxy resin is formed on the upper portion of the wire 18, the inner leads 18, and the portion including the semiconductor chip 10. have. When another package is stacked between the protective layer 22 and the inner lead 18 formed on the sidewall of the substrate 14, a connecting member 20 for electrically connecting the corresponding leads is inserted thereinto. It is tangentially facing.

Referring to FIG. 3, the semiconductor package having the configuration of FIG. 2 (hereinafter referred to as a lower layer package) is located in the lower layer in the stacked package. At the top thereof, another package (hereinafter referred to as an upper layer package) having the same configuration except for the connecting member 20 is placed on the lower layer package so as to face the protective layer 42 thereof. . The connecting member 20 is then joined by a forming process and bonded to a corresponding solder ball 46 of the upper layer package.

In the stacked semiconductor package having the above-described configuration, the inner leads 18 and 38 may be configured to include a portion in which an insulating film is partially coated thereon for insulation between adjacent inner leads. In this case, the coated part consists of polyimide.

Meanwhile, at least two semiconductor packages may be stacked in the stacked semiconductor package. In this case, at least one first semiconductor package having a logic type chip, such as an ASIC chip, and a memory chip, such as a DRAM or an SRAM, may be used. It is also possible to have a structure in which at least one second semiconductor package having a stacked structure. In all the above cases, the use of solder balls as outleads for connection with an external printed circuit board has the advantage of reducing the mounting area, but other types of leads other than solder balls may be used.

<Example 2>

4 is a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention. Unlike the previous embodiment, the upper layer package has a connection member 20, and an extended end of the connection member 20 is formed in a forming process. Are bonded to the solder balls of the bottom layer package. In this embodiment, the solder ball is additionally formed in the lower portion of the connection member 20 bonded to the solder ball 26 of the lower layer package for bonding with the external printed circuit board.

<Example 3>

5 is a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention, and shows a structure in which three semiconductor packages are stacked. As described above, in the case of stacking three or more packages, the bonding pad surface of the semiconductor chips 30 and 50 in each package is opposite to the bonding pad surface of the semiconductor chip 10 in the lowermost layer. It is laminated so as to have a structure. At this time, the connecting member 21 has a configuration projecting inwardly facing each other so as to be bonded to the corresponding solder ball of the package of each layer.

<Example 4>

6 is a cross-sectional view of a stacked semiconductor package according to still another embodiment of the present invention. The connecting member 20 of the package shown in FIG. 2 is formed in a desired bent state, and a TSOP type or SOJ type package is stacked thereon. You can have one structure. In this case, the connecting member 23 and the corresponding outlead 3 of the upper layer package are bonded.

When bonding to an external printed circuit board using two or more packages as described above, since the substrate formed in the lowermost layer serves as a simple support, it is possible to implement a stacked package without configuring a circuit.

As described above, the stacked semiconductor package of the present invention has the following effects.

First, the present invention forms a lead on a substrate (hard and flexible) used in a chip size package or configures a film as an out lead, so that a stacked package can be implemented in all chip size packages.

Second, by using a substrate when stacking an existing TSOP or QFP package, delay of electrical signal transmission is prevented.

Third, the use of a substrate that facilitates heat dissipation eliminates the need for a heat dissipation plate, thereby lowering the manufacturing cost.

Fourth, by attaching a lead or a pattern film to the ball grid array substrate, it is possible to configure a ball grid array type of packages in a stacked type.

Fifth, it is possible to configure a semiconductor package including a memory chip and a semiconductor chip including a logic chip in a stacked type, and stacking is possible even in a multi-pin package.

Although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (17)

An insulating substrate having a rectangular bottom plate and a pair of sidewalls formed perpendicular to the bottom plate along a pair of opposite edges of the bottom plate; A semiconductor chip disposed on a bottom plate of the substrate and having a plurality of bonding pads thereon; A plurality of inner leads formed on the substrate to reach adjacent edges of the semiconductor chip from an upper portion of each sidewall surface; An outer lead attached to a bottom surface of the substrate and electrically connected to the inner leads through wirings formed on the bottom plate, the outer leads for electrical connection with an external printed circuit board; First connecting means for electrically connecting the bonding pads of the semiconductor chip and the inner leads; And A semiconductor package formed on an upper portion of the portion including the first connecting means, the inner leads, and the semiconductor chip, and including a protective layer protecting the first connecting means, the inner leads, and the semiconductor chip; Is a stacked package in which at least two are stacked, and further comprising second connecting means for electrically connecting the inner leads of one of the semiconductor packages selected from the semiconductor packages and the out leads of the remaining semiconductor chips. package. The multilayer semiconductor package of claim 1, wherein the first connection means is a conductive wire. The multilayer semiconductor package of claim 1, wherein one end of the second connection means is interposed between the inner layer of the protective layer and the inner lead of the semiconductor package at a lowermost layer and is electrically connected to the inner lead. The multilayer semiconductor package of claim 1, wherein the inner leads include a portion coated with an insulating layer thereon for insulation between adjacent inner leads. 5. The stacked semiconductor package of claim 4 wherein the coated portion is comprised of polyimide. 2. The stacked semiconductor package of claim 1, wherein the at least two semiconductor packages comprise at least one first semiconductor package having an ASIC chip and at least one second semiconductor package having a memory chip. 7. The stacked semiconductor package of any one of claims 1 to 6, wherein the out leads are solder balls. An insulating substrate having a rectangular bottom plate and a pair of sidewalls formed perpendicular to the bottom plate along a pair of opposite edges of the bottom plate; A semiconductor chip disposed on a bottom plate of the substrate and having a plurality of bonding pads thereon; A plurality of inner leads formed on the substrate to reach adjacent edges of the semiconductor chip from an upper portion of each sidewall surface; An outer lead attached to a bottom surface of the substrate and electrically connected to the inner leads through wirings formed on the bottom plate, the outer leads for electrical connection with an external printed circuit board; First connecting means for electrically connecting the bonding pads of the semiconductor chip and the inner leads; And a protective layer formed on an upper portion of the portion including the first connecting means, the inner leads, and the semiconductor chip to protect the first connecting means, the inner leads, and the semiconductor chip. A first semiconductor package having at least one package stacked thereon; A semiconductor chip having a plurality of bonding pads; A plurality of leads including an inner lead electrically connected to bonding pads of the semiconductor chip, and an outer lead extending from the inner lead to protrude outwardly; Third connecting means for electrically connecting the inner lead and the bonding pads of the semiconductor chip; And at least one second semiconductor package including an insulative body portion surrounding the third connecting means, the inner lead, and the portion including the semiconductor chip. The second semiconductor package is stacked on top of the first semiconductor package, the second semiconductor package of the second semiconductor package and the stacked semiconductor package, characterized in that the out lead of the first semiconductor package is electrically connected. The multilayer semiconductor package of claim 8, wherein the first and third connection means are conductive wires. The multilayer semiconductor package of claim 8, wherein each of the first semiconductor package and the second semiconductor package is one. The method of claim 10, wherein one end of the second connecting means is interposed between the inner lead and the protective layer of the first semiconductor package located in the lowermost layer, is electrically connected to the inner lead, The other end of the multilayer semiconductor package, characterized in that electrically connected to the out lead of the second semiconductor package, respectively. The multilayer semiconductor package of claim 8, wherein the inner leads of the first semiconductor chip include a portion coated with an insulating layer thereon for insulation between adjacent inner leads. 13. The stacked semiconductor package of claim 12, wherein the coated portion is made of polyimide. 10. The stacked semiconductor package of claim 8, wherein the stacked semiconductor package comprises at least one first semiconductor package having an ASIC chip and at least one second semiconductor package having a memory chip. 10. The stacked semiconductor package of claim 8, wherein the second semiconductor package is a TSOP type. 10. The stacked semiconductor package of claim 8, wherein the second semiconductor package is an SOJ type. 18. The stacked semiconductor package according to any one of claims 8 to 17, wherein the out leads of the first semiconductor package are solder balls.