KR200180815Y1 - Semiconductor package having capacitor - Google Patents

Abstract

The present invention discloses a semiconductor package having a capacitor having a square plate structure. The capacitor of the semiconductor package is placed in an opening region of the package substrate, the first metal plate electrically contacting the first wiring, the second metal plate electrically contacting the second wiring, the first metal plate and the second metal plate. It includes a first insulating film interposed therebetween. A plurality of bonding pads are formed on the upper portion of the semiconductor chip, and the semiconductor package has an opening region in the center thereof, and the opening region has a stepped structure in which its cross-sectional area becomes narrower toward the lower portion, and the semiconductor chip is attached. A bottom surface of the opening area, a step surface formed on the top of the bottom surface of the opening area and an inner wall surface of the step surface. The leads are formed on the stepped surfaces of the package substrate, respectively, and are electrically connected to bonding pads of the semiconductor chip, and a plurality of leads extend and protrude out of the package substrate for signal transmission with an external circuit. The inner wall surface of the opening region of the package substrate is formed with a first wiring and a second wiring, respectively, the first wiring is electrically connected to the Vcc lead among the leads, and the second wiring is an inner wall surface of the other side of the package substrate. And is electrically connected to the Vss lead of the leads.

Description

Semiconductor Package with Capacitors

The present invention relates to a semiconductor package, and more particularly to a semiconductor package having a capacitor.

Package diversification, miniaturization and multipinning are underway. In order to meet the demands of electronic devices such as small size, light weight, high speed, and high performance, semiconductor packages have been continuously developed in various forms. In addition, the proper use of the semiconductor package corresponding to the use of the electronic device becomes important. Logic semiconductors, such as central processing units (CPUs) and on-demand semiconductors (ASICs), require more multi-output pins as their functions become more advanced. System-on-silicon thinking pushes the expansion of semiconductor chip sizes and increases the size of packages. At the same time, the problems of package electrical characteristics and heat dissipation due to the high speed of chips have become important issues in the structural design of packages. Packages corresponding to these include pin grid arrays (PGAs), ball grid arrays (BGAs), multi chip modules (MCMs), and quad flat packages (QFPs). There is an improvement type. For memory semiconductor products, the miniaturization and thinning of packages are the center of development. As a memory, there is a strong demand to package a large capacity semiconductor chip with high density. From this point of view, a thin Small Outerlead Package (TSOP) with a 1.0 mm package thickness, Ultra Thin Small Outerlead Package (UTSOP) or a vertical surface is further thinned to a thickness of 0.5 mm. Package Vertical Packages (SVPs) have been developed. These packages are mounted at high density on a printed board to realize high density of the entire memory module.

In order to realize a noise resistant package at low cost, a plastic package having a multilayer lead frame has been developed. For low noise, inductance reduction is essential. However, since the lead frame of the conventional plastic package is a single layer metal plate, the parasitic inductance is large. When noise occurs, the ceramic multilayer package is used to separate the power supply layer or the ground layer and lower the parasitic inductance to reduce the electromagnetic inductive effects generated between the wirings. However, the ceramic package has the advantage of low noise, but also has the disadvantage of high manufacturing cost.

1 is a plan view of a lead frame according to a conventional embodiment, and shows a configuration in which a capacitor is installed in the lead frame to reduce noise.

Generally in lead-on-chip (LOC) type, a capacitor is electrically connected between the first bus bar connected to the power supply terminal Vcc and the second bus bar connected to the ground terminal Vss to remove noise. do. The capacitor bonds the bonding pads of the semiconductor chip with the leads of the lead frame, and then mounts the capacitor.

However, this package reduces the noise of the input signal, while acting as a factor that impedes the flow of the molding compound during the molding process, causing the die to tilt, or creating voids in the molding compound, causing the package to fail. do.

Accordingly, an object of the present invention is to provide a semiconductor package having a capacitor capable of reducing noise while preventing a flow of a molding compound during a molding process.

1 is a plan view of a lead frame according to a conventional embodiment.

2 is a plan view of a capacitor according to an embodiment of the present invention.

3 is a cross-sectional view taken along the line II-II 'of FIG. 2;

4 is a cross-sectional view of a package substrate of a semiconductor package having a capacitor according to an embodiment of the present invention.

5 is a plan view of a semiconductor package having a capacitor according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10 capacitor 12 insulating film

14 metal plate 20 package substrate

30: lead

According to the present invention, a semiconductor package having a capacitor includes a semiconductor chip having a plurality of bonding pads thereon; The opening area has a central area, and the opening area has a stepped structure in which its cross-sectional area becomes narrower toward the bottom, and has a first surface formed on the bottom surface of the opening area to which the semiconductor chip is attached and on the bottom surface of the opening area. A package substrate including a step surface, an upper inner wall surface of the first step surface, and at least one second step surface on the first step surface; A plurality of leads each formed on the first stepped surface of the package substrate and electrically connected to bonding pads of the semiconductor chip and extending and protruding outward for signal transmission with an external circuit; A first wiring formed in a first predetermined portion of an inner wall surface of the opening region of the package substrate and a first predetermined portion of the second stepped surface and electrically connected to each other, and electrically connected to a Vcc lead among the leads; ; A second wiring formed on the second predetermined portion of the inner wall surface of the other side of the opening area of the package substrate and the second predetermined portion of the second stepped surface and electrically connected to each other, and electrically connected to the Vss lead of the leads; ; A first metal plate disposed in an opening region of the package substrate and electrically contacting the first wiring, a second metal plate electrically contacting the second wiring, and interposed between the first metal plate and the second metal plate; 1 includes a capacitor including an insulating film.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

2 is a plan view showing the configuration of a capacitor in a ceramic package having a capacitor according to an embodiment of the present invention, Figure 3 is a cross-sectional view taken along the line II-II 'of Figure 2, Figure 4 is a 2 is a plan view of the capacitor placed on the package substrate of FIG. 2.

2 and 3, the capacitor of the present invention has a rectangular structure and has a portion protruding outward at its opposite vertex. The capacitor has a structure in which two metal plates 14 are inserted into the dielectric at predetermined intervals, and the metal plate 14 is exposed on the bottom surface of the portions protruding to both sides.

The package substrate 20 made of ceramic is provided so that the capacitor 10 having the above-described configuration is installed in the semiconductor package. The ceramic substrate 20 has a rectangular opening region at a central portion thereof, and the opening region has a stepped structure in which its cross-sectional area is narrowed toward the bottom thereof, and a semiconductor chip (not shown) having bonding pads is attached thereto. A bottom surface of the opening region, two stepped surfaces formed on the top of the bottom surface of the opening region, and an inner wall surface of the stepped surface.

On the lower stepped surface of the package substrate 20, a plurality of leads 30 electrically connected to the bonding pads of the semiconductor chip and extending and protruding outward for signal transmission with an external circuit are disposed. Among the plurality of leads, two leads located at opposite vertices are electrically contacted with wires formed at opposite vertices of the upper inner wall surface and the upper step surface of the lower step surface, respectively. The upper stepped surface of the package substrate is a portion in which the protruding portion of the capacitor of FIG. 3 is placed and contacts. For accurate contact alignment between the exposed metal plate of the capacitor 10 and the wiring formed on the upper stepped surface, The upper stepped surface of the package substrate 20 has different depths from its surface. More specifically, since the thickness of the portion projecting to the left side of FIG. 3 is thinner than the thickness of the portion projecting to the right side, the depth of the left stepped surface of the package substrate 20 of FIG. It is made shallower than the depth of the face, and preferably the thickness of the left protrusion of the capacitor of FIG. 3 is approximately equal to the depth of the left stepped surface of FIG. 4, that is, the depth from the surface of the package substrate 20 to the upper left stepped surface. 3, the thickness of the right protrusion of the capacitor of FIG. 3 is approximately equal to the depth of the right step surface of FIG. 4, that is, the depth from the surface of the package substrate 20 to the right upper step surface. One side of the wires 22 formed at opposite vertices of the opening area of the package substrate is electrically connected to the power supply voltage Vcc lead, and the other wire is electrically connected to the ground voltage Vss lead. Therefore, Vcc and Vss are applied to the lead when the package is driven, so that the capacitor operates to reduce noise.

In the capacitor, the first metal plate is positioned above the second metal plate, and preferably further includes an insulating film formed on the first metal plate. In addition, the stepped surface of the package substrate may be composed of two or more, in this case, the selected two adjacent stepped structure should be a structure that is matched with each other so that the wiring formed on the upper stepped surface and the two metal plates of the capacitor.

Although not shown in the drawings, the semiconductor chip is placed on the bottom surface of the package substrate 20 and bonded by leads and wires formed on the lower stepped surface.

As described above, the semiconductor package of the present invention has a plate-shaped capacitor, thereby reducing noise during operation of the package and making the flow rate of the molding compound introduced when the molding compound flows in the same manner. This equalization of the flow velocity prevents the occurrence of bending and cavitation of the body portion consisting of the molding compound.

Although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (8)

A semiconductor chip having a plurality of bonding pads thereon; The opening area has a central area, and the opening area has a stepped structure in which its cross-sectional area becomes narrower toward the bottom, and has a first surface formed on the bottom surface of the opening area to which the semiconductor chip is attached and on the bottom surface of the opening area. A package substrate including a step surface, an upper inner wall surface of the first step surface, and at least one second step surface on the first step surface; A plurality of leads each formed on the first stepped surface of the package substrate and electrically connected to bonding pads of the semiconductor chip and extending and protruding outward for signal transmission with an external circuit; A first wiring formed in a first predetermined portion of an inner wall surface of the opening region of the package substrate and a first predetermined portion of the second stepped surface and electrically connected to each other, and electrically connected to a Vcc lead among the leads; ; A second wiring formed on the second predetermined portion of the inner wall surface of the other side of the opening area of the package substrate and the second predetermined portion of the second stepped surface and electrically connected to each other, and electrically connected to the Vss lead of the leads; ; A first metal plate disposed in an opening region of the package substrate and electrically contacting the first wiring, a second metal plate electrically contacting the second wiring, and interposed between the first metal plate and the second metal plate; A semiconductor package having a capacitor comprising a capacitor comprising an insulating film. The first predetermined portion of the inner wall surface on one side of the opening region of the package substrate and the first predetermined portion of the second step surface are located at one vertex of the opening region, And a second predetermined portion of the inner wall surface of the other side and a second predetermined portion of the second stepped surface are located at the other vertex opposite to the one vertex. 2. The semiconductor package of claim 1, wherein the second stepped surface is one. The first predetermined portion of the second stepped surface on one side of the opening region of the package substrate and the second predetermined portion of the inner wall surface on the other side of the opening region of the package substrate have different depths from the surface of the substrate. And a depth of the capacitor is equal to a thickness of the protruding portions of the capacitor that face each other. The method of claim 1, wherein the opening area of the package substrate has a rectangular structure, and the leads are partially exposed at each side of the step surface, and are electrically connected to the bonding pads of the semiconductor chip. A semiconductor package having a capacitor. 6. The semiconductor package of claim 5, wherein the bonding pads of the semiconductor chip and the leads exposed on the stepped surfaces of the opening area of the package substrate are electrically connected to each other by wires. The semiconductor device of claim 5, wherein the Vcc and Vss leads are formed at opposite vertices of the stepped surface of the rectangular structure, and the capacitors are separated from each other by the first metal plate, the second metal plate, and an insulating film interposed therebetween. And a rectangular plate-like structure in which the two metal plates are stacked at predetermined intervals, and protruded from a vertex of the rectangular plate so as to contact the Vcc and Vss leads formed at the vertex of the step surface. A semiconductor package having a capacitor, characterized in that. The semiconductor package according to claim 1, wherein the capacitor further comprises an insulating film on which the first metal plate is positioned above the second metal plate, and formed on the first metal plate.