TW457673B - Multi-chip module - Google Patents

Abstract

A multi-chip module which comprises a first chip configured on the upper surface of a substrate with wire bonding; and a second chip configured on the lower surface of the substrate with flip-chip bonding; in which, the first chip and the second chip are of the same type. The upper surface of the substrate is configured with a plurality of wire-bonding pads for electrical connection with the first chip and the lower surface of the substrate is configured with a plurality of flip-chip bonding pads for electrical connection with the second chip. According to the present invention, because the first and the second chips are both connected to the substrate with upward bond pad relative to the substrate, the address assignment of the bond pads on both semiconductor chips are matched with each other so that the circuit layouts for the upper and the lower surfaces of the substrate can be of similar designs and the plated vias can be used to electrically connect the same circuits on the upper and the lower surfaces of the substrate.

Description

Description of the invention (1) [Field of the invention] The present invention relates to a capacity ag + module (MCM), and particularly to 130 / equipment, manufacturing (mu 出 -chip, said chip is wire bonding and flip chip bonding respectively == There is one side. J is eight degrees and y, on a substrate. [Previous technology] As electronic products become thinner and thinner, the abundant conductors used for tablets and for providing external circuit connections have become day-to-day. Also, the need for miniaturization of thin, light, small, and high operating speeds is becoming more and more attractive in many electronic devices. "S κ 4+: Japanese-Japanese film packaging structure has never been added and attracted many days. The chip package structure can minimize the system speed limitation by combining two or more wafers in a single package structure. &Amp; Outer 'multi-chip package structure can reduce the length of the connection lines between chips. Reduce signal delay and access time. Chip package structure, which is to install two or more chips side by side on the main mounting surface of the common substrate. The connection between the chip and the conductive lines on the common substrate is generally by wire bonding Wi re bond ing) was achieved. However, the disadvantage of this side-by-side multi-chip package structure is that the packaging efficiency is too low, because the area of the common substrate will increase with the increase in the number of chips. Therefore, the semiconductor industry has developed a stacked chip package structure 100 It generally includes two wafers 110 and 130 stacked on top of each other (as shown in the first figure). The wafer 110 is fixed to the upper surface of a substrate 150 by a glazing layer 112. The wafer 110, There is a winning layer 1 3 2 in the 130 room. The chip 11 0, 1 30 points and other "丨" with a bond wire (bondi ng wi re) 1 1 4, 1 34 is electrically connected to the base Chip package structure is side-by-side

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Page 4 __Amendment 457673 Case No. 89101234 V. Description of the invention (2) A plurality of wire-bonding wires on the upper surface of the board 150. A plurality of solder balls are provided on the lower surface of the substrate 150.塾 1 5 4 is a plurality of wire bonding pads 152 which are electrically connected to the upper surface of the substrate 150. Each solder ball pad 1 5 4 is provided with a solder ball 1 5 6 for electrical communication with the outside world. The wafer 110, 130, the connecting wires 114, 134, and a portion of the upper surface of the substrate 50 are covered with a gel 1 60. However, when the stacked wafer package structure 100, the wafers stacked on each other have the same size At this time, the upper wafer will hinder the wire bonding operation of the lower wafer 110. In addition, the length and height of the connecting wire 134 used to connect the upper wafer 130 to the substrate 150 wire bonding pad 152 will increase relatively, which will increase the difficulty of the wire bonding operation For example, the longer and the higher the path type of the wire is, the easier it is to break the wire during wire bonding operation, and the easier it is to cause wi re sweep phenomenon when sealing the plastic package. High-path type wires and stacked chips, which require Higher encapsulant thickness is sufficient to cover wires and stacked wafers, thereby reducing packaging efficiency. R: .y; As shown in the second figure, US Patent No. 5,973,403 discloses another A multichip stacked device, which stacks a wire-bonded wafer on a flip-chip bonded wafer. The multi-chip stacked device includes a first semiconductor wafer 210 provided on a substrate 220 and a first wafer in a flip-chip manner. Two semiconductor wafers 230 are stacked on the first semiconductor wafer 210 and are electrically connected to the substrate 220 by wire bonding. The upper surface of the substrate 220 is provided with a plurality of wire-bonding pads 222 and a plurality of flip-chips. A flip-chip bonding pad 224 is provided with a plurality of solder ball pads 226 on the lower surface of the substrate 220. The first semiconductor wafer 2 10 is a cover bonded to the substrate 220 by a solder joint. Crystal bonding pad 224, the first

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4 5 7 8 7 3 Cable number V. Description of the invention (3) The second semiconductor wafer 2 3 0 is connected to the substrate by using a plurality of bonding wires. On the wire bonding pad 222. Since the lower wafer 21o is electrically connected to the substrate 220 using a flip-chip bonding method, it is not hindered by the upper wafer 23o. However, when the semiconductor wafers 21 and 230 are of the same type, the address assignments of the bond pads on the conductor wafers 21 and 230 are mirror images of each other (because of the semiconductor wafers) 210 is a flip-chip bonding method with the face down (referring to the wafer pad facing down on the substrate). Therefore, the address configuration of the plurality of wire bonding pads 222 (refer to addresses A 1 to D7 in the third figure) is the address configuration of the plurality of flip-chip bonding pads 2 2 4 (refer to the address in the third figure) A, i to D'7) are mirrors of each other. Therefore, the circuit layout of the substrate (circuit 1 ay ouΐ) will be quite complicated, and the density and length of the conductive lines (not shown in the third figure) on the substrate will be greatly increased. The longer the conductive line, the greater its impedance, inductance, and noise " large " thus affecting the electrical performance of the final package structure. In addition, the larger inductance value causes the semiconductor package structure to consume more power, and makes the integrated circuits and wires in the chip more susceptible to power surges. In addition, the connection wire 223 for connecting the upper layer chip 230 to the substrate 2 220 wire bonding pad 222 is the same as the aforementioned stacked chip package structure 1000, and its length and height are relatively increased, which will increase the difficulty of wire bonding operation. degree. As mentioned earlier, the longer and higher-path wire type is, the easier it is to break the wire during wire bonding operation, and the more likely it is to cause wire sweep during the encapsulation process. The longer and higher path type wires and stacked wafers, the higher the thickness of the encapsulant needed to cover the wires and stacked wafers, thereby reducing packaging efficiency.

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457673 Guang-_Case No. 8910] M4__I month g amendment V. Description of the invention (5) The two semiconductor wafers are respectively arranged on the upper surface and the lower surface of a substrate, wherein the two semiconductor wafers are connected by wire bonding and flip-chip bonding, respectively. The substrates are electrically connected, thereby reducing the thickness of the multi-chip package structure and improving the packaging efficiency. Another object of the present invention is to provide a multi-chip package structure including two semiconductor wafers respectively disposed on an upper surface and a lower surface of a substrate, wherein the two semiconductor wafers are electrically connected to the substrate by wire bonding and flip-chip bonding, respectively. This reduces the difficulty of bonding wires of multi-chip package structures. Another object of the present invention is to provide a multi-chip package structure including two semiconductor wafers respectively disposed on an upper surface and a lower surface of a substrate, wherein the two semiconductor wafers are electrically connected to the substrate by wire bonding and flip-chip bonding, respectively. The semiconductor connection is used to improve the electrical performance of the chip sealing structure. A multi-chip package structure according to a preferred embodiment of the present invention mainly includes a first chip provided on a substrate upper surface by wire bonding and a second chip provided on a flip-chip bonding method. The lower surface of the substrate, wherein the first and second wafers are of the same type. A plurality of wire-bonding pads are provided on the upper surface of the ϋ, a plurality of flip-chip bonding pads and a plurality of solder ball pads are provided on the lower surface of the substrate, and the plurality of wire-bonding pads are provided. The pad and the plurality of flip-chip bonding pads are electrically connected to the corresponding solder ball pads. Since the first and second wafers are bonded to the substrate with the wafer pads facing up, the address configurations of the wafer pads on the two semiconductor wafers coincide with each other. Therefore, the upper and lower surfaces of the substrate are electrically conductive. The circuit layout can be similar to the design.

^ 〇〇 ~ 008.ptc Page 8 Case No. 89101234 Λ_Ά Revision 457673 V. Description of the invention (6) Electrically connect the same conductive lines on the upper surface and the lower surface of the substrate. In order to make the above and other objects, features, and advantages of the present invention more apparent, the preferred embodiments of the present invention will be described in detail below, in conjunction with the accompanying drawings, as follows. [Explanation of the invention] 凊 Referring to the fourth figure, it discloses a multi-chip package structure according to the present invention—a preferred embodiment, which mainly includes two semiconductor wafers 2 and 0, which are respectively disposed on the upper surface and the lower surface of a substrate 2 60. surface. The upper surface of the substrate 26 is provided with a plurality of wire-bonding pads 2 6 2, and the lower surface of the substrate is provided with a plurality of flip-chip bonding pads 264 and a plurality of solder ball pads 2 6 6. The plurality of wire bonding pads 262 and the plurality of flip-chip bonding pads 2 6 4 are electrically connected to the corresponding solder ball bonding pads 266 via conductive lines and plated through holes on the substrate. A solder ball 268 is provided on each solder ball pad 266 on the lower surface of the substrate 26 to communicate with the outside. The substrate 26Q can be formed of a glass fiber reinforced BT (bUmaleimide-triazine) resin or a core layer made of FR-4 glass fiber reinforced epoxy resin (fibergUss reinforc epoxy resin). In addition, @ 基板 260 also has a ceramic substrate. The substrate 260 is characterized by only two layers of conductive circuits (located on the upper surface and the lower surface of the substrate 2 respectively), which can achieve the multi-chip package of the invention.

Page 9 May / Refer to the fourth figure. According to the manufacturing method of the present invention, the semiconductor wafer 230 is fixed on the upper surface of the substrate 26 with an adhesive layer such as an epoxy adhesive. The semiconductor chip 230 is electrically connected to a plurality of wire bonding pads (bonding bonding pads) on the upper surface of the soil plate 260 by using bonding wires 232.

Page 10. ^ 4576 73 Amendment No. 89101234 V. Description of the invention (8) Disconnection and line punching phenomenon, and improve the yield of line operation. In addition, the shorter connecting line 232 has better electrical performance, and can reduce the thickness of the sealing compound, thereby also improving packaging efficiency. Compared with U.S. Patent No. 5,801,072 and U.S. Patent No. 5,973,403, when two semiconductor wafers of a multi-chip package structure are of the same type, and have the same bond pad address configuration, In the case of 'assignment', the address assignments of wafer pads of the semiconductor wafer wafer pads of the top and bottom semiconductor wafers of U.S. Patent No. 5,80,072 and U.S. Patent No. 5,973,403 are mirror images of each other, However, a complicated circuit layout of the conductive circuit of the substrate is required to electrically connect the upper and lower semiconductor wafers to each other. In contrast to the design of the present invention, the two wafers 2 丨 0, 2 3 0 are bonded to the substrate 26 with the wafer pads facing up to the substrate 260. Therefore, the address configuration of the wafer pads on the two semiconductor wafers coincide with each other. Therefore, the conductive circuit circuit layout table of the upper surface and the lower surface of the substrate 260 is designed, and the same conductive circuits on the upper surface and the lower surface of the substrate are electrically connected with the through holes 261. Although the present invention has been disclosed with the foregoing preferred embodiments, anyone skilled in the art can make various changes without departing from the spirit and scope of the present application within the scope of the present invention. The scope of the patent is defined by the protection scope of the present invention 4 5 7 6 73 case number 89101234, a simple explanation of the revised drawing [illustration] Figure 1: a cross-sectional view of a conventional stacked chip package structure; Figure 2: Sectional view of a multi-wafer stacking device according to US Patent No. 5 9734 0 3; FIG. 3: Top view of a substrate for the multi-wafer stacking device of FIG. 2; Circle 4: A preferred implementation according to the present invention A cross-sectional view of the multi-chip package structure of the example; and FIG. 5: a top view of a substrate used in the multi-chip package structure of FIG. 4. Drawing number description 100 stacked chip package structure 110 wafer 110a wafer pad 112 adhesive layer 114 connection line 130 wafer 130a wafer 132 adhesive layer 134 connection line 150 substrate 152 wafer connection pad 154 solder ball pad 156 solder ball 210 wafer 220 substrate 222 line Connect 224 flip-chip bonding pads 226 solder ball pads 230 wafers 260 substrate 262 wire bonding pads 264 flip-chip bonding pads 266 solder ball pads 268 solder balls 270 filler 280 sealant A1 to D, 7 Address

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Claims (1)

457673 ___Case No. 89101234__Year Month Amendment VI. Patent application scope 1 A multi-chip package structure (multichip module), which includes: 〃 A substrate 'has an upper surface and a lower surface' The upper surface of the substrate is provided with Plural wire-bonding pads' The bottom surface of the substrate is provided with a plurality of flip-chip bonding pads (f 1 ip-chipb ο ndingpad) and a plurality of solder ball pads, the plurality of wire-bonding pads and the plurality of The flip-chip bonding pads are electrically connected to the corresponding solder ball bonding pads, wherein the address assignments of the plurality of wire bonding pads are the same as those of the flip-chip bonding pads; A wafer is provided on the upper surface of the substrate, and the first wafer has a plurality of wafer bonding pads electrically connected to corresponding wire bonding pads by a plurality of connecting lines; and a first wafer is provided in a flip-chip bonding manner. The lower surface of the substrate is used to join a plurality of tin boat connections of the first aa piece with a plurality of flip-chip bonding pads on the lower surface of the substrate, wherein the first wafer and the second wafer are phase Type. 2. According to the multi-chip package structure of the first patent application scope, the first and second chips are approximately the same size. 3. The multi-chip package structure according to item 1 of the scope of the patent application, which further includes a plurality of solder balls with a plurality of solder balls provided on the lower surface of the substrate. 4. A multi-chip package structure (mult ich ip module), which includes: ’, POO-008.ptc Page 13 457673 The upper surface of the substrate is provided with a pad on the lower surface of the substrate, and a plurality of one substrates have an upper surface and a lower surface, a plurality of wire-bonding pads, a plurality of flip-chip bonding pads (flip_chip b 〇nding solder ball pads; 'the first chip has a plurality of to the corresponding plurality of wires connected to a first chip provided on the top surface of the substrate; the wafer Xue is electrically connected to the bonding pad by a plurality of connecting wires; and one, The two wafers are arranged on the lower surface of the substrate in a flip-chip bonding manner, so that the plurality of tin-shao connections of the first aa chip are bonded to the plurality of flip-chip bonding pads on the lower surface of the substrate. 5. According to item 4 of the scope of patent application The multi-chip package structure, wherein the first and second chips are approximately the same size. 6. The multi-chip package structure according to item 4 of the patent application scope, further comprising a plurality of tin balls and a plurality of tins provided on a lower surface of the substrate. Ball bonding pad. F 7 'According to the multi-chip package structure of claim 4 in the patent application scope, at least one of the plurality of wire bonding pads is electrically connected to at least one of the plurality of flip-chip bonding pads. To the corresponding solder ball bonding pad. 8. The multi-chip package structure according to item 4 of the patent application scope, wherein the address assignment of the plurality of wire bonding pads is the same as the position of the plurality of flip-chip bonding pads. The address configuration is the same. 457 8 73 __Case No. 89101234_Year Month Date Amendment __ VI. Scope of Patent Application 9. A method for manufacturing a multi-chip package structure, which includes the following steps: Provide a substrate having an upper surface and a lower surface, the substrate The upper surface is provided with a plurality of wire-bond ing pads, and the lower surface of the substrate is provided with a plurality of flip-chip bonding pads and a plurality of solder ball pads; On the upper surface of the substrate, the first wafer has a plurality of wafer bonding pads electrically connected to a corresponding plurality of wire bonding pads by a plurality of connecting wires; and a second wafer is provided on the substrate in a flip-chip bonding manner. On the lower surface, a plurality of tin-lead connections on the second wafer are bonded to a plurality of flip-chip bonding pads on the lower surface of the substrate. 10. The method for manufacturing a multi-chip package structure according to item 9 of the scope of the patent application, wherein the first chip and the second chip are of the same type. 1 1. The method for manufacturing a multi-chip package structure according to item 9 of the patent application scope ′ further includes a plurality of solder balls with a plurality of solder balls provided on the lower surface of the substrate. 12. The method for manufacturing a multi-chip package structure according to item 9 of the scope of the patent application, wherein at least one of the plurality of wire bonding pads and at least one of the plurality of flip-chip bondings are electrically connected to correspond to each other. Kick pad. P00-008.ptc Page 15 457673 Case No. 89101234 Month / Date Amendment P00 * 008.ptc Page 16