TW200416988A - Package and manufacturing method thereof - Google Patents

Package and manufacturing method thereof Download PDF

Info

Publication number
TW200416988A
TW200416988A TW092103468A TW92103468A TW200416988A TW 200416988 A TW200416988 A TW 200416988A TW 092103468 A TW092103468 A TW 092103468A TW 92103468 A TW92103468 A TW 92103468A TW 200416988 A TW200416988 A TW 200416988A
Authority
TW
Taiwan
Prior art keywords
opening
wafer
substrate
metal
heat sink
Prior art date
Application number
TW092103468A
Other languages
English (en)
Other versions
TW582106B (en
Inventor
Yu-Fang Tsai
Chin-Hsien Lin
Tsung-Yueh Tsai
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092103468A priority Critical patent/TW582106B/zh
Priority to US10/776,490 priority patent/US7037750B2/en
Application granted granted Critical
Publication of TW582106B publication Critical patent/TW582106B/zh
Publication of TW200416988A publication Critical patent/TW200416988A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

200416988 五、發明說明(1) 【發明所屬之技術領域1 本發明是有關於一種去于 關於一種配置一金屬散熱片 製造方法。 裝件及製造方法,且特別是有 於晶片之底面下方的封裝件及 【先前技術】 由於電子產。口越來越輕薄短小,使 ;,以及,供:卜:電路連接的封褒件也同樣需要趨= 短小之設計:當然’封裝件的散熱設計也是重要的=專 请參广第1圖,其繪示乃傳統之具有金屬散熱片之球 陣列(heat slug ball grid array ,HSBGA)封筆件 剖面圖。在第i目中,封震件1〇〇包括基板1〇2、黏著劑午的 10 4a及104b、晶片106、數條銲線1〇8、金屬散熱片11()、 封膠112、數個銲墊1 14及數個錫球116。藉由黏晶動作 (die attaching ),使得晶片1〇6經由黏著劑1〇“固定於 基板102之正面上。再藉由打線動作(wire b〇nding ), 使得銲線1 0 8形成於晶片1 〇 6之正面及晶片1 〇 6外之基板1 0 4 的正面之間,以電性連接晶片1〇6及基板! 04。金屬散熱片 11 0之兩下垂端係藉由黏著劑1 〇 4 b固定於銲線1 〇 8外之基板 1 0 2的正面上,使得金屬散熱片11 〇之中間水平結構位於晶 片1 0 6之正面上方。此外,藉由灌膠動作 (encapsulating),使得封膠112覆蓋部分之金屬散熱片 11 0、晶片1 0 6、銲線1 0 8及部分之基板1 0 2之正面,並露出 金屬散熱片11 0之中間水平結構。另外,銲墊11 4係形成於
TW1026F(曰月光).ptd 第6頁 200416988
基板102的底面上,用以經由基板1〇2之内部線路與銲線 =8電丨生連接。藉由植球(bal 1 mount ing ),使得數個等 了,錫球1 U形成於銲墊11 4上,封裝件1 〇 〇將藉由錫球丨i 6 ”夕圍電路電性連接。其中,封裝件100之厚度為錫球116 之底端與封膠11 2之頂端之間的距離。 ^ ^ 1隨裝件1 〇 〇運作時,雖然晶片1 0 6所產生之熱量可以 、、二土、’政熱片11 〇逸散至外界中。但由於基板1 0 2導熱性 不佳’且其正面具有低導.熱性的防銲層(solder mask ) $致晶片1 〇 6所產生之部分熱量受到防銲層之阻 隔而累積於晶片1〇6及基板102之正面之間不易散逸,影塑 封裝件1GG之運作甚矩。此外,配置金屬散熱片於晶^ 106之正面上方的設計,一方面會增加封裝件1〇〇之厚度; 另一方面,基於銲線,設置的考量,金屬散熱片11〇之兩下 垂端必須固定於銲線108外之基板1〇2之正面上,將合增加 JJ102之正面的面積。因此,整個封裝件1〇。的“會 變大,生產成本將增加許多。 發明内容】 有鑑於此,本發明的目 造方法。其配置金屬散熱:片 得晶片所產生之熱量將經由 的金屬散熱片逸散至外界中 之問題’並提高封裝件之.散 片的厚度小於錫球的高度, 的就是在提供一種封裝件及製 ,晶片之底面下方的設計,使 晶片之底面下方之高熱傳導性 。可以省去基板之低熱傳導性 f效果…卜,由於金屬散熱 在不增加晶片之厚度的狀況
200416988 五、發明說明(3) 下,可以縮小封裝件之厚度 根據本發明的目的,提 屬散熱片、晶片、數條銲線 片係固定於基板之底面上並 片係固定於開口中之金屬散 板之正面上,用以與金屬散 形成於晶片之正面及基板之 及基板。封膠係覆蓋晶片、 面,此些錫球係形成於基嚷 其中’當晶片之底面積 係藉由一黏著劑固定於開口 開口之口壁之間的孔隙係以 晶片之底面積係等於開口之 定於開口中之金屬散熱片上 之大小’晶片係藉由一黏著 板的正面上,且介於晶片及 黏著劑填滿,使得晶片藉由 連接。 根據本發明的再一目的 法。在此方法中,首先,、提 之底面具有數個銲墊。接著 上,以封住開口之下口端及 晶片於開口中之金屬片上或 上。接著,形成數條銲線於 ’並減少生產成本。 出一種封裝件,包括基板、全 、封膠及數個錫球。金屬散埶 封住基板之開口的下口端。二、 熱片上或開口之上口端旁之爲 熱片導熱性連接。此些銲線: 正面之間,用以電性連接晶片、 此些銲線及部分之基板之: 之底面之數個銲墊上。 係小於該開口之大小時,晶片 中之金屬散熱片上,且晶^及 另一黏著劑或此封膠填滿;當 大小,晶片係藉由一黏著劑固 ’當晶片之底面積係大於開口 劑固定於開口之上口端旁之基 金屬散熱片之間的開口係以此 此黏著劑與金屬散熱片導熱性 ’提出一種封裝件之製造方 供一具有一開口之基板,基板 ’固定一金屬片於基板之底面 覆蓋此些銲墊。然後,固定一 開口之上口端旁之基板的正面 晶片之正面及基板之正面之
TW1026F(日月光).Ptd 第8頁 200416988 五、發明說明(4) 間,以電性連接晶片及基板。然後,形成封膠以覆蓋晶 片、此些銲線及部分之基板的正面。接著,去除部分之金 屬片,以形成一與晶片導熱性連接之金屬散熱片,並暴露 此些銲墊。然後,形成數個錫球於此些銲墊上,封裝件終 告完成。 其中,本方法使用一黏著劑,以固定底面積小於開口 之大小之晶片於開口中之金屬片上,且晶片及開口之口壁 之間的孔隙係以另一黏著劑或封膠填滿;本方法使用一黏 著劑,以固定底面積等於開口之大小之晶片於開口中之金 屬片上;本方法使用一黏著劑,以固定底面積大於開口之 大小之晶片於開口之上口端旁之基板的正面上,且介於晶 片及金屬片之間的開口係以此黏著劑填滿,使得晶片將籍 由此黏著劑與金屬散熱片導熱性連接。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 【實施方式】 本發明特別設計一封裝件及製造方法。其配置金屬散 熱片於晶片之底面下方的設計,使得晶片所產生之熱量將 經由晶片之底面下方之高熱傳導性的金屬散熱片逸散至外 界中。可以省去基板之低熱傳導性之防銲層的隔絕,並提 高封裝件之散熱效果。另外,由於金屬散熱片的厚度小於 錫球的高度,在不增加晶片之厚度的狀況下,可以縮小封
TW1026F(日月光).ptd 第9頁 200416988 五、發明說明(5) 裝件之厚度,並減少生產成本。 清參照第2 A〜2 E圖,其繪示乃依照本發明之實施例一 ,封裝件之製造方法的流程剖面圖。首先,在第2A圖中, 提供一具有一開口 203之基板202,並固定一金屬片210於 基板202之底面上,以封住開口203之下口端及覆蓋基板 102之底面的數個銲墊214。其中,金屬片21〇可以藉由黏 著劑2 04a固定於基板2 0 2之底面上。 接著’進行黏晶動作(die attaching),固定一晶 片206於開口203中之金屬片210上,如第2B圖所示。在第 2B圖中,晶片2 0 6之底面積係小於開口 2 0 3之大小,且晶片 206將藉由黏著劑2〇 4b固定於開口 203中之金屬片210上。 由於晶片2 0 6並未塞滿開口 2 0 3,使得位於開口 2 0 3中之晶 片2 0 6及開口 2 0 3之口壁之間具有空隙。當然,本發明亦可 以使用另一黏著劑填滿晶片2 0 6及開口 2 0 3之口壁之間的空 隙。偏若晶片之底面積係等於開口 2 0 3之大小時,晶片亦 可以藉由一黏著劑固定於開口 2 0 3中之金屬片2 1 0上,且晶 片剛好塞滿開口 2 0 3。 然後’依序進行打線,動作(wire bonding)及灌膠動 作(encapsulating),形成數條銲線2 0 8及封膠212,如 第2C圖所示。在第2C圖中,銲線2 0 8係形成於晶片2 0 6之正 面及基板2 0 2之正面之間,使得晶片20 6經由銲線2 0 8與基 板2 0 2電性連接。此外,錡膠212係覆蓋晶片2 0 6、銲線208 及部分之基板2 0 2之正面。由於晶片2 0 6之底面積係小於開 口 2 0 3之大小,封膠2 1 2可以填滿晶片2 0 6及開口 2 0 3之口壁
TW1026F(日月光).Ptd 第10頁 200416988
之間的空隙。 接著,去除部分之金屬片210,以形成一與晶片2〇6導 熱性連接之金屬散熱片210a,並暴露銲墊214,如第2D圖 所示。在第2D圖中,金屬散熱片2i〇a係位於晶片206之下 f,、而金屬散熱片210係以蝕刻部分之金屬片21〇之方式被 兀成’、且金屬散熱片210a之頂面積係大於開口 203之大 小。然後,進行植球(ba H mounting ),形成數個等高 之錫球216於銲墊214上,使得封裝件2〇〇終告完成,如第 2E圖所示。在第2E圖中,在金屬散熱片2i〇a之頂端與錫球 216之頂端位於同一水平面之情況下,金屬散熱片21〇&之 厚度係小於錫球216的高庠,且封裝件2〇〇之厚度為錫球 216之底端與封膠212之頂端之間的距離。
y 當封裝件2〇〇運作時,晶片2〇6所產生之熱量將經由晶 片206之底面下方之高熱傳導性的金屬散熱片21〇&直接逸 散至外界中,可以省去基板2〇2之低熱傳導性之防銲層的 隔絕,使得封裝件2 0 0之散熱效果較傳統之封裝件1〇〇之散 熱效果更佳。此夕卜,配置晶片2〇6於開口2〇3中及配置金屬 散熱片210a於晶片206之底面下方的設計,由 散埶
片21〇a之厚度小於絲216之高度。在不增力口晶片=之厚 度的狀況下,封襄件2 0 0之厚度將會比傳統之封裝件ι〇〇之 厚^還小,可以減少生產減本。另外,金屬散熱片以仏也 不會跟銲線m之設置空間產生衝突,可以減少基板2〇2之 正面的面積。因此,封裝件2 0 0之體積將縮小許多。 請參照第3A〜3E圖,其緣示乃依照本發明之實施例二
200416988 五、發明說明(7) 之封裝件之製造方法的流名剖面圖。首先,在第3A圖中, 提供一具有一開口 30 3之基板3〇2,並固定一金屬片31〇於 基板302之底面上,以封住開口 3〇3之下口端及覆蓋基板 302之底面之數個銲墊314。其中,金屬片31〇係藉由黏著 劑304a固定於基板302之底面上。 接著,進行黏晶動作,固定—晶片3 〇 6於開口 3 〇 3之上 口端旁之基板3 02的正面上,如第3B圖所示。在第⑽圖 中,晶片30 6之底面積係大於開口3〇3之大小,晶片3〇6係 猎由黏著劑304b固定於開口 303之上口端旁之基座3〇2的正 面上。此時,介於晶片3〇6及金屬片31〇之間的開口3 以黏著劑304b填滿。 308及然jVsil序線動作及灌膠動作,形成數條銲線 308及料312,如㈣圖5所示。在第%圖中鋒線3〇8係 形成於晶片30 6之正面及基板3〇2之正面之間使 3 0 6經由銲線3 0 8與基板3 〇 2電性i隶拉 曰曰 ”電f生連接。此外,封膠312係覆 盍日日片30 6、銲線3 0 8及部丨分之基板3〇2之正面。 :著,纟除部分之金屬片31〇,以形成一與晶片3〇6導 …一、接之金屬政熱片3i〇a,並暴露鮮塾314,如第⑽圖 ::川在S圖中,晶片3〇6係藉由黏著劑3_ …、 ^導…、性連接,而金屬散熱片31〇a係位於晶片3〇6 =I方。金屬散熱片3 1 〇8係以蝕刻部分之金屬片3 1 0之方 工完成y,且金屬散熱片31 0a之頂面積係大於開口 3 0 3之大 然後,進行黏球動作,形成數個等高之錫球316於銲 墊314上,使得封裝件3〇〇終告完成,如第3e圖所示。在第
200416988 五、發明說明(8) 3E圖中’在金屬散熱片31〇a之頂端與錫球316之頂端位於 同一水平面之情況下,金V戛散熱片3 1 〇a之厚度係小於錫球 316之高度。且封裝件300之厚度為錫球316之底端與封膠 3 1 2之頂端之間的距離。 / 當封裝件3 0 0運作時,晶片3 0 6所產生之熱量將經由晶 片306之底面下方之高熱傳導性的金屬散熱片31〇a逸散至 =界中,省去基板3 0 2之低熱傳導性之防銲層的隔絕,使 得封裝件3 0 0之散熱效果較傳統之封裝件丨〇 〇之散熱效果更 佳。其中,配置金屬散熱片31〇a於晶片3〇6之底面下方的 設計,由於金屬散熱片310a之厚度小於錫球316之高度。 在不增加晶片3 0 6之厚度的狀況下,封裝件3〇〇之厚度將會 ,傳統之封裝件1〇〇之厚度更小,可以減少生產成本。另 外,金屬散熱片31〇a也不嗆跟銲線3〇8之設置空間產生 突,可以減少基板302之正面r- 雜接脸π , 4夕的積。因此,封裝件30〇之 體積將縮小奸多。 ,熟悉U藝者亦可以明瞭本發明之技術並不侷限於 ΐ僂片i金屬散熱片之材質為銀、_或其他高 i t 4 t # I ,、中,基板之開口係以機械鑽孔、雷射 鑽孔或其他鑽孔方式完成。 Η 另外,本發明亦可以直接固定 ^ ^ ^ ^ = 而金屬散熱片剛好封住開口 明可以省略固定金屬片及法除^塾。如此〜來,本發 iL ^ as ^ , 除4分之金屬片等步驟。 本發明上述實施例所揭露之 置金屬散熱片於晶片之底湎下衣件及1以方法,其配 低自下方的設計,使得晶片所產生
200416988 五、發明說明(9) 之熱量將經由晶片之底面下方之高熱傳導性的金屬散熱片 逸散至外界中。可以省去基板之低熱傳導性之防銲層的隔 絕,並提高封裝件之散熱效果。此外,由於金屬散熱片的 厚度小於錫球的高度,在不增加晶片之厚度的狀況下,可 以縮小封裝件之厚度,並減少生產成本。另外,金屬散熱 片也不會跟銲線之作業空間產生衝突,可以減少基板之正 面的面積。因此,封裝件之體積將縮小許多。 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明,任何熟習此技藝者,在不脫離 本發明之精神和範圍内,當可作各種之更動與潤飾,因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準〇
TW1026F(日月光).ptd 第14頁 200416988 圖式簡單說明 【圖式簡單說明】 第1圖繪示乃傳統之具有金屬散熱片之球格陣列封裝 件的剖面圖。 第2 A〜2E圖繪示乃依照本發明之實施例一之封裝件之 製造方法的流程剖面圖。 第3 A〜3E圖繪示乃依照本發明之實施例二之封裝件之 製造方法的流程剖面圖。 圖式標號說明 1 0 0、2 0 0、3 0 0 :封裝件 102 > 2 0 2 ^ 3 0 2 :基板 104a 、 104b 、 204a 、 204b 、 304a 、 304b :黏著劑 106 、2 0 6 、3 0 6 :晶片 108 ^ 2 0 8 ^ 3 0 8 :銲線 110、210a、310a :金屬散熱片 112 ^212 ^ 312 ··封膠 114、214、314 :銲墊 116 > 216 ^ 316 :錫球 203 、 303 :開口 210、310 :金屬片
TW1026F(日月光).ptd 第15頁

Claims (1)

  1. 200416988 六、申請專利範圍 1 · 一種封裝件之製造方法,至少包括: 提供一具有一開口之基板,該基板之底面具有複數個 録塾; 固定一金屬片於該基板之底面上,以封住該開口之下 口端及覆蓋該些銲墊; 固定一晶片於該開口中之該金屬片上或該開口之上口 端旁之該基板的正面上; 形成複數條銲線於該晶片之正面及該基板之正面之 間’以電性連接該晶片及該基板; 形成一封膠以覆蓋該晶片、該些銲線及部分之該基板 的正面;以及 去除部分之該金屬片:,以形成/與該晶片導熱性連接 之金屬散熱片,並暴露該些銲墊。 2 ·如申請專利範圍第1項所述之方法,其中該方法於 該去除部分之該金屬片之步驟後又包括 形成複數個等高之錫球於該 3 ·如申請專利範圍第2項所述 該呰銲墊上。 所述之方法, ,其中該金屬散 熱片的厚度係小於各該錫球的高度 4 ·如申請專利範圍第1項所 該固定一金屬片於該基板之底面上 使用一黏著劑,以固定該金屬 5 ·如申請專利範圍第1項所述 方法,其中該方法於
    該固定一晶片於該開口中之該金屬 使用一黏著劑,以固定底面積 屬片於該基板之底面上。 i方法,其中該方法於 屬片上的步驟中又包括· 小於該開口之大小之該
    TW1026F(日月光).Ptd 第16頁 200416988 六、申請專利範圍 晶片於該開口中之該金屬片上,且該晶片及該開口之口壁 之間的孔隙係以另一黏著劑填滿。 6. 如申請專利範圍第1項所述之方法,其中該方法於 該固定一晶片於該開口中之該金屬片上的步驟中又包括: 使用一黏著劑,以固定底面積等於該開口之大小之該 晶片於該開口中之該金屬片上。 7. 如申請專利範圍第1項所述之方法,其中該方法於 該固定一晶片於該開口之上口端旁之該基板的正面上的步 驟中又包括: 使用一黏著劑,以固定底面積大於該開口之大小之該 晶片於該開口之上口端旁之該基板的正面上,且介於該晶 片及該金屬片之間的該開口係以該黏著劑填滿。 8. 如申請專利範圍第7項所述之方法,其中該晶片係 藉由另該黏著劑與該金屬散熱片導熱性連接。 9. 如申請專利範圍第1項所述之方法,其中該金屬片 之材質為銅。 β 10. 如申請專利範圍第9項所述之方法,其中該金屬 散熱片之材質為銅。 11. 如申請專利範圍第1項所述之方法,其中該方法 於該去除部分之該金屬片之步驟中又包括: 蝕刻該金屬片,以形成一與該晶片導熱性連接之金屬 散熱片。 12. —種封裝件,至少包括: 一基板,具有一開口;
    TW1026F(日月光).ptd 第17頁 200416988 六、申請專利範圍 一金屬 口之下口端 一晶片 口之上口端 熱性連接。 13·如 裝件又包括 複數條 之間,用以 一封膠 正面;以及 複數個 熱片覆蓋之 1 4.如 屬散熱片的 15. 如 屬散熱片係 1 6.如 片之底面積 劑固定於該 之口壁之間 17.如 片之底面積 固定於該開 散熱片,係固定於該基板之底面上並封住該開 :以及 ’係固定於該開口中之該金屬散熱片 旁之該基板之正面上,用以與該金屬 申請專利範圍、1 2項所述之封裝件, 銲線,係形成於該晶片之正面及該基 電性連接該晶片及該基板; ’係覆蓋該晶片、該些銲線及部分之 等高之錫 底面的複 申睛專利 厚度係小 申請專利 藉由一觀 申請專利 係小於該 開口中之 的孔隙係 申請專利 係等於該 口中之鈦 球,係形成 數個銲墊上 範圍第1 3項 於各該錫球 範圍第1 2項 著劑'固定於 範圍第1 2項 開口之大小 #金屬散熱 以另一黏著 範園第12項 開口之大小人 ..... 於該基板之未被 〇 所述之封裝件, 的高度。 所述之封裝件, 該基板之底面上 所述之封裝件, ,而該晶片係精 片上’且該晶片 劑填滿。 所述之封裝件, ,該晶片係错由 上0 上或該開 散熱片導 其中該封 板之正面 該基板的 該金屬散 其中該金 其中該金 其中該 曰曰 由一黏著 及該開口 其中該晶 一黏著劑
    200416988 六、申請專利範圍 18. 如申請專利範圍第1 2項所述之封裝件,其中該晶 片之底面積係大於該開口之大小,該晶片係藉由一黏著劑 固定於該開口之上口端旁之該基板的正面上,且介於該晶 片及該金屬散熱片之間的該開口係以該黏著劑填滿,使得 該晶片藉由該黏著劑與該金屬散熱片導熱性連接。 19. 如申請專利範圍第1 2項所述之封裝件,其中該金 屬散熱片之材質為銅。“
    TW1026F(日月光).ptd 第19頁
TW092103468A 2003-02-19 2003-02-19 Package and manufacturing method thereof TW582106B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW092103468A TW582106B (en) 2003-02-19 2003-02-19 Package and manufacturing method thereof
US10/776,490 US7037750B2 (en) 2003-02-19 2004-02-11 Method for manufacturing a package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092103468A TW582106B (en) 2003-02-19 2003-02-19 Package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW582106B TW582106B (en) 2004-04-01
TW200416988A true TW200416988A (en) 2004-09-01

Family

ID=32847879

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092103468A TW582106B (en) 2003-02-19 2003-02-19 Package and manufacturing method thereof

Country Status (2)

Country Link
US (1) US7037750B2 (zh)
TW (1) TW582106B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101584044A (zh) * 2006-12-12 2009-11-18 艾格瑞系统有限公司 集成电路封装体和用于在集成电路封装体中散热的方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3602968B2 (ja) * 1998-08-18 2004-12-15 沖電気工業株式会社 半導体装置およびその基板接続構造
US8125076B2 (en) * 2004-11-12 2012-02-28 Stats Chippac Ltd. Semiconductor package system with substrate heat sink
TWI305479B (en) * 2006-02-13 2009-01-11 Advanced Semiconductor Eng Method of fabricating substrate with embedded component therein
CN101944520B (zh) * 2010-09-26 2012-06-27 日月光半导体制造股份有限公司 半导体封装结构与半导体封装工艺
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3398721B2 (ja) * 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6781242B1 (en) * 2002-12-02 2004-08-24 Asat, Ltd. Thin ball grid array package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101584044A (zh) * 2006-12-12 2009-11-18 艾格瑞系统有限公司 集成电路封装体和用于在集成电路封装体中散热的方法

Also Published As

Publication number Publication date
TW582106B (en) 2004-04-01
US7037750B2 (en) 2006-05-02
US20040161879A1 (en) 2004-08-19

Similar Documents

Publication Publication Date Title
US6650006B2 (en) Semiconductor package with stacked chips
US6559525B2 (en) Semiconductor package having heat sink at the outer surface
TWI521653B (zh) Semiconductor device
TW200427029A (en) Thermally enhanced semiconductor package and fabrication method thereof
JP2004200316A (ja) 半導体装置
JP2008543055A (ja) バックサイド・ヒートスプレッダを用いる集積回路ダイ取り付け
TW200416988A (en) Package and manufacturing method thereof
TWI283049B (en) Cavity down ball grid array package
TW200416989A (en) Semiconductor device and method therefor
JPH04207061A (ja) 半導体装置
TW200529387A (en) Chip package structure
JPH05198701A (ja) 半導体装置用パッケージ
JPH10335577A (ja) 半導体装置及びその製造方法
JPH09199629A (ja) 半導体装置
TWI225296B (en) Chip assembly package
JP2003297994A5 (zh)
JP3628991B2 (ja) 半導体装置及びその製造方法
TWI230449B (en) High heat dissipation micro package of semiconductor chip
TW582102B (en) Package and manufacturing method thereof
TWM593659U (zh) 直接導出電子元件熱能的封裝結構
JP2008109056A (ja) 樹脂封止型半導体素子及びその製造方法
JP2962575B2 (ja) 半導体装置
TWI237361B (en) Chip package structure
JP2002124623A (ja) 半導体装置
JP2002064174A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent