200410376 Π) 玖、發明說明 【發明所屬之技術領域】 本發明是關於內藏具有當作電感器或變壓器功能的線 圈的多層基板（印刷基板）、疊層有多層基板（插入式選擇 指、電極配線層）的半導體晶片及其製造方法，更詳細爲 關於內藏像小型’大致可任意設定繞數以及形成方向，可 抑制對其他電路元件的雜訊的線圈的多層基板，疊層有該 多層基板但可抑制來自包含於該多層基板的線圈的雜訊的 半導體晶片及其製造方法。 【先前技術】 線圈自古以來在天線、馬達等廣泛的領域中被使用。 在電子機器的領域中，使用線圈的稱爲電感器（inductor) 的構造在各種零件、IC晶片內製造，廣泛被使用。僅使 電感器晶片化於表面安裝用係被稱爲晶片電感器（chip inductor)，例如也有在行動電話一台搭載20個以上的報 告。內藏電感器的零件也爲數眾多。例如組合電感器與電 容器的稱爲疊層LC濾波器（filter)的零件係以除去雜訊 (noise)等的目的，以高頻用途爲中心廣泛被使用。而且， 稱爲 VCO(Voltage Controlled Oscillator:壓控振盪器）的零 件也具有組合電感器與電容器的內部構造。VC0係可藉 由施加的電壓改變振盪頻率的振盪器，左右無線電路品質 的重要零件。對於假想近年來以爆發地普及的行動電話爲 首的在高頻區域的使用的機器係搭載有多數個這些零件。 -4- (2) (2)200410376 伴隨著電子機器的所謂的輕薄短小化的進行，對於這些零 件也被要求小型化。 再者，將所供給的電流的電壓變換成預定的電壓的變 壓器也在內部具有線圈構造。變壓器也常被安裝/形成於 基板上或半導體晶片上，因此，當然對於變壓器也要求小 型化。 這些零件類均被表面安裝。伴隨著近年的電氣機器的 輕薄短小化，安裝面積也逐漸變小。因此，將這些被動零 件形成於基板內部的嚐試也多數被實施。 針對電感器內藏基板，在與基板平面平行的面藉由習 知的微影（photolithography)法形成螺旋圖案（spiral pattern)的方法最普通。而且，朝半導體晶片上形成線圈 自古以來便被檢討。現在，關於此事被實用化係如上述， 在與半導體基板平行的面內形成導體的螺旋圖案。但是， 對於此方法仍有許多問題點。取晶片電感器的形狀變遷爲 例來說明。 晶片電感器係使用繞線（winding)在習知以來便已被廣 泛使用。最近以陶瓷製的晶片零件爲中心有種種提案。例 如如日本特開平1 1 -2043 3 6號公報所揭示的，已知在綠薄 片（green sheet)以導電性漿糊（paste)印刷電路，藉由在疊 層後燒成’形成線圈。但是此方法爲單層線圈，無法確保 充分的繞數’無法得到充分的電感。對於確保充分的繞數 需要增加疊層數，由成本、大小的觀點有界限。 而且’已知若在高頻區域使用電感器，則無法忽視浮 -5- (3) (3)200410376 置電容（floating capacity)。浮置電容係藉由感應線圈 (inductor coil)在相同平面相對的構造，藉由當作電容器 (C ο n d e n s e r )作用而產生。在與基板平面平行的面形成螺旋 圖案，疊層此螺旋圖案作爲多層線圈的情形也產生此問 題。此即在線圈間產生的浮置電容對電極爲並聯。 若在高頻區域使用此構造的電感器，則雜訊的問題也 發生。即感應磁場在電感器的軸方向即對基板平面垂直的 方向產生。此點爲帶給晶片下部的訊號線不良影響。爲所 謂的雜訊。此問題如近年來的行動電話機在高的頻率區域 使用時顯著。此機構例如在日經BP公司發行的日經電子 200 1年、3-26號（No.792)的 173〜174頁詳細說明。即在 與基板平行的面內形成導體的螺旋圖案的情形，若變動電 流藉由機器的使用而在該處流動的話，變動磁場會沿著與 該螺旋圖案直交的方向產生。據此，感應電流會流過與此 變動磁場交鏈（interlink)的基板平面或半導體晶片的配線 或其他電路元件，使雜訊產生。因此，習知即使在電晶體 等的電路元件的正上形成電感器的情形，爲了減少雜訊的 影響’常常採取特意夾幾層，在該層上形成電感器的迂迴 手法。但是在這種手法中，設計上會受到非常多的限制， 成爲問題。 而且’在日本特開平1 1 -2 1 4622號公報提出在與基板 平面垂直的方向形成螺線管（solenoid coil)的方法。在此 方法中因形成螺線管，故磁場被封閉於線圈內，由雜訊的 觀點無問題。但是，因所形成的螺線管必然地具有非常多 -6- (4) (4)200410376 的體積，故由設計自由度的點有問題。 鑒於以上的問題點，在日本特開平1 0-2849 1 9號公報 與本發明一樣提出在與基板平面垂直的方向形成線圈的方 法。藉由此方法，因前述浮置電容對電極爲串聯故此問題 小。在此構造中，基板安裝時的雜訊問題也大致被解決。 但是，此方法也與前述的方法一樣，由於是單層，故無法 期待得到充分的電感。而且，藉由在與基板平面平行的方 向延長，可確保繞數，但因貫通孔或導電圖案的製造精度 的界限，故一定以上的高密度化很困難，因此，在實用的 大小上無法得到充分的電感。而且，增加疊層數會招致不 良率的上升，結果成本升高。 在日本特開昭62- 1 8 97 07號公報也可看到與本發明類 似的電感器的提案。而且，在日本特開平4-23 7 1 06號公 報也針對電感器以及變壓器提案。但是，在這些提案中關 於具體的製造法雖然有對基板垂直方向的螺旋狀電路部分 藉由貫通孔（through hole)或介層孔（via hole)形成的既 述，惟無更具體的說明。而且，因無這種線圈的關於如後 述的高頻區域中的優良性質的見識，故這種線圈除了製造 的困難度外，在利用面上實用化也被阻礙。 在日本特開平3 -3 4407號公報提出線圈自身的構造使 用與本發明類似的多層線圈的晶片電感器。但是，此提案 也是關於安裝於印刷配線基板表面的晶片電感器，具有因 晶片而造成的問題，並且製造方法也有問題。即製造方法 因在一平面形成螺旋構造，疊層此螺旋構造，故需以印刷 -7- (5) (5)200410376 形成微細的螺旋構造。近年來檢討被進行的晶片電感器爲 〇· 3mm X 0.3mm X 0.6mm的非常小型.，在其剖面藉由印刷 形成螺旋構造會發生因污點造成的短路發生等的問題，故 非常困難。 以上，針對習知的晶片電感器中的構造/製造方法等 的問題點來記述。這些問題點在形成電感器於基板內部的 情形也完全相同會變成問題。而且，若以高密度安裝晶片 電感器的話，彼此的串擾（crosstalk)爲問題，而且對於安 裝晶片於基板上的情形，會引起晶片的一側隨著時間脫落 成爲直立狀態的所謂的墓石（tombstone)現象，成爲基板全 體無可用的問題。 另一方面，變壓器也使用線圈。變壓器的典型構造在 夾著磁性體的兩側配置繞數不同的兩條線圈。藉由作成這 種構造，可損失少地進行變壓。但是，在習知的線圈的製 造方法中，因線圈作成方向爲與各線圈剖面垂直的方向， 故在兩條線圈之間配設磁性體層在製程上困難，需以另外 作成的線圈與磁性體爲一個零件再度組裝，不可能形成於 基板內部。 而且，在與基板平行的方向隔著絕緣層形成兩片電感 器，形成變壓器的方法也被提出。取代絕緣體使用磁性體 的例子也已知。但是，利用此方法的情形，在限定的面積 中電感器的繞數有限制，無法發揮充分的功能。爲了發揮 功能需要作成大的面積，惟由小型化的觀點有問題。若作 成感應線圈爲多層的話，在限定的面積中可確保線圈的繞 -8~ (6) 200410376 數，但此時若不配置磁性體於線圈的伸長方向的話就無法 獲得充分的效果，且在其方向配置磁性體很困難。200410376 Π) 发明. Description of the invention [Technical field to which the invention belongs] The present invention relates to a multilayer substrate (printed substrate) having a coil having a function as an inductor or a transformer, and a multilayer substrate (plug-in selection finger, electrode) Wiring layer) semiconductor wafer and its manufacturing method are more detailed about a multilayer substrate with a built-in image, such as a small-sized coil, which can be arbitrarily set with a winding number and a formation direction, and can suppress noise to other circuit elements. A substrate, but a semiconductor wafer capable of suppressing noise from a coil included in the multilayer substrate, and a manufacturing method thereof. [Prior Art] Coils have been used in a wide range of fields such as antennas and motors since ancient times. In the field of electronic equipment, a structure called an inductor using a coil is manufactured in various parts and IC chips and is widely used. Chips used for surface-mounting inductors only are called chip inductors. For example, there are reports that 20 or more are mounted on a mobile phone. There are also many parts with built-in inductors. For example, a component called a laminated LC filter that combines an inductor and a capacitor is widely used mainly for high-frequency applications in order to remove noise and the like. In addition, a component called a VCO (Voltage Controlled Oscillator) also has an internal structure that combines an inductor and a capacitor. VC0 is an oscillator that can change the oscillation frequency by the applied voltage, which is an important part that affects the quality of wireless circuits. Many of these devices are mounted on devices that are supposed to be used in the high-frequency region, including mobile phones that have become popular in recent years. -4- (2) (2) 200410376 With the so-called thinness and miniaturization of electronic devices, these parts are also required to be miniaturized. Furthermore, a transformer that converts a voltage of a supplied current into a predetermined voltage also has a coil structure inside. Transformers are also often mounted / formed on substrates or semiconductor wafers. Therefore, miniaturization of transformers is also required. These parts are all surface mounted. With the reduction in weight and weight of electrical equipment in recent years, the mounting area has gradually become smaller. Therefore, many attempts have been made to form these passive components inside the substrate. For a substrate built in an inductor, a method of forming a spiral pattern on a surface parallel to the plane of the substrate by a conventional photolithography method is the most common. Furthermore, the formation of coils on semiconductor wafers has been reviewed since ancient times. Now, as described above, a practical matter is to form a spiral pattern of a conductor in a plane parallel to a semiconductor substrate. However, there are still many problems with this method. Take the shape change of the chip inductor as an example to explain. Chip inductors have been widely used since they have been used for winding. Recently, various proposals have been made mainly on ceramic wafer parts. For example, as disclosed in Japanese Patent Application Laid-Open No. 1 1-2043 36, it is known that a circuit is printed on a green sheet with a conductive paste, and the coil is formed by firing after lamination. However, this method is a single-layer coil, and a sufficient number of windings cannot be ensured, and a sufficient inductance cannot be obtained. In order to ensure a sufficient number of windings, it is necessary to increase the number of laminations, and there are limits in terms of cost and size. Moreover, it is known that if an inductor is used in a high frequency region, the floating capacity cannot be ignored. (3) (3) 200410376 Floating capacity. The floating capacitor is produced by the structure of the inductor coils facing each other on the same plane, and is generated by acting as a capacitor (C ο n d e n s er). This problem also occurs when a spiral pattern is formed on a plane parallel to the plane of the substrate, and this spiral pattern is laminated as a multilayer coil. This means that the floating capacitor counter electrodes generated between the coils are connected in parallel. If an inductor with this structure is used in a high frequency region, noise problems also occur. That is, the induced magnetic field is generated in the axial direction of the inductor, that is, the direction perpendicular to the plane of the substrate. This point is an adverse effect on the signal line on the lower part of the chip. Is the so-called noise. This problem is noticeable when a mobile phone is used in a high frequency region in recent years. This organization is explained in detail on pages 173 to 174 of Nikkei Electronics 2001, No. 3-26 (No. 792) issued by Nikkei BP, for example. That is, in the case where a spiral pattern of a conductor is formed in a plane parallel to the substrate, if a fluctuating current flows there through the use of a device, a fluctuating magnetic field is generated in a direction orthogonal to the spiral pattern. As a result, an induced current flows through the plane of the substrate interlinked with the changing magnetic field, the wiring of the semiconductor wafer, or other circuit elements, and noise is generated. Therefore, even in the case where an inductor is formed directly above a circuit element such as a transistor, in order to reduce the influence of noise ', a circuitous method of sandwiching several layers to form an inductor on this layer is often used. However, in this method, the design is subject to a lot of restrictions and becomes a problem. Furthermore, Japanese Patent Application Laid-Open No. 1 1-2 2622 proposes a method of forming a solenoid coil in a direction perpendicular to the plane of the substrate. In this method, since the solenoid is formed, the magnetic field is enclosed in the coil, and there is no problem from the viewpoint of noise. However, since the formed solenoid inevitably has a very large volume of -6- (4) (4) 200410376, there is a problem from the point of design freedom. In view of the above problems, Japanese Patent Application Laid-Open No. 10-2849 1 9 proposes a method of forming a coil in a direction perpendicular to the substrate plane, as in the present invention. With this method, since the counter electrode of the floating capacitor is connected in series, this problem is small. In this configuration, the noise problem at the time of mounting the substrate is also largely resolved. However, this method is also the same as the above-mentioned method. Since it is a single layer, a sufficient inductance cannot be expected. In addition, the number of windings can be ensured by extending in a direction parallel to the plane of the substrate. However, due to the limitation of the manufacturing accuracy of the through holes or conductive patterns, it is difficult to achieve a higher density than a certain level, so it cannot be obtained in practical sizes. Full inductance. Furthermore, increasing the number of laminations leads to an increase in the defective rate, and as a result, the cost increases. A proposal of an inductor similar to the present invention can be found in Japanese Patent Application Laid-Open No. 62- 1 8 97 07. Furthermore, Japanese Patent Publication No. 4-23 7 1 06 also proposes inductors and transformers. However, although specific manufacturing methods in these proposals have been described in which a spiral circuit portion in a vertical direction to a substrate is formed by a through hole or a via hole, there is no more specific description. In addition, since there is no knowledge of the excellent properties of such coils in the high-frequency region described later, in addition to the difficulty of manufacturing the coils, the practical use of the coils has been hindered. Japanese Unexamined Patent Publication No. 3-33 4407 proposes a chip inductor using a multilayer coil similar to the present invention in the structure of the coil itself. However, this proposal is also related to a chip inductor mounted on the surface of a printed wiring board, which has problems caused by the chip and a manufacturing method. That is, the manufacturing method forms a spiral structure on one plane and stacks the spiral structure, so it is necessary to form a fine spiral structure by printing -7- (5) (5) 200410376. In recent years, the chip inductors that have been reviewed are very small, 0.3 mm X 0.3 mm X 0.6 mm. It is very difficult to form a spiral structure in the cross section by printing, which causes problems such as short circuits due to stains. The problems of the structure and manufacturing method in the conventional chip inductor have been described above. These problems also become the same when the inductor is formed inside the substrate. In addition, if chip inductors are mounted at high density, crosstalk between them is a problem, and in the case where a chip is mounted on a substrate, one side of the chip may fall over time into a so-called tombstone. ) Phenomenon, which becomes a problem that the entire substrate is unavailable. On the other hand, transformers also use coils. A typical structure of a transformer includes two coils having different numbers of windings on both sides of a magnetic body. By constructing such a structure, the transformer can be transformed with less loss. However, in the conventional coil manufacturing method, since the coil formation direction is a direction perpendicular to the cross section of each coil, it is difficult to arrange the magnetic layer between the two coils, and it is necessary to use a separately prepared coil and magnetic body. It is impossible to form a component inside the substrate once it is assembled again. Furthermore, a method of forming a transformer by forming two inductors with an insulating layer in a direction parallel to the substrate is also proposed. Examples of using a magnetic body instead of an insulator are also known. However, in the case of this method, the number of windings of the inductor is limited in a limited area, and it cannot perform sufficient functions. In order to function, a large area is required, but there is a problem from the viewpoint of miniaturization. If the induction coil is made of multiple layers, the number of coils can be ensured in a limited area of -8 ~ (6) 200410376. However, if a magnetic body is not arranged in the coil's elongation direction, a sufficient effect cannot be obtained. It is difficult to arrange the magnetic body in its direction.
本發明是以提供安裝/形成於配線基板，或對內藏的 其他零件或電路的雜訊等的不良影響少，即使高密度地內 藏也能減少相互的串擾的小型且可以同一製程任意地變更 繞數（層數），可得到大的自感（self inductance)或互感 (mutual inductance)的內藏形成方向也可任意變更的線圈 或變壓器的多層配線基板及其製造方法爲課題。而且，也 以提供一體地疊層有這種線圈或變壓器的半導體晶片及其 製造方法爲課題。 【發明內容】 如果依照本發明，上述課題可藉由如以下的任一個手 段達成。申請專利範圍第1項所述之發明其特徵包含：與 多層基板一體形成的線圈，包含平行於該多層基板的繞線 部分以及垂直於該多層基板的繞線部分，被支持於該多層 基板內的線圈；以及支持該線圈，構成該多層基板的絕緣 部分的至少一部分，以及由疊層的絕緣層構成的絕緣體， 其中該線圈的單位繞線在由與接鄰的其他單位繞線相同方 向§的情形’分別具有在互相相反的方向旋轉的螺旋狀的 案’以及該線圈的互相接鄰的單位繞線的組在該螺旋狀 的圖案的前端彼此或末端彼此中交互連接。 $目靑專利範圍第2項所述之發明其特徵包含：與多層 基板一體形成的線圈，包含平行於該多層基板的繞線部分 -9 - (7) (7)200410376 以及垂直於該多層基板的繞線部分，被支持於該多層基板 內的線圈；由貫通該線圈內部的柱狀的磁性體構成的芯構 造；以及支持該線圈，構成該多層基板的絕緣部分的至少 一部分，以及由疊層的絕緣層構成的絕緣體。 申請專利範圍第3項所述之發明係除了申請專利範圍 第2項所述之發明的特徵外尙有：該線圈的單位繞線在由 與接鄰的其他單位繞線相同方向看的情形，分別具有在互 相相反的方向旋轉的螺旋狀的圖案，以及該線圈的互相接 鄰的單位繞線的組在該螺旋狀的圖案的前端彼此或末端彼 此中交互連接。 申請專利範圍第4項所述之發明係除了申請專利範圍 第1項至第3項中任一項所述之發明的特徵外尙有：該線 圈其平行於該多層基板的繞線部分係以疊層的導電層的一 部分形成，垂直於該多層基板的繞線部分係以連接隔著該 絕緣層接鄰的該導電層間的凸塊（b u m p)形成。 申請專利範圍第5項所述之發明係除了申請專利範圍 第1項至第3項中任一項所述之發明的特徵外尙有：該線 圈是藉由增層（build-up)工法，使平行於該多層基板的繞 線部分以疊層的導電層的一部分形成，垂直於該多層基板 的繞線部分以連接通過該絕緣層接鄰的該導電層間的介層 或貫通孔形成。 申請專利範圍第6項所述之發明係除了申請專利範圍 第1項至第5項中任一項所述之發明的特徵外尙有：更具 有在與該多層基板平行的面內具有電路面的平面線圈。 -10- (8) (8)200410376 申請專利範圍第7項所述之發明係除了申請專利範圍 第1項至第6項中任一項所述之發明的特徵外尙有：具有 複數條該線圈，該複數條線圈是令藉由至少任一個線圈所 產生的磁力線的變動，被其他線圈感應的電壓最少而配 置。 申請專利範圍第8項所述之發明係除了申請專利範圍 第1項至第6項中任一項所述之發明的特徵外尙有：具有 複數條該線圈，該複數條線圈是令至少任一個線圈所產生 的磁力線貫通其他線圈的主方向與該其他線圈的中心軸直 交而配置。 申請專利範圍第9項所述之發明其特徵包含：與多層 基板一體形成的線圈，包含平行於該多層基板的繞線部分 以及垂直於該多層基板的繞線部分的複數條線圈；在與該 多層基板平行的面內具有電路面的平面線圈；以及支持該 線圈以及該平面線圈，構成該多層基板的絕緣部分的至少 一部分，以及由疊層的絕緣層構成的絕緣體。 申請專利範圍第1 〇項所述之發明其特徵包含：與多層 基板一體形成的複數條線圈，包含平行於該多層基板的繞 線部分以及垂直於該多層基板的繞線部分，被該多層基板 內支持，令藉由至少任一個線圈所產生的磁力線的變動， 被其他線圈感應的電壓最少而配置的複數條線圈；以及支 持該複數條線圈，構成該多層基板的絕緣部分的至少一部 分，以及由疊層的絕緣層構成的絕緣體。 申請專利範圍第1 1項所述之發明其特徵包含：與多層 -11- (9) (9)200410376 基板一體形成的複數條線圈，包含平行於該多層基板的繞 線部分以及垂直於該多層基板的繞線部分，被該多層基板 內支持，令至少任一個線圈所產生的磁力線貫通其他線圈 的主方向與該其他線圈的中心軸直交而配置的複數條線 圈；以及支持該複數條線圈，構成該多層基板的絕緣部分 的至少一部分，以及由疊層的絕緣層構成的絕緣體。 申請專利範圍第1 2項所述之發明係除了申請專利範 圍第8項至第1 1項中任一項所述之發明的特徵外尙有：該 線圈係平行於該多層基板的繞線部分以疊層的導電層的一 部分形成’垂直於該多層基板的繞線部分以連接隔著該絕 緣層接鄰的該導電層間的凸塊形成。 申請專利範圍第1 3項所述之發明係除了申請專利範 圍第8項至第1 1項中任一項所述之發明的特徵外尙有：該 線圈是藉由增層工法’使平行於該多層基板的繞線部分以 疊層的導電層的一部分形成’垂直於該多層基板的繞線音β 分以連接通過該絕緣層接鄰的該導電層間的介層或貫通？L 形成。 申請專利範圍第1 4項所述之發明係除了申請專利範 圍第1項至第1 3項中任一項所述之發明的特徵外尙有：該 線圈的至少任一個爲電感器。 申請專利範圍第1 5項所述之發明係除了申請專利範 圍第1項至第1 3項中任一項所述之發明的特徵外尙有：該 線圈的至少任一個爲由相互磁氣結合的兩個以上的線圈構 成的變壓器。 -12- (10) (10)200410376 申請專利範圍第1 6項所述之發明其特徵爲申請專利 範圍第1項至第1 5項中任一項所述之線圈內藏多層基板 係疊層於外面。 申請專利範圍第1 7項所述之發明其特徵包含：形成構 成多層基板的一個絕緣層的步驟；形成平行於該多層基板 的線圈的繞線部分的至少一部分於該多層基板內的絕緣層 上的步驟；形成以絕緣層間電氣連接平行於該多層基板的 線圈的該繞線部分的至少一部分彼此的垂直連接部，據 此’形成垂直於該多層基板的線圈的繞線部分的至少一部 分的步驟；以及到藉由平行於該多層基板的線圈的繞線部 分與垂直於該多層基板的線圈的繞線部分，形成有被支持 於該多層基板內的預定的線圈爲止，對到此爲止形成的多 層基板的部分，適宜反覆形成絕緣層的該步驟、形成平行 於該多層基板的線圈的繞線部分的至少一部分的該步驟以 及形成垂直於該多層基板的線圈的繞線部分的至少一部分 的該步驟的至少任一個的步驟，其中該預定的線圈的單位 繞線在由與接鄰的其他單位繞線相同方向看的情形，分別 具有在互相相反的方向旋轉的螺旋狀的圖案，以及該預定 的線圈的互相接鄰的單位繞線的組在該螺旋狀的圖案的前 端彼此或末端彼此中交互連接。 申請專利範圍第1 8項所述之發明其特徵包含：形成構 成多層基板的一個絕緣層的步驟；形成平行於該多層基板 的線圈的繞線部分的至少一部分於該多層基板內的絕緣層 上的步驟；形成以絕緣層間電氣連接平行於該多層基板的 -13 - (11) (11)200410376 線圈的該繞線部分的至少一部分彼此的垂直連接部，據 此，形成垂直於該多層基板的線圈的繞線部分的至少一部 分的步驟；用以配置由柱狀的磁性體構成的芯構造於該線 圈的內部而形成的步驟；以及到藉由平行於該多層基板的 線圈的繞線部分與垂直於該多層基板的線圈的繞線部分， 形成有被支持於該多層基板內的預定的線圈爲止，對到此 爲止形成的多層基板的部分，適宜反覆形成絕緣層的該步 驟、形成平行於該多層基板的線圈的繞線部分的至少一部 分的該步驟以及形成垂直於該多層基板的線圈的繞線部分 的至少一部分的該步驟的至少任一個的步驟。 申請專利範圍第1 9項所述之發明其特徵包含：形成構 成多層基板的一個絕緣層的步驟；形成平行於該多層基板 的線圈的繞線部分的至少一部分於該多層基板內的絕緣層 上的步驟；形成以絕緣層間電氣連接平行於該多層基板的 該繞線部分的至少一部分彼此的垂直連接部，據此，形成 垂直於該多層基板的線圈的繞線部分的至少一部分的步 驟；以及到藉由平行於該多層基板的線圈的繞線部分與垂 直於該多層基板的線圈的繞線部分，形成有被支持於該多 層基板內的預定的線圈爲止，對到此爲止形成的多層基板 的部分，適宜反覆形成絕緣層的該步驟、形成平行於該多 層基板的線圈的繞線部分的至少一部分的該步驟以及形成 垂直於該多層基板的線圈的繞線部分的至少一部分的該步 驟的至少任一個的步驟，其中該線圈是令藉由至少任一個 線圈所產生的磁力線的變動，被其他線圈感應的電壓最少 -14 - (12) (12)200410376 而配置的複數條線圈。 申請專利範圍第20項所述之發明其特徵包含：形成構 成多層基板的一個絕緣層的步驟；形成平行於該多層基板 的線圈的繞線部分的至少一部分於該多層基板內的絕緣層 上的步驟；形成以絕緣層間電氣連接平行於該多層基板的 該繞線部分的至少一部分彼此的垂直連接部’據此’形成 垂直於該多層基板的線圈的繞線部分的至少一部分的步 驟；以及到藉由平行於該多層基板的線圈的繞線部分與垂 直於該多層基板的線圈的繞線部分，形成有被支持於該多 層基板內的預定的線圈爲止，對到此爲止形成的多層基板 的部分，適宜反覆形成絕緣層的該步驟、形成平行於該多 層基板的線圈的繞線部分的至少一部分的該步驟以及形成 垂直於該多層基板的線圈的繞線部分的至少一部分的該步 驟的至少任一個的步驟，其中該線圈是令至少任一個線圈 所產生的磁力線貫通其他線圈的主方向與該其他線圈的中 心軸直交而配置的複數條線圈。 申請專利範圍第2 1項所述之發明係除了申請專利範 圍第1 9項或第2 0項中任一項所述之發明的特徵外尙有： 更具有用以配置由柱狀的磁性體構成的芯構造於該線圈內 的至少任一個的內部而形成的步驟。 申請專利範圍第22項所述之發明係除了申請專利範 圍第1 7項至第21項中任一項所述之發明的特徵外尙有： 該線圈內藏多層基板係疊層於半導體晶圓的外面，更具有 將疊層有該線圈內藏多層基板的該半導體晶圓切割成半導 -15 - (13) (13)200410376 體晶片單位的步驟。 申請專利範圍第2 3項所述之發明係除了申請專利範 圍第1 7項至第2 1項中任一項所述之發明的特徵外尙有： 該線圈內藏多層基板係疊層於半導體晶片的外面。 【實施方式】 以下針對本發明的實施形態，一邊參照圖面一邊說 明。先說明與本發明的第一實施形態有關的線圈內藏多層 基板1的構成。第1圖是顯示線圈內藏多層基板1的槪略 構成的斜視圖。線圈內藏多層基板1是由線圈1 a以及多 層基板1 c構成。線圈〗a是在多層基板中的複數層絕緣層 以及導電層的每一層的形成步驟中當作導電層的一部分而 形成的給予電感的構成要素。線圈1 a係中心軸平行於多 層基板’包含平行於多層基板的繞線部分以及垂直於該多 層基板的繞線部分（在本說明書中稱像中心軸平行於多層 基板的線圈爲[縱型線圈])。線圈1 a較佳爲剖面形狀爲四 角Jb、圓形等的導線重複的圖案的單位繞線以電氣地串聯 連續連接的形態構成（以下稱這種線圈爲[多層線圈])。在 本說明書中的線圈1 a及其單位繞線的形態也廣泛地包含 給予電感用的任何形態。線圈1 a的單位繞線在由與接鄰 的其他單位繞線相同方向看的情形，分別具有在互相相反 的方向旋轉的螺旋狀的圖案，以及互相接鄰的單位繞線彼 此在該螺旋狀的圖案的前端彼此或末端彼此中互相連接。 藉由如此構成線圈〗a，可使單位繞線內的繞數比1還 •16- (14) (14)200410376 大，且因若電流流過線圈1 a的話所有的單位繞線會產生 相同方向的磁場，故可增大電感。較佳爲平行於線圈la 的多層基板的繞線部分以疊層的導電層的一部分形成，垂 直於多層基板的繞線部分以連接隔著絕緣層接鄰的該導電 層間的凸塊、介層或貫通孔等形成。據此，藉由形成線圈 la，利用增層（build-up)工法等的公知的多層基板製造技 術’在多層基板的製程中可同時形成線圈1 a於多層基板 內。多層基板1 c係疊層絕緣層而構成的基板。此外，在 實際的多層基板1 c的形成步驟中，絕緣層與導電層係交 互疊層。而且，導電層的部分成爲前述線圈1 a的一部 分，其他的絕緣層的部分成爲多層基板1 c。 第1 1圖是顯示藉由線圈內藏多層基板1的疊層的製 程的斜視槪念圖。如此，線圈內藏多層基板1係在絕緣層 1 c的每一層形成線圈1 a的各部分，其次藉由疊層一體化 來製造。在線圈內藏多層基板1於平行延長於多層基板的 方向或於多層基板的上側或下側形成有包含其他線圈等的 電路也可以。 其次，說明與本發明的第二實施形態有關的線圈內藏 多層基板2的構成。第2圖（a)是顯示線圈內藏多層基板2 的槪略構成的斜視圖。線圈內藏多層基板2具有像配置磁 性體2d於線圏2a內部的構造。線圈內藏多層基板2的各 構成要素係在線圈內藏多層基板1中與由1到2變更符號 的數字部分的構成要素。據此，因在線圈2a的內部配置 有磁性體2 d，故有可增大線圈2 a的電感的優點。此外， -17- (15) (15)200410376 像是在與本發明的第一實施形態有關的線圈內藏多層基板 1的線圈1 a的內部配置磁性體的構成也可以。第2圖（b) 以及（c)係其他線圈的構造例。在這些例子中，僅在平行 或直交於線圈的中心軸的方向的繞線部分構成有線圈。 其次，說明與本發明的第三實施形態有關的線圈內藏 多層基板3的構成。第3圖（a)以及（b)是顯示線圈內藏多 層基板3的槪略構成的斜視圖。在第3圖（a)所示的實施 形態中，線圈內藏多層基板3係具有將中心軸平行於多層 基板的線圈3 a，及中心軸與產生磁場的中心方向直交， 且在平行於多層基板的面內具有電路面的平面線圈3 b配 置於多層基板3c上的構造。在第3圖（b)所示的實施形態 中，線圏3 d爲多層線圈。如此，藉由配置兩個線圈可防 止一側的線圈所產生的磁場的影響及於他側的線圈，可減 少起因於這種影響的雜訊等。 其次，說明與本發明的第四實施形態有關的線圈內藏 多層基板4的構成。第4圖（a)以及（b)是顯示線圈內藏多 層基板4的槪略構成的斜視圖。在第4圖（a)所示的實施 形態中，線圈內藏多層基板4係具有將中心軸平行於多層 基板的線圈4a與中心軸平行於多層基板的線圈4b，令藉 由任一個線圈所產生的磁力線的變動，被其他線圈感應的 電壓最少（例如令任一個線圈所產生的磁力線貫通其他線 圈的主方向與該其他線圈的中心軸直交）配置於多層基板 3 c內的構造。此外，磁力線貫通線圈的主方向是指例如 平均貫通線圈的磁力線的向量的向量的方向。在第4圖（a) -18- (16) (16)200410376 所示的實施形態中，線圈4 d以及4 d爲多層線圈。第3 4 圖是用以說明與本發明有關的線圈內藏多層基板內的最小 化由互感造成的雜訊用的複數個線圈的較佳配置的槪念 圖。第3 4圖是顯不在弟一線圈所產生的磁力線變動時， 使被第二線圈感應的電壓最少的配置。其中，令第一線圈 所產生的磁力線貫通第二線圈的主方向與該第二線圈的中 心軸直交而配置。據此，藉由配置第二線圈，可防止一側 的線圈所產生的磁場的影響及於他側的線圈，可減少起因 於這種影響的雜訊等。而且’在多層基板內可積集形成許 多線圈，提高設計的自由度。 再者其次，說明與本發明的第五實施形態有關的線圈 內藏多層基板5的構成。第5圖（a)以及（b)是顯示線圈內 藏多層基板5的槪略構成的斜視圖。在第5圖（a)所示的 實施形態中係對第4圖（a)所示的實施形態，附加在平行 於多層基板的面內具有電路面的平面線圈5 c的構成。在 第5圖（b)所示的實施形態中，對第4圖（b)所示的實施形 態，附加在平行於多層基板的面內具有電路面的平面線圈 5 c的構成。據此，藉由配置三個線圈，可防止任一個線 圈所產生的磁場的影響及於其他側線圈，可減少起因於這 種影響的雜訊等。而且，在多層基板內可積集形成更多的 線圈，更提高設計的自由度。 再者其次，說明與本發明的第六實施形態有關的線圈 內藏多層基板6的構成。第6圖是顯示線圈內藏多層基板 6的槪略構成的斜視圖。線圈內藏多層基板6係具有將中 -19 - (17) (17)200410376 心軸平行於多層基板的線圈6 a，及與中心軸在同一直線 上，且中心軸平行於多層基板的線圈6b配置於多層基板 6 c內的構造。據此，藉由配置兩個線圈，可在兩個線圈 之間產生互感，可形成變壓器。此情形，藉由沿著兩方的 線圈的中心軸配置磁性體，可更提高變壓器的效率。 再者其次，說明與本發明的第七實施形態有關的線圈 內藏多層基板7的構成。第7圖（a)以及（b)是顯示線圈內 藏多層基板7的槪略構成的斜視圖。線圈內藏多層基板7 係具有將中心軸平行於多層基板的線圈7a，及位於與中 心軸爲平行的位置，且接鄰的線圈7b配置於多層基板7c 內，更配置磁氣地有效結合兩方的線圈用的磁性體7d或 7e的構造。據此，藉由配置兩個線圈，可在兩個線圈之 間產生互感，可形成變壓器。磁性體如第7圖（a)所示的 磁性體7 d配置於兩方的線圈之間也可以，對於更有效地 磁氣結合，如如第7圖（b)所示的磁性體7e，成爲具有貫 通兩方的線圈的中心軸的部分的環狀形態而配置也可以。 再者其次，說明與本發明的第八實施形態有關的線圈 內藏多層基板8的構成。第8圖是顯示線圈內藏多層基板 8的槪略構成的斜視圖。線圈內藏多層基板8是由中心軸 平行於多層基板的線圈8a以及多層基板8c構成。線圈 1 a的單位繞線係螺旋構造的導體在平行於多層基板的面 內排列兩個的構造。藉由這種構造，在限定的體積中可形 成非常密的線圈，可增大電感。而且，第9圖是顯示與本 發明的第九實施形態有關的線圈內藏多層基板9的槪略構 -20- (18) (18)200410376 成的斜視圖。在線圈內藏多層基板9中，於單位繞線的兩 個螺旋構造的導體之間配置磁性體9d，可得到更大的電 感。 現在說明線圈內藏多層基板1〜9的動作。線圈內藏多 層基板1〜9當作將印刷基板、構成單塊（m〇n〇lithic)IC等 的半導體晶片黏著（mount)於其上的插入式選擇指 (interposer)或半導體晶片的電極配線層使用較佳。而且， 線圈內藏多層基板1〜9可將其他電路元件形成於其內部或 黏著於外部，可構成附加以這種其他電路元件與線圈內藏 多層基板1〜9構成的電路的功能於半導體晶片自身的功能 的半導體。線圈內藏多層基板1〜9藉由線圈的伸長方向的 調節，可簡便且大致任意地設定繞數，可自由地使自感以 及互感變化。而且，藉由全體地或部分地調節單位繞線與 磁場交鏈的面積，也能柔軟地設定電感。再者，藉由在線 圈的內部配置磁性體也能增大電感。據此，線圈內藏多層 基板1〜9在通過線圈的兩側的端子被由外部的電路施加電 壓石，當作電感器或變壓器的功能。 其次，針對本發明的實施例來說明。組合在第3 5圖 到第3 7圖顯示構造的縱型線圈與在第3 8圖到第40圖顯 示構造的平面線圈，使線圈接近而配置時，藉由三次元電 磁場模擬器（Sonnet)解析朝互相未直接連接的接鄰線圈的 端子的訊號洩漏與配置的關係，比較種種情形。上述圖中 的長度的數値單位爲mm。導體間的介電常數以2.0實施 模擬。 -21 - (19) (19)200410376 首先，進行線圈單體的解析。第41圖是表示由模擬 求得的縱型線圈的訊號通過特性圖。第42圖是表示由模 擬求得的平面線圈的訊號通過特性圖。其次，針對接鄰線 圈彼此而配置的情形進行解析。藉由模擬求得在第4 3圖 顯示構造的線圈間距離〇. 1 mni的平行配置的縱型線圈（第 一實施例）的訊號通過特性圖顯示於第44圖。第44圖中 的S2 1、S3 1以及S41是分別顯示由第43圖中的端子T1 到端子T2、端子T1到端子T3以及端子T1到端子T4的 訊號傳達的程度（在以下的圖中也一樣）。藉由模擬求得在 第45圖顯示構造的線圈間距離0.1mm的平行配置的平面 線圈（第二實施例）的訊號通過特性圖顯示於第46圖。藉 由模擬求得在第4 7圖顯示構造的接鄰配置的縱型線圈與 平面線圈（第三實施例）的訊號通過特性圖顯示於第4 8 圖。藉由模擬求得在第 49圖顯示構造的線圈間距離 0.2mm的平行配置的縱型線圈（第一實施例）的訊號通過特 性圖顯示於第5 0圖。藉由模擬求得在第5 1圖顯示構造的 線圈間距離0.2mm的平行配置的平面線圈（第二實施例）的 訊號通過特性圖顯示於第52圖。由這些結果得知在第47 圖所示的第三實施例中，相較於第4 3圖所示的第一實施 例以及第4 5圖所示的第二實施例，S 3 1、S 4 1所示的訊號 洩漏約低5 dB左右。因此，由訊號洩漏的觀點得知第47 圖所示的第三實施例比第4 3圖所示的第一實施例以及第 4 5圖所示的第二實施例還能藉由線圈配置改善訊號洩 漏。而且，訊號洩漏的改善程度比令線圈間距離爲〇.2mm -22- (20) (20)200410376 的第49圖所示的第一實施例以及第5 1圖所示的第二實施 例還優良可分別由第5 0圖以及第5 2圖的訊號通過特性得 知。此外，得知積極地利用訊號洩漏使訊號間的結合當作 變壓器的功能等的情形，第一實施例以及第二實施例比第 三實施例還適合。 其次，針對本發明的線圈內藏多層基板1到9的製造 方法，與習知技術比較的優點一起說明。若使用本發明的 方法可簡便地得到所希望的繞數的線圈。在習知的與基板 平面平行的面形成螺旋圖案的方法中，對於增加繞數會發 生增加疊層數的必要，成爲大的成本上升，但是藉由本發 明的方法’疊層數依照原樣僅延伸於線圈的伸長方向即 可，成本上升少。 以下’本發明的線圈內藏多層基板的製造方法，爲了 簡略化說明以線圈部分爲中心具體地說明。首先，作成第 1 1圖的內層（第二層）部分的情形若適用兩面貼銅疊層板的 開孔、藉由電鍍的貫通孔的導電化、利用負（subtractive) 法的表面的圖案形成（p a 11 e r n i n g)等被熟知的方法的話 佳。其次，對此第二層，若在兩面作成絕緣層更進一步作 成導電層，進行圖案形成以及電氣連接的話，可得到第1 圖。針對幾個方法舉例說明。 對於利用所謂的增層法的情形如第1 5圖所示，在上 述第二層（由1 a、1 b構成）的基板形成絕緣層。絕緣層可 使用一體化玻璃環氧系或芳香族聚醯胺（aramid)樹脂系等 的預浸樹脂玻璃布（pre-preg)、液狀或薄膜狀的熱可塑或 -23 - (21) (21)200410376 熱硬化性的樹脂組成物或一般稱爲附樹脂的銅箔的銅箔與 絕緣樹脂層的物質等。 絕緣層的形成例如可如以下進行。如第1 5圖（a)所 示，在上述第二層的基板兩面配置未被圖案化的銅箔j i 或如第1 5圖（b)所示附樹脂的銅箔1 2，如第1 6圖所示， $曰由豐層沖壓（p r e s s )法總括地使迨些材料疊層/硬化，作 成一體化絕緣層與導電層。（或者如第17圖所示在上述第 一層基板上，以網版（screen)印刷、簾塗佈（curtain coating)、噴塗（spray coat)等的公知慣用的方法塗佈，藉 由ϋν、電子線、熱等使其硬化。或者在上述基板上以軋 輥（roll)、疊層（laminate)等的方法貼著，以預定的方法使 其硬化，得到絕緣層1 3。） 接著形成介層。在以上述方法得到的基板的預定位置 使用鑽孔、雷射等形成介層1 4。第1 8圖（a)是針對絕緣層 以及導電層使用預浸樹脂玻璃布1 0與銅箔1 1的情形，同 樣地第1 8圖（b)是針對附樹脂的銅箔1 2的情形，第1 8圖 (c)是針對使用液狀或薄膜狀的熱可塑或熱硬化性的樹脂 組成物1 5的情形來表示。對於使用預浸樹脂玻璃布類或 附樹脂的銅箔形成絕緣層以及導電層的情形，在使用被盲 介層（blind via)的形成廣泛使用的碳酸氣體雷射時，依照 需要預先以蝕刻除去預定位置的導電體，實施所謂的罩幕 (mask)加工也可以。 使用預浸樹脂玻璃布類或附樹脂的銅箔形成絕緣層以 及導電層的情形，例如如第1 9圖（a)所示對介層印刷配合 -24 - (22) (22)200410376 銀、銅等的導電性粉末的導電性漿糊1 6 ’以分配等的方 法埋入，以預定的方法使其硬化。或者如第1 9圖（b)所 示，藉由對通常的貫通孔電鍍即在介層內賦予電鍍催化劑 後進行無電解電鍍，接著藉由進行電解電鍍的方法形成電 鍍層1 7的方法，也能達成電氣的連接。使用液狀或薄膜 狀的組成物形成絕緣層的情形如第1 9圖（c)所示’例如沖 壓銅箔1 1在絕緣層的外側形成導電層，罩幕加工預定的 位置後，藉由導電性漿糊1 6或電鍍層1 7導電化連接肓介 層。此情形先進行盲介層的導電化也可以。而且’如第 19圖（d)所示，對形成有絕緣層、肓介層的基板賦予催化 劑，進行無電解電鍍處理，接著藉由依照需要進行電解電 鍍處理，也能總括地進行導電層1 8的形成與盲介層的導 電化。此情形肓介層的導電化也能藉由導電性漿糊來進 行。 或者藉由以下的方法，也能總括地進行絕緣層與導電 層、電氣連接。即如第20圖所不’在第二層基板電路上 的預定場所使用導電性漿糊等形成前端尖銳的導電性凸塊 19後藉由配置預浸樹脂玻璃布1〇與銅箔11(第20圖（a)) 或薄膜狀的絕緣體20與銅箔11(第20圖（b))或附樹脂的 銅箔12後進行沖壓加工（第20圖（〇)，使導電性凸塊19 貫通絕緣層，實現與導電層的連接。 以這些增層法疊層的情形，肓介層藉由導電性漿糊或 電鍍等，藉由以導電體塡充，使線圈的剖面均爲導電體較 佳。但是，即使爲如習知的貫通孔僅外周部被導電化的構 -25- (23) (23)200410376 造，使用低雜訊、機械的強度、設計的自由度等的本發明 的方法形成的線圈的特徵也無任何變化，可無問題地依頻 帶（frequency band)使用。 而且，堆積肓介層形成線圈部分的情形，在像使用貫 通孔電鍍的一般的增法法中，所謂的堆疊介層（stacked via)(Wa on via)構造其形成非常困難，其結果線圈的一邊 不在直線上而是成爲階梯狀。但是，即使成爲此構造，使 用本發明的方法形成的線圈的特徵也無任何變化，可無問 題地依頻帶使用。 此外，使用藉由電鍍連接的貫通孔，使用上述液狀或 薄膜狀的絕緣材料的情形，或對於更在藉由一旦增層法形 成的有盲介層的絕緣層上疊層的情形，藉由埋孔用的墨水 或電鍍處理塡埋貫通孔或盲介層，以平滑化表面也可以。 除了增層法以外，也能藉由以下的方法總括地疊層。 絕緣層係針對使用玻璃環氧系的預浸樹脂玻璃布的四層構 造的線圈的情形來說明。即如第2 1圖所示，使用雷射等 對貼銅單面玻璃環氧基板2 1的基材側的預定位置進行開 孔加工。接著，以銅箔1 1爲電極進行電鍍，以電鍍1 7塡 充產生的孔。然後，以連續電鍍法作成低熔點的金屬凸塊 22。 銅箔1 1如第22圖所示，蝕刻加工程預定的圖案。在 凸塊側薄薄地塗佈與在絕緣層使用的同樣的絕緣體組成物 2 3，使其半硬化。由此單面基板製造的第2 2圖的組成物 係成爲最外層即第一層以及第四層。 • 26- (24) 200410376 接著，如第2 3圖所示，定位第二層基板與！ 最外層，藉由沖壓加工使其半硬化的組成物由凸 去，與形成層間的絕緣層同時，凸塊部與內層的 氣連接，以製造具有四層構造的線圈。藉由應用 更多層化也能容易進行。 此時，絕緣層的厚度可依照用途任意地設定 緣可靠度的觀點在實用上10微米到3 00微米左 導體的厚度也與絕緣層一樣，可依照用途任意地 在實用上5微米到200微米左右較佳。 藉由在線圈中心部配設以磁性體爲主成分的 使本發明的線圈可得到更大的電感。磁性體芯構 可藉由在該當部分塗佈含有鐵、肥粒鐵等的漿糊 以上係針對線圈部分的製作過程來說明，惟 與線圈形成同時，作爲目的的基板，必要的其他 線也依照需要形成於形成有線圈的各層。因此， 了配合其他電路、配線的形成而由幾個方法之中 擇。 此外’在同一平面作成所有的線圈的情形， 的一部分的貫通孔即與基板平面垂直的方向的導 精度成爲問題，惟藉由錯開各線圈的平面而形成 問題。顯示此情形的一例的線圈的螺旋狀電路剖 示於第一 10圖。藉由以第一電路面以及第二電 一面的圖案製造線圈，可解決上述問題點。 而且’不形成螺旋構造於同一平面，如在第 有2 2圖的 塊部被除 導電體電 此方法， ，但由絕 右較佳。 設定，但 芯構造， 造的形成 來進行。 如記述， 電路或配 各製程爲 適宜地選 形成線圈 體的形成 可解決此 面圖係顯 路面的每 11圖所 -27 - (25) (25)200410376 顯示的一例，因獨立形成各層，在疊層時形成有螺旋構 造，故蝕刻不良等成爲原因的短路等的不良在本質上不會 發生。而且，各螺旋構造之中其一半左右係以所謂的貫通 孔形成。貫通孔因其剖面爲圓形，故無角可抑制電阻値於 低値。再者，在疊層一體化後在螺旋狀電路面中發生層的 剝離的去疊層（delamination)不會發生。 再者，已知若在高頻區域使用電感器的話，則浮置電 容無法忽視。浮置電容係藉由感應線圈在相同平面相對的 構造，藉由當作電容器作用而產生。在本發明的線圈內藏 多層基板中，感應線圈的浮置電容因可視爲對電極面串 聯，故此問題少。再者，如前述的第1 〇圖，錯開線圈面 的構造不使用特別的技術可簡便地製造。若使用此構造， 則本質上可減小浮置電容。據此，可高高地保持電感器的 自共振頻率。 藉由應用上述的製程，可製造各種實施形態的線圈內 藏多層基板。例如，如第3圖所示的線圈內藏多層基板3 如第2圖所示若疊層絕緣層與導電層的話佳。而且，第6 圖所示的線圈內藏多層基板6如第1 3圖所示若疊層絕緣 層與導電層的話佳。而且，如第7圖（a)所示的線圈內_ 多層基板7如第1 4圖所示若疊層絕緣層與導電層與磁性 體的話佳。 再者，針對如上述任一個線圈內藏多層基板也能形成 於構成單塊1C等的半導體晶片上。藉由作成這種構成， 可在半導體以高的積集度組裝線圈等的元件。現在，以γ -28 - (26) 200410376 顯示在半導體基板上形成中心軸與基板平面平行的線 過程。典型例爲顯示形成電晶體，更在以鎢等形成電 的矽晶圓的上層所謂的電極配線層’形成第1圖的線 藏多層基板1的例子。藉由應用此方法，可任意地設 數、歹！J (層）數、形成方向等。此外’半導體不限於矽 使用鎵砷等的任意的公知的半導體材料。 首先，如第2 4圖所示，在形成電晶體、電極部 晶圓上形成最下層的絕緣層25。使用CVD等的氣相 成氧化矽膜，或在旋塗（spin coat)後藉由後烘烤（post 可形成近年來被注目的聚醯亞胺（Polyimide)、苯并環 (benzocyclobutene)等的有機原料。接著如第25圖所 在必要的位置使用各種雷射進行孔2 6的開孔。孔2 6 行半導體晶圓2 4的特定的位置或與下層的電極部的 連接的位置。接著如第26圖所示，形成導電性圖案 使用一般所使用的鋁的濺鍍（sputtering)或以CVD等 相法或電鍍法等的濕式法形成銅的層。接著進行曝光 刻以形成圖案。此情形，在形成先形成圖案的光阻層 進行導電化也可以。在此製程中，以第2 5圖所示的 開孔的孔26也被導電化，第一層與第二層的電氣連 進行。此外，在曝光製程之前通常藉由組合物理的硏 稱爲 CMP(Chemical Mechanical Polishing :化學機械 ί 法的化學的硏磨與物理的硏磨的方法等，平坦化表面 其次，如第2 7圖所示形成第二絕緣層2 8。接著 第2 8圖所示再度開孔，藉由導體圖案形成以形成第 圈的 極部 圈內 定圈 ，可 的矽 法形 bake) 丁烯 示， 爲進 電氣 27 ° 的氣 、蝕 後才 製程 接被 磨或 汗磨） 〇 ，如 二導 -29- (27) (27)200410376 電性圖案29。接著如第29圖所示藉由前述的方法形成第 三絕緣層3 0，實施開孔、導電化、圖案形成，形成第三 導電性圖案3 1，並且取得第二層、第三層的導通。 以後重複此操作，如第3 0圖所示形成第四絕緣層3 2 後’進行開孔、導電化、圖案形成，形成第四導電性圖案 3 3 °若應用此操作的話，圈數的增減、歹U (層）數的增減、 具有不同的伸長方向的複數個線圈的形成等可簡便地進 行。 在絕緣層形成、開孔後形成導電層，並且進行線間的 電氣連接時，如第3 1圖所示若以導電體3 5塡充孔部分 (介層）34的話，如在第32圖顯示線圈剖面，可形成一般 稱爲堆疊介層的構造即在塡充的介層上再有介層的構造， 可作成線圈的邊成直線。 而且，一般進行的方法即在不以導電體塡充介層的方 法中，不形成堆疊介層構造。此時，所製造的線圈如第 3 3圖所示的介層連接部具有成階梯狀的剖面。即使成爲 這種構造，特別是對於在高頻區域使用的情形實用上也無 問題。 在矽晶圓2 4上的多層基板內形成所希望的線圈後， 將包含該矽晶圓24與線圈的多層基板切割成半導體晶 片。 此外，在矽晶圓2 4疊層內藏線圈的多層基板前，也 能將矽晶圓24切割成晶片單位。此情形在預先被切割的 半導體晶片的外面，與上述製程一樣，疊層內藏線圈的多 -30- (28) (28)200410376 層基板也可以。 如以上所說明，本發明的線圈內藏多層基板具有除了 由習知推測的此種線圈的性質，即小型且以同一製程可任 意地變更繞數（層數），可給予大的電感之特長外，不僅內 藏形成方向也可任意變更的線圈，線圈不給予其他零件或 電路雜訊產生等的不良影響，而且，線圈彼此的串擾可避 免之習知所未見的優良的特長。而且，作爲線圈在具有相 同的構造的晶片電感器看見到的接近安裝線圈的情形所產 生的所謂的墓石（tombstone)現象也不發生。由本發明的多 層基板的這種特長，可以說回顧習知本很少的這種線圈已 經初次到達實用化的階段。 【圖式簡單說明】 第1圖是顯示與本發明的第一實施形態有關的線圈內 藏多層基板1的槪略構成的斜視圖（在以下的圖面中也顯 示有基板中的線圈部分，其他的電路、配線等省略）。 第2圖（a)是顯示與本發明的第二實施形態有關的線 圈內藏多層基板2的槪略構成的斜視圖，第2圖（b)以及 第2圖（c)是顯示其他線圈的構造例圖。 第3圖是顯示與本發明的第三實施形態有關的線圈內 藏多層基板3的槪略構成的斜視圖。 第4圖是顯示與本發明的第四實施形態有關的線圈內 藏多層基板4的槪略構成的斜視圖。 第5圖是顯示與本發明的第五實施形態有關的線圈內 -31- (29) (29)200410376 藏多層基板5的槪略構成的斜視圖。 第6圖是顯示與本發明的第六實施形態有關的線圈內 藏多層基板6的槪略構成的斜視圖。 第7圖是顯示與本發明的第七實施形態有關的線圈內 藏多層基板7的槪略構成的斜視圖。 第8圖是顯示與本發明的第八實施形態有關的線圈內 藏多層基板8的槪略構成的斜視圖。 第9圖是顯示與本發明的第九實施形態有關的線圈內 藏多層基板9的槪略構成的斜視圖。 第1 〇圖是表示線圈的相互接鄰的單位繞線的導體配 置的剖面圖。 第1 1圖是用以說明與本發明的第一實施形態有關的 線圈內藏多層基板1的製造過程的斜視圖。 第1 2圖是用以說明與本發明的第三實施形態有關的 線圈內藏多層基板3的製造過程的斜視圖。 第1 3圖是用以說明與本發明的第六實施形態有關的 線圈內藏多層基板6的製造過程的斜視圖。 第1 4圖是用以說明與本發明的第七實施形態有關的 線圈內藏多層基板7的製造過程的斜視圖。 第1 5圖是與本發明的第一實施形態有關的線圈內藏 多層基板1的製造初階段的斜視圖。 第1 6圖是顯示與本發明的第一實施形態有關的線圈 內藏多層基板1的製法的一例的斜視圖。 第17圖是顯示與本發明的第一實施形態有關的線圈 -32 - (30) (30)200410376 內藏多層基板1的製法的一例的斜視圖。 第1 8圖是顯示與本發明的第一實施形態有關的線圈 內藏多層基板1的製法的一例的斜視圖。 第1 9圖是顯示與本發明的第一實施形態有關的線圈 內藏多層基板1的製法的一例的斜視圖。 第2 0圖是顯示與本發明的第一實施形態有關的線圈 內藏多層基板1的製法的一例的斜視圖。 第2 1圖是顯示與本發明的第一實施形態有關的線圈 內藏多層基板1的製法的一例的斜視圖。 第22圖是顯示與本發明的第一實施形態有關的線圈 內藏多層基板1的製法的一例的斜視圖。 第2 3圖是顯示與本發明的第一實施形態有關的線圈 內藏多層基板1的製法的一*例的斜視圖。 第24圖是到與本發明的第一實施形態有關的線圈內 藏多層基板1的1C晶片上的製造初階段的剖面圖。 第2 5圖是介層形成的說明用的剖面圖。 第2 6圖是電路形成用的導電圖案形成的說明用的剖 面圖。 第27圖是第二絕緣層形成的說明用的剖面圖。 第2 8圖是第二導電圖案形成的說明用的剖面圖。 第29圖是第三層形成的說明用的剖面圖。 第3 0圖是與形成於IC晶片上的本發明的第一實施形 態有關的線圈內藏多層基板1的剖面圖。 第3 1圖是介層的剖面圖。 -33 - (31) (31)200410376 第3 2圖是顯示與形成於i C晶片上的本發明的第一實 施形態有關的線圈內藏多層基板1的一例的剖面圖。 第3 3圖是顯示與形成於I c晶片上的本發明的第一實 施形態有關的線圈內藏多層基板1的一例的剖面圖。 第3 4圖是用以說明與本發明有關的線圈內藏多層基 板內的最小化由互感造成的雜訊用的複數個線圈的較佳配 置的槪念圖。 第3 5圖是縱型線圈的斜視圖。 第3 6圖是縱型線圈的俯視圖。 第3 7圖是縱型線圈的A-A箭視橫剖面圖。 第3 8圖是平面線圈的斜視圖。 第3 9圖是平面線圈的俯視圖。 第4 0圖是平面線圈的B - B箭視橫剖面圖。 第4 1圖是表示縱型線圈的訊號通過特性圖。 第42圖是表示平面線圈的訊號通過特性圖。 第4 3圖是與第一實施例有關的平行配置的縱型線圈 (線圈間距離〇 . 1 mm)的俯視圖。 第44圖是表示與第一實施例有關的平行配置的縱型 線圈（線圈間距離0.1 mm)的訊號通過特性圖。 第4 5圖是與第二實施例有關的平行配置的平面線圈 (線圈間距離0.1 mm)的斜視圖。 第4 6圖是表示與第二實施例有關的平行配置的平面 線圈（線圈間距離0.1 mm)的訊號通過特性圖。 第4 7圖是與第三實施例有關的線圈內藏多層基板的 "34 * (32) (32)200410376 接鄰配置的縱型線圈與平面線圈的斜視圖。 第4 8圖是表示與第三實施例有關的線圈內藏多層基 板的接鄰配置的縱型線圈與平面線圈的訊號通過特性圖。 第4 9圖是與第一實施例有關的平行配置的縱型線圈 (線圈間距離〇 . 2 m m)的斜視圖。 第5 0圖是表示與第一實施例有關的平行配置的縱型 線圈（線圈間距離0.2 mm)的訊號通過特性圖。 第5 1圖是與第二實施例有關的平行配置的平面線圈 (線圈間距離〇.2mm)的斜視圖。 第52圖是表示與第二實施例有關的平行配置的平面 線圈（線圈間距離〇.2mm)的訊號通過特性圖。 [符號說明] 1〜9 :線圈內藏多層基板 la〜6a、4b、4d、6b、7a、7b、8a:線圈 lc〜4c、7c、8c: 多層基板 2 d、7 d、7 e、9 ch 磁性體 3b > 5c:平面線圈 8 c :多層基板 1 〇 :預浸樹脂玻璃布 1 1 :銅箔 1 2 :附樹脂的銅箔 1 3 :絕緣層 14:介層 -35- (33) (33)200410376 1 5 :樹脂組成物 1 6 :導電性漿糊 1 7 :電鍍層 1 8 :導電層 1 9 :導電性凸塊 20·.絕緣體 2 1 :玻璃環氧基板 22:金屬凸塊 2 3 :絕緣體組成物 2 4 :砂晶圓 2 5 :絕緣層 2 6 :孔 27:導電性圖案 2 8 :第二絕緣層 2 9 :第二導電性圖案 3 0 :第三絕緣層 3 1 :第三導電性圖案 3 2 :第四絕緣層 3 3 :第四導電性圖案 3 4 :介層 3 5 :導電體 T1〜T4:端子The present invention is to provide a small size that can be mounted on / formed on a wiring board or has no adverse effects on built-in other parts or circuits, and can reduce mutual crosstalk even if built in at high density. Changing the number of windings (number of layers) to obtain a multilayer wiring board of a coil or a transformer with a large self inductance or mutual inductance can be arbitrarily changed in the formation direction, and a manufacturing method thereof. It is also an object of the present invention to provide a semiconductor wafer in which such a coil or a transformer is integrally laminated, and a method for manufacturing the same. [Summary of the Invention] According to the present invention, the above problems can be achieved by any of the following means. The invention described in item 1 of the patent application scope includes a coil integrally formed with the multilayer substrate, including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate, and is supported in the multilayer substrate. A coil supporting the coil, at least a part of an insulating portion constituting the multilayer substrate, and an insulator composed of a laminated insulating layer, wherein the unit winding of the coil is in the same direction as the winding of other units adjacent thereto§ In the case of 'each having a spiral case which rotates in mutually opposite directions' and a group of adjacent unit windings of the coil are alternately connected to each other at the front end or the end of the spiral pattern. The feature of the invention described in item 2 of the patent scope includes: a coil formed integrally with the multilayer substrate, including a winding portion parallel to the multilayer substrate-9-(7) (7) 200410376 and perpendicular to the multilayer substrate The winding portion is supported by the coil in the multilayer substrate; a core structure composed of a columnar magnetic body penetrating the inside of the coil; and the coil is supported by at least a part of the insulation portion of the multilayer substrate, and by a stack Insulators consisting of layers of insulation. The invention described in item 3 of the scope of patent application is in addition to the features of the invention described in item 2 of the scope of patent application. The unit winding of the coil is viewed in the same direction as the winding of other units adjacent to it. Groups each having a spiral pattern rotating in mutually opposite directions, and groups of adjacent unit windings of the coil are alternately connected to each other at the front end or the end of the spiral pattern. The invention described in item 4 of the scope of the patent application is in addition to the features of the invention described in any one of the scope of claims 1 to 3 in the patent scope: The coil has a winding portion parallel to the multilayer substrate. A part of the laminated conductive layer is formed, and a winding portion perpendicular to the multilayer substrate is formed by bumps connecting the conductive layers adjacent to each other across the insulating layer. The invention described in item 5 of the scope of patent application is in addition to the features of the invention described in any one of scopes 1 to 3 of the patent application. The coil has a build-up method, The winding portion parallel to the multilayer substrate is formed by a part of the laminated conductive layer, and the winding portion perpendicular to the multilayer substrate is formed by a via layer or a through-hole connected between the conductive layers adjacent to each other through the insulating layer. The invention described in item 6 of the scope of patent application is in addition to the features of the invention described in any one of scopes 1 to 5 of the scope of patent application. In addition, it has a circuit surface in a plane parallel to the multilayer substrate. Plane coil. -10- (8) (8) 200410376 The invention described in item 7 of the scope of patent application is in addition to the features of the invention described in any one of the scope of patent applications 1 to 6: A coil, and the plurality of coils are arranged so that a change in a magnetic field line generated by at least one coil is minimized by a voltage induced by another coil. The invention described in item 8 of the scope of the patent application is in addition to the features of the invention described in any one of the scope of patent applications 1 to 6: it has a plurality of coils, and the plurality of coils are The main directions of the magnetic fluxes generated by one coil penetrate the other coils and are arranged orthogonal to the central axis of the other coils. The invention described in item 9 of the scope of the patent application includes a coil integrally formed with the multilayer substrate, including a plurality of coils parallel to the winding portion of the multilayer substrate and a plurality of coils perpendicular to the winding portion of the multilayer substrate; A planar coil having a circuit surface in a plane parallel to the multilayer substrate; and supporting the coil and the planar coil, constituting at least a part of an insulating portion of the multilayer substrate, and an insulator composed of a laminated insulating layer. The invention described in claim 10 of the patent application scope includes a plurality of coils integrally formed with the multilayer substrate, including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. Internal support so that a plurality of coils configured by a change in magnetic field lines generated by at least one of the coils to minimize the voltage induced by other coils; and supporting the plurality of coils to form at least a part of an insulating portion of the multilayer substrate, and An insulator composed of a laminated insulating layer. The invention described in item 11 of the scope of the patent application includes a plurality of coils integrally formed with the multilayer -11- (9) (9) 200410376 substrate, including a winding portion parallel to the multilayer substrate and perpendicular to the multilayer The winding portion of the substrate is supported by the multilayer substrate, and a plurality of coils arranged so that magnetic lines of force generated by at least any one coil pass through the main direction of the other coil and intersect the central axis of the other coil at right angles; and support the plurality of coils, At least a part of an insulating portion constituting the multilayer substrate, and an insulator composed of a laminated insulating layer. In addition to the features of the invention described in any one of the eighth to eleventh patent applications, the invention described in item 12 of the scope of patent application includes: the coil is parallel to the winding portion of the multilayer substrate A portion of the laminated conductive layer is formed perpendicular to the winding portion of the multilayer substrate to form a bump connecting the conductive layers adjacent to each other across the insulating layer. The invention described in item 13 of the scope of the patent application is in addition to the features of the invention described in any one of the scope of patent application items 8 to 11: The coil is made parallel to the The winding portion of the multilayer substrate is formed with a part of the laminated conductive layer to be perpendicular to the winding sound β of the multilayer substrate to connect the interlayer or the penetration between the conductive layers adjacent through the insulating layer? L is formed. The invention described in item 14 of the scope of patent application is in addition to the features of the invention described in any one of the scope of patent applications 1 to 13 in that at least any one of the coils is an inductor. The invention described in item 15 of the scope of patent application is in addition to the features of the invention described in any one of scopes 1 to 13 of the patent scope: at least any one of the coils is magnetically combined with each other. A transformer consisting of more than two coils. -12- (10) (10) 200410376 The invention described in item 16 of the scope of patent application is characterized in that the coil-embedded multilayer substrate system described in any one of the scope of claims 1 to 15 of the scope of patent application is laminated Outside. The invention described in item 17 of the scope of the patent application includes the steps of forming an insulating layer constituting a multilayer substrate; forming at least a part of a winding portion of a coil parallel to the multilayer substrate on the insulating layer in the multilayer substrate A step of forming at least a portion of the coiled portion of the coil that is parallel to the multilayer substrate by electrically connecting the insulating layers with each other to form a vertical connection with each other, and thereby forming at least a portion of the coiled portion of the coil that is perpendicular to the multilayer substrate And until a predetermined coil supported by the multilayer substrate is formed by the winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate, The part of the multilayer substrate is suitable to repeatedly form the step of forming the insulating layer, the step of forming at least a portion of the winding portion of the coil parallel to the multilayer substrate, and the step of forming at least a portion of the winding portion of the coil perpendicular to the multilayer substrate. A step of at least any one of the steps, wherein the unit of the predetermined coil is When other unit windings of the same are viewed in the same direction, they each have a spiral pattern that rotates in mutually opposite directions, and a group of adjacent unit windings of the predetermined coil are at the front ends of the spiral pattern with each other or The ends are interconnected in each other. The invention described in claim 18 of the patent application scope includes the steps of forming an insulating layer constituting a multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate on the insulating layer in the multilayer substrate. (11) (11) 200410376 at least a part of the winding portion of the coil is electrically connected in parallel with the multilayer substrate by an electrical connection between the insulation layers, and a vertical connection portion with each other is formed according to this, thereby forming a perpendicular to the multilayer substrate A step of arranging at least a part of a winding portion of a coil; a step of disposing a core made of a columnar magnetic body formed inside the coil; and a step of passing the winding portion of the coil parallel to the multilayer substrate and The winding portion of the coil perpendicular to the multilayer substrate is formed until a predetermined coil supported in the multilayer substrate is formed. For the portion of the multilayer substrate formed so far, the step of forming an insulating layer is preferably repeated in parallel to form This step of forming at least a part of a winding portion of a coil of the multilayer substrate and forming a winding portion of a coil perpendicular to the multilayer substrate Points at least a part of the step of at least any one of the steps. The invention described in item 19 of the scope of the patent application includes the steps of forming an insulating layer constituting a multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate on the insulating layer in the multilayer substrate. A step of forming at least a portion of the winding portion of the coil perpendicular to the coil of the multilayer substrate by electrically connecting at least a portion of the winding portion of the multilayer substrate electrically with an insulating layer in parallel; and Until a predetermined coil supported in the multilayer substrate is formed by the winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate, the multilayer substrate formed so far is used. It is suitable to repeatedly form the step of forming an insulating layer, the step of forming at least a portion of a winding portion of a coil parallel to the multilayer substrate, and the step of forming at least a portion of a winding portion of a coil perpendicular to the multilayer substrate. At least one of the steps, wherein the coil is a magnetic field generated by at least one of the coils The variation of the force line is a plurality of coils configured with a minimum voltage induced by other coils of -14-(12) (12) 200410376. The invention described in claim 20 of the patent application feature includes: a step of forming an insulating layer constituting a multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate on the insulating layer in the multilayer substrate. A step of forming at least a portion of a coiled portion of the coil perpendicular to the multilayer substrate by electrically connecting at least a portion of the coiled portion of the multilayer substrate with an insulating layer electrically connected to each other in parallel; and to The winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate are formed with a predetermined coil supported in the multilayer substrate. In part, it is suitable to repeatedly form the step of forming an insulating layer, the step of forming at least a portion of a winding portion of a coil parallel to the multilayer substrate, and the step of forming at least a portion of a winding portion of a coil perpendicular to the multilayer substrate Any one of the steps, wherein the coil is a line of magnetic force generated by at least any one of the coils Through main direction orthogonal to the other coils and the central axis of the other coil of the coil disposed in a plurality of strips. The invention described in item 21 of the scope of patent application, in addition to the features of the invention described in any one of the scope of patent application 19 or 20, has the following features: It also has a columnar magnetic body. The step of forming the structured core inside at least one of the coils. The invention described in item 22 of the scope of patent application is in addition to the features of the invention described in any one of scopes 17 to 21 of the scope of patent application. In addition, the coil includes a multilayer substrate that is laminated on a semiconductor wafer. On the outside, there is a step of dicing the semiconductor wafer on which the multilayer substrate with a built-in coil is laminated into a semiconducting -15-(13) (13) 200410376 bulk wafer unit. The invention described in item 23 of the scope of patent application is in addition to the features of the invention described in any one of scope of patent applications 17 to 21: The outside of the wafer. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the structure of the multilayer substrate 1 built into the coil according to the first embodiment of the present invention will be described. Fig. 1 is a perspective view showing a schematic configuration of a multilayer substrate 1 in which a coil is incorporated. The coil-embedded multilayer substrate 1 is composed of a coil 1 a and a multilayer substrate 1 c. The coil a is a constituent element that imparts inductance formed as a part of the conductive layer in the formation steps of the plurality of insulating layers and each of the conductive layers in the multilayer substrate. The coil 1 a is a system whose central axis is parallel to the multilayer substrate, and includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. ]). The coil 1 a is preferably constituted by unit windings in which a repeating pattern of wires such as a square Jb, a circle, and the like is electrically connected in series and continuously (hereinafter, such a coil is referred to as a “multilayer coil”). The form of the coil 1a and its unit winding in this specification also broadly includes any form for imparting inductance. When the unit windings of the coil 1 a are viewed in the same direction as the other unit windings adjacent to each other, they have spiral patterns that rotate in opposite directions, and the unit windings adjacent to each other are in the spiral shape. The front ends or the ends of the patterns are connected to each other. By constituting the coil in this way, a, the number of windings in a unit winding can be made larger than 1 • 16- (14) (14) 200410376, and if the current flows through the coil 1 a, all unit windings will be the same Direction magnetic field, so inductance can be increased. Preferably, the winding portion of the multilayer substrate parallel to the coil la is formed by a part of the laminated conductive layer, and the winding portion perpendicular to the multilayer substrate is connected to the bumps and interlayers between the conductive layers adjacent to each other through the insulating layer. Or through holes. According to this, by forming the coil la and using a known multilayer substrate manufacturing technique such as a build-up method, the coil 1a can be simultaneously formed in the multilayer substrate during the manufacturing process of the multilayer substrate. The multilayer substrate 1 c is a substrate configured by laminating insulating layers. In addition, in the actual step of forming the multilayer substrate 1c, the insulating layer and the conductive layer are alternately laminated. A part of the conductive layer becomes a part of the coil 1a, and a part of the other insulating layer becomes a multilayer substrate 1c. Fig. 11 is a perspective view showing a process of laminating a multilayer substrate 1 in which a coil is incorporated. In this way, the multilayer substrate 1 with built-in coils is formed by forming each part of the coils 1a on each of the insulating layers 1c, and is then manufactured by lamination and integration. The coil-embedded multilayer substrate 1 may have a circuit including other coils formed in a direction extending parallel to the multilayer substrate or on the upper or lower side of the multilayer substrate. Next, the configuration of the multilayer substrate 2 built into the coil according to the second embodiment of the present invention will be described. FIG. 2 (a) is a perspective view showing a schematic configuration of the multilayer substrate 2 in which the coil is incorporated. The coil-embedded multilayer substrate 2 has a structure in which a magnetic body 2d is arranged inside the coil 2a. Each of the constituent elements of the coil-embedded multilayer substrate 2 is a constituent element of the coil-embedded multilayer substrate 1 and its numerals are changed from 1 to 2. Accordingly, since the magnetic body 2 d is arranged inside the coil 2a, there is an advantage that the inductance of the coil 2a can be increased. In addition, -17- (15) (15) 200410376 may have a configuration in which a magnetic body is arranged inside the coil 1 a of the multilayer substrate 1 in which the coil according to the first embodiment of the present invention is incorporated. Fig. 2 (b) and (c) are structural examples of other coils. In these examples, the coil is formed only in a winding portion in a direction parallel or orthogonal to the central axis of the coil. Next, the configuration of the multilayer substrate 3 built in the coil according to the third embodiment of the present invention will be described. Figs. 3 (a) and (b) are perspective views showing a schematic configuration of a multi-layered substrate 3 in which a coil is incorporated. In the embodiment shown in FIG. 3 (a), the multi-layer substrate 3 with built-in coils has a coil 3a having a central axis parallel to the multi-layer substrate, and the central axis is perpendicular to the center direction of the generated magnetic field, and is parallel to the multi-layer A structure in which a planar coil 3 b having a circuit surface in a plane of a substrate is arranged on a multilayer substrate 3 c. In the embodiment shown in Fig. 3 (b), the coil 3d is a multilayer coil. By arranging the two coils in this way, the influence of the magnetic field generated by the coil on one side and the coil on the other side can be prevented, and noise and the like due to such influence can be reduced. Next, a configuration of a multilayer substrate 4 built in a coil according to a fourth embodiment of the present invention will be described. Figs. 4 (a) and 4 (b) are perspective views showing a schematic configuration of the multilayer substrate 4 in which the coil is incorporated. In the embodiment shown in FIG. 4 (a), the coil-embedded multilayer substrate 4 has a coil 4a having a central axis parallel to the multilayer substrate and a coil 4b having a central axis parallel to the multilayer substrate. The generated magnetic field lines have the smallest voltage induced by other coils (for example, the main direction of magnetic field lines generated by any one coil passes through the other coils and intersects the central axis of the other coils at right angles). The main direction of the magnetic field lines penetrating the coil means, for example, the direction of the vector of the magnetic field lines passing through the coil on average. In the embodiment shown in Fig. 4 (a) -18- (16) (16) 200410376, the coils 4d and 4d are multilayer coils. Fig. 34 is a conceptual diagram for explaining a preferred arrangement of a plurality of coils for minimizing noise caused by mutual inductance in a multilayer substrate built in a coil according to the present invention. Fig. 34 is an arrangement for minimizing the voltage induced by the second coil when the magnetic field lines generated by the first coil are displayed. Among them, the main direction of the magnetic lines of force generated by the first coil passes through the second coil and is arranged perpendicular to the central axis of the second coil. Accordingly, by arranging the second coil, the influence of the magnetic field generated by the coil on one side and the coil on the other side can be prevented, and noise caused by such influence can be reduced. Moreover, many coils can be accumulated in a multilayer substrate to increase the degree of freedom in design. Next, a description will be given of the configuration of the multilayer substrate 5 built in the coil according to the fifth embodiment of the present invention. 5 (a) and 5 (b) are perspective views showing a schematic configuration of the multilayer substrate 5 in which the coil is incorporated. In the embodiment shown in Fig. 5 (a), a planar coil 5c having a circuit surface in a plane parallel to the multilayer substrate is added to the embodiment shown in Fig. 4 (a). In the embodiment shown in Fig. 5 (b), a planar coil 5c having a circuit surface in a plane parallel to the multilayer substrate is added to the embodiment shown in Fig. 4 (b). Accordingly, by arranging three coils, it is possible to prevent the influence of the magnetic field generated by any of the coils and other side coils, and to reduce noise and the like due to such effects. In addition, more coils can be accumulated in the multilayer substrate, which increases the degree of freedom in design. Next, a description will be given of a configuration of a multilayer substrate 6 built in a coil according to a sixth embodiment of the present invention. Fig. 6 is a perspective view showing a schematic configuration of the multilayer substrate 6 in which the coil is incorporated. The coil-embedded multilayer substrate 6 is a coil 6 a having a central axis parallel to the multilayer substrate and a coil 6 b which is parallel to the central axis and whose central axis is parallel to the multilayer substrate. Structure arranged in the multilayer substrate 6 c. Accordingly, by disposing two coils, mutual inductance can be generated between the two coils, and a transformer can be formed. In this case, by arranging magnetic bodies along the center axis of the two coils, the efficiency of the transformer can be further improved. Next, a description will be given of the configuration of the multilayer substrate 7 built in the coil according to the seventh embodiment of the present invention. Figs. 7 (a) and 7 (b) are perspective views showing a schematic configuration of the multilayer substrate 7 built in the coil. The coil-embedded multilayer substrate 7 includes a coil 7a having a central axis parallel to the multilayer substrate, and a coil 7b located in a position parallel to the central axis, and adjacent coils 7b are arranged in the multilayer substrate 7c. Structure of the square coil magnetic body 7d or 7e. Accordingly, by disposing two coils, mutual inductance can be generated between the two coils, and a transformer can be formed. The magnetic body may be arranged between the two coils, such as the magnetic body 7 d shown in FIG. 7 (a). For more effective magnetic bonding, such as the magnetic body 7 e shown in FIG. 7 (b), It may be arranged in a ring shape having a portion that passes through the central axis of both coils. Next, a description will be given of a configuration of a multilayer substrate 8 built in a coil according to an eighth embodiment of the present invention. Fig. 8 is a perspective view showing a schematic configuration of the multilayer substrate 8 in which the coil is incorporated. The coil-embedded multilayer substrate 8 is composed of a coil 8a having a central axis parallel to the multilayer substrate and a multilayer substrate 8c. The unit winding of the coil 1 a has a structure in which a conductor having a spiral structure is arranged in a plane parallel to the multilayer substrate. With this structure, a very dense coil can be formed in a limited volume, and the inductance can be increased. Fig. 9 is a perspective view showing a schematic structure of a multilayer substrate 9 with a coil built in the coil according to a ninth embodiment of the present invention (-20- (18) (18) 200410376). In the multilayer substrate 9 built in the coil, a magnetic body 9d is arranged between the two spirally-structured conductors of a unit winding, and a larger inductance can be obtained. The operation of the multilayer substrates 1 to 9 embedded in the coil will now be described. The coil-embedded multilayer substrates 1 to 9 are used as an interposer or electrode wiring for mounting a printed circuit board, a semiconductor wafer constituting a monolithic IC, or the like on the semiconductor wafer. Use of layers is preferred. In addition, the multi-layer substrates 1 to 9 included in the coil can form other circuit elements inside or be adhered to the outside, and can constitute a function of adding a circuit composed of such other circuit elements and the multi-layer substrates 1 to 9 included in the coil to a semiconductor wafer. Self-functional semiconductor. The coil-embedded multilayer substrates 1 to 9 can be simply and arbitrarily set by adjusting the coil elongation direction, and the self-inductance and mutual inductance can be freely changed. In addition, by fully or partially adjusting the area where the unit winding and the magnetic field are interlinked, the inductance can be set softly. In addition, the inductance can be increased by placing a magnetic body inside the coil. According to this, the multilayer substrates 1 to 9 included in the coil are provided with a piezo stone by an external circuit at the terminals on both sides of the coil, and function as an inductor or a transformer. Next, an embodiment of the present invention will be described. The vertical coils with the structure shown in Figures 35 to 37 are combined with the planar coils with the structure shown in Figures 38 to 40. When the coils are arranged close to each other, a three-dimensional electromagnetic field simulator (Sonnet) is used. Analyze the relationship between signal leakage and arrangement to the terminals of adjacent coils that are not directly connected to each other, and compare various situations. The unit of the length in the above figure is mm. The dielectric constant between conductors is 2. 0 implementation simulation. -21-(19) (19) 200410376 First, the analysis of the coil unit is performed. Fig. 41 is a graph showing a signal passing characteristic of a vertical coil obtained by simulation. Fig. 42 is a graph showing a signal passing characteristic of a planar coil obtained by simulation. Next, the case where adjacent coils are arranged is analyzed. The distance between the coils of the structure shown in Fig. 43 was obtained by simulation. The signal of the 1-mni parallel-arranged vertical coil (first embodiment) is shown in Fig. 44 through a characteristic diagram. S2 1, S3 1, and S41 in Fig. 44 show the degree of signal transmission from terminals T1 to T2, terminals T1 to T3, and terminals T1 to T4 in Fig. 43 (also in the following figures) same). The distance between the coils of the structure shown in Figure 45 was calculated by simulation. The signal of the 1mm parallel-arranged planar coil (second embodiment) is shown in Fig. 46 through a characteristic diagram. The signals of the vertical coils and the planar coils (third embodiment) arranged adjacent to each other in the structure shown in Figs. 4 and 7 are obtained by simulation. The characteristics are shown in Figs. The distance between the coils of the structure shown in Figure 49 was calculated by simulation. The signals of the 2mm parallel-arranged vertical coils (first embodiment) are shown in Fig. 50 through a characteristic diagram. The distance between the coils of the structure shown in Figure 51 was calculated by simulation. The signal of the 2 mm parallel-arranged planar coil (second embodiment) is shown in Fig. 52 through a characteristic diagram. From these results, it is known that in the third embodiment shown in FIG. 47, compared with the first embodiment shown in FIG. 43 and the second embodiment shown in FIG. 45, S 3 1, S The signal leakage shown by 4 1 is about 5 dB lower. Therefore, from the viewpoint of signal leakage, it is known that the third embodiment shown in FIG. 47 can be improved by the coil arrangement than the first embodiment shown in FIG. 43 and the second embodiment shown in FIG. 45. Signal leaked. Moreover, the improvement of the signal leakage ratio is such that the distance between the coils is 0. 2mm -22- (20) (20) 200410376 The first embodiment shown in Fig. 49 and the second embodiment shown in Fig. 51 are also excellent. The signals shown in Fig. 50 and Fig. 52 can be obtained respectively. Know by characteristics. In addition, it has been found that the first embodiment and the second embodiment are more suitable than the third embodiment in a case where the signal leakage is actively used to make the combination between signals function as a transformer. Next, the manufacturing method of the coil-embedded multilayer substrates 1 to 9 of the present invention will be described together with the advantages of the conventional technology. By using the method of the present invention, a coil having a desired winding number can be easily obtained. In the conventional method of forming a spiral pattern on a plane parallel to the plane of the substrate, it is necessary to increase the number of windings to increase the number of windings, resulting in a large increase in cost. It only needs to be in the elongation direction of the coil, and the cost increase is small. Hereinafter, a method for manufacturing a multilayer substrate with a coil embedded therein according to the present invention will be specifically described with a focus on the coil portion for the sake of simplicity. First, if the inner layer (second layer) part of Fig. 11 is prepared, the openings on both sides of the copper-clad laminated board, the conduction through the plated through-holes, and the surface pattern using the negative method are applied. A well-known method such as formation (pa 11 erning) is preferred. Next, for this second layer, if an insulating layer is formed on both sides and a conductive layer is further formed, and patterning and electrical connection are performed, the first picture can be obtained. Give examples for several methods. In the case of using the so-called build-up method, as shown in FIG. 15, an insulating layer is formed on the substrate of the second layer (consisting of 1 a and 1 b). For the insulating layer, a pre-preg resin glass cloth (pre-preg) such as an integrated glass epoxy-based or aromatic polyamide resin (pre-preg), a liquid or film thermoplastic, or -23-(21) ( 21) 200410376 A thermosetting resin composition, a copper foil generally called a resin-attached copper foil, and a substance of an insulating resin layer. The formation of the insulating layer can be performed as follows, for example. As shown in FIG. 15 (a), unpatterned copper foil ji or copper foil with resin 12 as shown in FIG. 15 (b) is disposed on both sides of the substrate of the second layer, as shown in FIG. As shown in FIG. 6, these materials are laminated / hardened collectively by a layer press method to form an integrated insulating layer and a conductive layer. (Alternatively, as shown in FIG. 17, the first-layer substrate is coated by a well-known and conventional method such as screen printing, curtain coating, and spray coating. It is hardened by electron wires, heat, or the like. Alternatively, it may be affixed to the substrate by a method such as roll, laminate, or the like, and hardened by a predetermined method to obtain an insulating layer 13.) Then, an interlayer is formed. . The interlayer 14 is formed at a predetermined position of the substrate obtained by the above method using drilling, laser, or the like. Fig. 18 (a) is a case where a prepreg resin glass cloth 10 and a copper foil 11 are used for an insulating layer and a conductive layer. Similarly, Fig. 18 (b) is a case where a copper foil 12 with a resin is used. FIG. 18 (c) shows a case where a liquid or film-like thermoplastic or thermosetting resin composition 15 is used. In the case of using a prepreg glass cloth or a copper foil with a resin to form an insulating layer and a conductive layer, when a carbon dioxide gas laser that is widely used to form a blind via is used, it is removed by etching in advance as necessary. The conductor at a predetermined position may be subjected to a so-called mask process. When using prepreg glass cloth or copper foil with resin to form the insulating layer and the conductive layer, for example, as shown in Figure 19 (a), the interlayer is printed with -24-(22) (22) 200410376 silver, The conductive paste 16 'of a conductive powder such as copper is embedded by a method such as dispensing, and is hardened by a predetermined method. Alternatively, as shown in FIG. 19 (b), a method of electroless plating is performed by electroplating a normal through-hole plating, that is, by providing a plating catalyst in the interlayer, and then forming a plating layer 17 by electrolytic plating. Electrical connection can also be achieved. A liquid or film-like composition is used to form an insulating layer as shown in FIG. 19 (c). For example, a copper foil 11 is stamped. A conductive layer is formed on the outside of the insulating layer. The conductive paste 16 or the plating layer 17 is electrically connected to the interposer. In this case, it is also possible to conduct the blind interlayer first. Further, as shown in FIG. 19 (d), a substrate is formed with a catalyst and an electroless plating process is applied to the substrate on which the insulating layer and the hafnium interposer are formed, and then the conductive layer 1 can be collectively performed by performing the electrolytic plating process as necessary. The formation of 8 and the conductivity of the blind dielectric layer. In this case, the conduction of the interposer can also be performed by a conductive paste. Alternatively, the insulating layer, the conductive layer, and the electrical connection can be collectively performed by the following method. That is, as shown in FIG. 20, a conductive paste 19 having a sharp front end is formed using a conductive paste or the like at a predetermined place on the second-layer substrate circuit, and then a prepreg Plexiglas 10 and a copper foil 11 (No. Fig. 20 (a)) or the thin film insulator 20 and the copper foil 11 (Fig. 20 (b)) or the resin-coated copper foil 12 are then press-processed (Fig. 20 (0) to penetrate the conductive bump 19) The insulation layer realizes the connection with the conductive layer. In the case of lamination by these build-up methods, the dielectric layer is made of conductive paste or electroplating, and filled with a conductive material, so that the cross section of the coil is made of conductive material However, even if the conventional through-hole has a structure in which only the outer periphery is electrically conductive, it is made of -25- (23) (23) 200410376, which uses the present invention with low noise, mechanical strength, and freedom of design. The characteristics of the coil formed by the method are not changed at all, and can be used in a frequency band without any problem. In addition, in the case where a coil portion is stacked to form a coil portion, in a general addition method such as through-hole plating, the so-called It is very difficult to construct a stacked via (Wa on via). As a result, one side of the coil is not in a straight line but has a step shape. However, even with this structure, the characteristics of the coil formed by the method of the present invention are not changed at all, and it can be used in a frequency band without problems. In addition, it is connected by plating In the case of using the above-mentioned liquid or film-like insulating material for the through hole, or in the case of laminating the insulating layer with a blind dielectric layer formed by the build-up method, the ink for buried holes or It is also possible to smooth the surface by burying through-holes or blind interposers by electroplating. In addition to the build-up method, it can also be laminated in the following ways. The insulating layer is for prepreg resin glass using epoxy glass. A four-layer structured coil of cloth will be described. That is, as shown in FIG. 21, a laser is used to perform a hole-cutting process at a predetermined position on the substrate side of the copper-clad single-sided glass epoxy substrate 21. Next, The copper foil 11 is used as an electrode for electroplating, and the holes generated by electroplating 17 are filled. Then, a low melting point metal bump 22 is made by the continuous plating method. As shown in FIG. 22, the copper foil 11 is scheduled to be etched and processed. of On the bump side, the same insulator composition 2 3 as that used for the insulating layer is thinly coated and semi-hardened. The composition shown in FIG. 2 and 2 of the single-sided substrate manufacturing becomes the outermost layer, which is the first. Layer and the fourth layer. • 26- (24) 200410376 Next, as shown in Figure 2 and 3, locate the second layer substrate and the outermost layer, and the semi-hardened composition is removed by pressing and forming. At the same time, the insulating layer between the layers is air-connected between the bump portion and the inner layer to produce a coil having a four-layer structure. It can be easily performed by applying more layers. At this time, the thickness of the insulating layer can be arbitrarily set according to the application. The viewpoint of edge reliability is practically 10 micrometers to 300 micrometers. The thickness of the left conductor is also the same as that of the insulating layer, and it is preferably practically about 5 micrometers to 200 micrometers according to the application. By arranging a magnetic body as a main component at the center of the coil, the coil of the present invention can obtain a larger inductance. The magnetic core structure can be explained by applying the paste containing iron, ferrous iron, and the like to the coil part. However, at the same time as the coil formation, as the target substrate, other necessary wires are also used. It is necessary to be formed in each layer in which a coil is formed. Therefore, there are several methods to choose from to match the formation of other circuits and wiring. In addition, when all the coils are made on the same plane, a part of the through-holes, that is, the direction accuracy perpendicular to the substrate plane becomes a problem, but the problem is caused by staggering the planes of the coils. A spiral circuit of a coil showing an example of this is shown in FIG. 10. The above problems can be solved by manufacturing a coil with a pattern on the first circuit surface and the second circuit surface. Moreover, the spiral structure is not formed on the same plane. For example, in the block shown in Fig. 22, the electric conductor is removed by this method, but it is better from the right. The setting, but the core structure, the formation of the fabrication are carried out. As described, the formation of the circuit or the process is appropriately selected to form the coil body, which can solve the problem shown in Figure 11 of each road surface shown in Figure -27-(25) (25) 200410376. Because each layer is formed independently, Since a spiral structure is formed during lamination, defects such as short circuits, which are the cause of defects such as etching defects, do not substantially occur. In addition, about half of each spiral structure is formed with so-called through holes. Because the cross-section of the through-hole is circular, there is no corner to prevent the resistance from being lowered. Furthermore, delamination in which the layer peeling occurs on the spiral circuit surface after the lamination is integrated does not occur. Furthermore, it is known that if an inductor is used in a high frequency region, a floating capacitor cannot be ignored. Floating capacitors are produced by inductive coils facing each other on the same plane and acting as capacitors. In the multilayer substrate with built-in coil of the present invention, since the floating capacitance of the induction coil can be regarded as a series of counter electrode surfaces, there are few problems. Furthermore, as shown in the above-mentioned Fig. 10, the structure of the staggered coil surface can be easily manufactured without using a special technique. If this configuration is used, the floating capacitance can be substantially reduced. Accordingly, the self-resonance frequency of the inductor can be kept high. By applying the above-mentioned process, a coil-embedded multilayer substrate of various embodiments can be manufactured. For example, as shown in FIG. 3, the coil-embedded multilayer substrate 3 is preferably laminated with an insulating layer and a conductive layer as shown in FIG. Further, as shown in FIG. 13, the coil-embedded multilayer substrate 6 shown in FIG. 6 is preferably a laminated insulating layer and a conductive layer. In the coil as shown in Fig. 7 (a), the multilayer substrate 7 is preferably laminated with an insulating layer, a conductive layer, and a magnetic body as shown in Fig. 14. Furthermore, a multilayer substrate with a coil built in as described above can also be formed on a semiconductor wafer constituting a single 1C or the like. With such a configuration, components such as coils can be assembled in a semiconductor with a high degree of integration. Now, the process of forming a line with the central axis parallel to the plane of the substrate on the semiconductor substrate is shown in γ -28-(26) 200410376. A typical example is an example in which a transistor is formed, and a so-called electrode wiring layer 'shown in FIG. 1 is formed on a so-called electrode wiring layer' which is an upper layer of a silicon wafer formed of tungsten or the like. By applying this method, the number can be set arbitrarily. J (layer) number, formation direction, etc. The 'semiconductor' is not limited to silicon, and any known semiconductor material such as gallium arsenic is used. First, as shown in Fig. 24, the lowermost insulating layer 25 is formed on the wafer where the transistor and the electrode portion are formed. Vapor-phase formation of silicon oxide film using CVD, etc., or post-bake (post-bake) after spin coating (Polyimide, benzocyclobutene, etc.) Organic raw materials. Then use various lasers to make holes 2 6 as necessary in the position shown in Figure 25. The holes 2 6 are at a specific position of the semiconductor wafer 24 or the position where they are connected to the lower electrode part. As shown in FIG. 26, a conductive layer is formed using a commonly used aluminum sputtering or a wet method such as a CVD phase method or a plating method. Next, exposure is performed to form a pattern. In some cases, the patterned photoresist layer may be electrically conductive. In this process, the holes 26 with the openings shown in FIG. 25 are also electrically conductive, and the first layer and the second layer are electrically connected. In addition, prior to the exposure process, the surface is usually planarized by a combination of physical honing called CMP (Chemical Mechanical Polishing) and chemical honing, etc., as shown in Section 2 7 The figure shows the formation of the second insulation 2 8. Then open the hole again as shown in Figure 28, and form a conductor pattern to form the fixed loop inside the pole loop of the first ring. The silicon method can be used. Bake) Butene is shown. After the process is then ground or sweated) 〇, such as the second lead -29- (27) (27) 200410376 electrical pattern 29. Next, as shown in FIG. 29, a third insulating layer 30 is formed by the aforementioned method, and openings, conductivity, and patterning are performed to form a third conductive pattern 31, and the conduction of the second layer and the third layer is obtained. . Repeat this operation in the future. After the fourth insulating layer 3 2 is formed as shown in FIG. 30, a hole, conductivity, and patterning are performed to form a fourth conductive pattern 3 3 ° If this operation is applied, the number of turns increases. It is possible to easily perform reduction, increase / decrease in the number of 歹 U (layers), formation of a plurality of coils having different elongation directions, and the like. When the conductive layer is formed after the insulating layer is formed and the holes are formed, and the electrical connection between the wires is performed, as shown in FIG. 31, if the conductive part 3 5 is used to fill the hole portion (interlayer) 34, as shown in FIG. 32 Displaying the cross section of the coil, a structure generally called a stacked interlayer can be formed, that is, a structure having an interlayer on the filled interlayer, and the sides of the coil can be formed into a straight line. In addition, a generally performed method is a method in which a conductive interlayer is not used to fill the interposer, and a stacked interposer structure is not formed. At this time, the manufactured coil has a stepped cross-section as shown in FIG. 33. FIG. Even with this structure, there is no problem in practical use especially in the case of use in a high frequency region. After forming a desired coil in the multilayer substrate on the silicon wafer 24, the multilayer substrate including the silicon wafer 24 and the coil is cut into semiconductor wafers. In addition, the silicon wafer 24 can be diced into wafer units before the silicon wafer 24 and the multilayer substrate with built-in coils are stacked. In this case, the outer surface of the semiconductor wafer that has been cut in advance is the same as the above-mentioned process, and a multilayer substrate with a built-in coil may be stacked. (30) (28) (28) 200410376 As described above, the coil-embedded multilayer substrate of the present invention has the characteristics of this coil in addition to the coils speculated by conventional methods, that is, the number of windings (number of layers) can be arbitrarily changed in the same process, and large inductance can be imparted. In addition, not only are coils built in which the formation direction can be changed arbitrarily, the coils do not adversely affect other parts or circuit noise, etc., and the crosstalk between the coils can be avoided. In addition, the so-called tombstone phenomenon that occurs when a coil is seen as a coil near a mounted coil as seen from a wafer inductor having the same structure. Based on this characteristic of the multi-layer substrate of the present invention, it can be said that such a coil, which is rarely known, has reached the stage of practical application for the first time. [Brief Description of the Drawings] Fig. 1 is a perspective view showing a schematic configuration of a multilayer substrate 1 built into a coil according to a first embodiment of the present invention (the coil portion in the substrate is also shown in the following drawings, Other circuits, wiring, etc. are omitted). Fig. 2 (a) is a perspective view showing a schematic configuration of a multilayer substrate 2 built into a coil according to a second embodiment of the present invention. Figs. 2 (b) and 2 (c) are views showing other coils. Structure example diagram. Fig. 3 is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 3 according to a third embodiment of the present invention. Fig. 4 is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 4 according to a fourth embodiment of the present invention. Fig. 5 is a perspective view showing a schematic configuration of a multilayer substrate 5 in a coil according to a fifth embodiment of the present invention. (31) (29) (29) 200410376 Fig. 6 is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 6 according to a sixth embodiment of the present invention. Fig. 7 is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 7 according to a seventh embodiment of the present invention. Fig. 8 is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 8 according to an eighth embodiment of the present invention. Fig. 9 is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 9 according to a ninth embodiment of the present invention. Fig. 10 is a cross-sectional view showing a conductor arrangement of unit windings of the coils adjacent to each other. Fig. 11 is a perspective view for explaining a manufacturing process of the multilayer substrate 1 with a coil built-in according to the first embodiment of the present invention. Fig. 12 is a perspective view for explaining a manufacturing process of a multi-layered substrate 3 built in a coil according to a third embodiment of the present invention. Fig. 13 is a perspective view for explaining a manufacturing process of the coil-embedded multilayer substrate 6 according to the sixth embodiment of the present invention. Fig. 14 is a perspective view for explaining a manufacturing process of the coil-embedded multilayer substrate 7 according to the seventh embodiment of the present invention. Fig. 15 is a perspective view showing an initial stage of manufacturing a multilayer substrate 1 with a coil built-in according to a first embodiment of the present invention. Fig. 16 is a perspective view showing an example of a method of manufacturing the multilayer substrate 1 with a coil built-in according to the first embodiment of the present invention. Fig. 17 is a perspective view showing an example of a manufacturing method of the built-in multilayer substrate 1 according to the first embodiment of the coil -32-(30) (30) 200410376. Fig. 18 is a perspective view showing an example of a method for manufacturing the multilayer substrate 1 with a coil built in it according to the first embodiment of the present invention. Fig. 19 is a perspective view showing an example of a method for manufacturing a multilayer substrate 1 with a coil built-in according to the first embodiment of the present invention. Fig. 20 is a perspective view showing an example of a method for manufacturing the multilayer substrate 1 with a coil built-in according to the first embodiment of the present invention. Fig. 21 is a perspective view showing an example of a method for manufacturing the multilayer substrate 1 with a coil built-in according to the first embodiment of the present invention. Fig. 22 is a perspective view showing an example of a method for manufacturing the multilayer substrate 1 with a coil built-in according to the first embodiment of the present invention. Fig. 23 is a perspective view showing an example of a method for manufacturing the multilayer substrate 1 with a coil built-in according to the first embodiment of the present invention. Fig. 24 is a cross-sectional view showing the initial stage of production on a 1C wafer in which the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention is formed. Fig. 25 is a cross-sectional view for explaining the formation of an interlayer. Fig. 26 is a sectional view for explaining formation of a conductive pattern for circuit formation. Fig. 27 is a cross-sectional view for explaining formation of a second insulating layer. Fig. 28 is a cross-sectional view for explaining formation of a second conductive pattern. Fig. 29 is a sectional view for explaining formation of a third layer. Fig. 30 is a cross-sectional view of a coil-embedded multilayer substrate 1 according to a first embodiment of the present invention formed on an IC wafer. Figure 31 is a cross-sectional view of the interposer. -33-(31) (31) 200410376 Fig. 32 is a cross-sectional view showing an example of a coil-embedded multilayer substrate 1 according to the first embodiment of the present invention formed on an IC chip. Fig. 33 is a sectional view showing an example of a coil-embedded multilayer substrate 1 according to the first embodiment of the present invention formed on an IC wafer. Fig. 34 is a conceptual diagram for explaining a preferred configuration of a plurality of coils for minimizing noise caused by mutual inductance in a multilayer substrate built in a coil according to the present invention. Fig. 35 is a perspective view of a vertical coil. Fig. 36 is a plan view of the vertical coil. Fig. 37 is a cross-sectional view taken along the arrow A-A of the vertical coil. Figure 38 is a perspective view of a planar coil. Fig. 39 is a plan view of a planar coil. Figure 40 is a B-B arrow cross-sectional view of a planar coil. Fig. 41 is a signal transmission characteristic diagram showing a vertical coil. Fig. 42 is a signal transmission characteristic diagram showing a planar coil. Fig. 43 is a longitudinal coil (the distance between the coils is 0. 1 mm). Fig. 44 is a diagram showing a longitudinal arrangement of the parallel coils (the distance between the coils is 0. 1 mm) signal through the characteristic diagram. Fig. 4 and Fig. 5 are plane coils arranged in parallel (the distance between the coils is 0. 1 mm). Figures 4 and 6 are plane coils (parallel coil distance 0. 1 mm) signal through the characteristic diagram. Figs. 4 to 7 are perspective views of a vertical coil and a planar coil arranged adjacent to each other in the multilayer built-in substrate of the coil according to the third embodiment; "34 * (32) (32) 200410376". Figures 4 to 8 are signal transmission characteristic diagrams showing the vertical coils and the planar coils arranged adjacent to each other in the coil-embedded multilayer substrate in the third embodiment. Figures 4 to 9 are longitudinal coils arranged in parallel (distance between the coils 0 and 0) according to the first embodiment. 2 m m) oblique view. FIG. 50 is a longitudinal coil (parallel coil distance of 0. 2 mm) signal through characteristic diagram. Fig. 51 is a plane coil (parallel coil distance of 0. 2mm). Fig. 52 is a diagram showing a planar coil (the distance between coils is 0. 2mm) signal passing characteristic chart. [Symbols] 1 to 9: Multilayer substrates la to 6a, 4b, 4d, 6b, 7a, 7b, and 8a included in the coil: Coils lc to 4c, 7c, and 8c: Multilayer substrates 2d, 7d, 7e, and 9 ch magnetic body 3b > 5c: planar coil 8 c: multilayer substrate 1 〇: prepreg glass cloth 1 1: copper foil 1 2: copper foil with resin 1 3: insulating layer 14: interposer-35- (33 (33) 200410376 1 5: Resin composition 16: Conductive paste 17: Plating layer 18: Conductive layer 19: Conductive bump 20 ... Insulator 2 1: Glass epoxy substrate 22: Metal bump 2 3: Insulator composition 2 4: Sand wafer 2 5: Insulating layer 2 6: Hole 27: Conductive pattern 2 8: Second insulating layer 2 9: Section Two conductive patterns 3 0: third insulating layer 3 1: third conductive pattern 3 2: fourth insulating layer 3 3: fourth conductive pattern 3 4: interlayer 3 5: conductors T1 to T4: terminals