JP7219136B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

2. Description of the Related Art Memory devices formed using semiconductors and having functions of writing, reproducing, and erasing memory data are known. The operation of the memory device is performed by applying a high voltage for a short period of time using various voltage sources different from the external power supply. For example, in a NAND type flash memory device, the external power supply is 3 V, but a voltage of about 15 to 20 V is required for writing and erasing memory data, and a voltage of about 8 to 10 V is required for reading memory data. It is

JP-A-2008-84933

Application of a high voltage in a general memory device is performed using a charge pump circuit. In order to boost the voltage in a short period of time, it is necessary to increase the capacity of the capacitors that constitute the charge pump circuit, and in this case, there is a problem that the power consumption and the chip size increase.

Some NAND-type flash memory devices are packaged by stacking a plurality of chips, but if a charge pump circuit is provided for each chip, the total cost and power will increase. There is a problem of hoarding.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an interposer that achieves reduction in chip area and power consumption, and a semiconductor device having the same.

In order to solve the above problems, the present invention employs the following means.

(1) An interposer according to an aspect of the present invention includes a ring-shaped iron core, a primary coil wound around a part of the iron core, and a secondary coil wound around another part of the iron core. wherein the iron core comprises a first metal pattern formed as a first metal layer and the primary coil is formed side-by-side as a second metal layer above the first metal layer a third metal pattern formed side by side as a third metal layer below the first metal layer; a plurality of first vias connecting the second metal layer and the third metal layer; The second metal pattern, the first via, the third metal pattern, and the first via are repeatedly connected in order so as to form a spiral, and the secondary coil is connected to the first metal a fourth metal pattern formed side by side as a fourth metal layer above the first metal layer; a fifth metal pattern formed side by side as a fifth metal layer below the first metal layer; The fourth metal pattern, the second via, the fifth metal pattern, and the second via are repeatedly connected in order so as to form a spiral. there is

(2) In the interposer described in (1) above, it is preferable that the number of contained metal layers is three or more.

(3) In the interposer described in either (1) or (2) above, it is preferable that the second metal layer and the fourth metal layer are the same layer.

(4) In the interposer according to any one of (1) to (3) above, it is preferable that the third metal layer and the fifth metal layer are the same layer.

(5) A semiconductor device according to an aspect of the present invention includes: the interposer according to any one of (1) to (4); a ring oscillator that inputs a voltage to a primary coil of the transformer; and an AD converter that outputs a voltage from the secondary coil of the device.

(6) In the semiconductor device described in (5) above, a first inverter including a first transformer and a second transformer as the transformers, wherein a primary coil of the first transformer constitutes the ring oscillator. , the secondary coil of the first transformer is connected to the first transistor forming the AD converter, and the primary coil of the second transformer is connected to the second inverter forming the ring oscillator. and a secondary coil of the second transformer is connected to a second transistor that constitutes the ring oscillator, and in the ring oscillator, the first inverter and the second inverter are arranged in a front stage and a rear stage or a rear stage and a front stage. and in the AD converter, the first transistor and the second transistor are adjacent to each other so as to have a relationship of front stage and rear stage or rear stage and front stage. is preferred.

The transformer of the present invention is constructed using three or more metal layers originally provided in an interposer that constitutes a power device. This transformer has the same function as the charge pump circuit externally attached to the interposer in the conventional power device and used as a booster circuit. Therefore, by applying an interposer that includes this transformer to a power device mounted on a semiconductor chip, a charge pump circuit as a booster circuit becomes unnecessary, resulting in a corresponding reduction in chip area and power consumption. can do.

1(a) and 1(b) are a perspective view and a cross-sectional view of a transformer according to an embodiment of the present invention; FIG. (a) to (d) are cross-sectional views of an object to be processed in the manufacturing process of the transformer of FIG. 3(a) to 3(c) are cross-sectional views of an object to be processed in the manufacturing process of the transformer of FIG. 1; FIG. (a) to (c) are plan views of an object to be processed in the manufacturing process of the transformer of FIG. FIG. 11 is a perspective view of a transformer according to Modification 1; 2 is a diagram schematically showing the configuration of a semiconductor device including the transformer of FIG. 1; FIG. 7 is an equivalent circuit diagram of a ring oscillator that constitutes the semiconductor device of FIG. 6; FIG. 7A and 7B are equivalent circuit diagrams of a first transformer and a second transformer that constitute the semiconductor device of FIG. 6; FIG. 7 is an equivalent circuit diagram of an AD converter that constitutes the semiconductor device of FIG. 6; FIG.

An interposer and a semiconductor device including the interposer according to embodiments to which the present invention is applied will be described in detail below with reference to the drawings. In addition, in the drawings used in the following explanation, in order to make the features easier to understand, the characteristic portions may be enlarged for convenience, and the dimensional ratios of each component may not necessarily be the same as the actual ones. do not have. Also, the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited to them, and can be implemented with appropriate modifications within the scope of the invention.

FIG. 1(a) is a perspective view of a transformer 100 included in an interposer according to one embodiment of the present invention. FIG. 1(b) is a cross-sectional view of the transformer 100 of FIG. 1(a) taken along line α-α. The transformer 100 is formed as part of a laminated structure obtained using a semiconductor process, and includes a ring-shaped iron core 101 and a part of the iron core (the left part in FIG. 1(a)) 101a. It is composed of a primary coil 102-1 to be wound and a secondary coil 102-2 to which another part of the iron core (right part in FIG. 1A) 101b is wound.

The expression “ring-shaped” here means that the through-hole 101H (the portion surrounded by the dashed line in FIG. 1A) extends substantially in one direction, and the entire periphery of the through-hole 101H is closed. shape. Although FIG. 1A illustrates a case where the through-hole 101H has a rectangular shape, the shape is not limited to this shape, and for example, other polygonal, circular, or a combination of multiple shapes can be used. It may be in shape.

The iron core 101 is formed as a metal layer (hereinafter referred to as a first metal layer 104) which is the Nth (N is a natural number) counted from the substrate side during mounting among a plurality of metal layers (layers having conductivity). , has a ring-shaped first metal pattern 101P. As a material of the iron core 101, for example, copper, aluminum, tungsten, or the like can be used.

The primary coil 102-1 is formed using at least two metal layers (hereinafter referred to as second metal layer 105-1 and third metal layer 103-1) and a via (hereinafter referred to as first via 107). be.

A second metal layer 105-1 is formed as a layer above the first metal layer 104 and has a plurality of second metal patterns 105-1P. The second metal pattern 105-1P is a linear pattern that straddles the first metal pattern 101P in plan view from the upper layer side of the second metal layer 105-1 (upper side in FIG. 1B). The plurality of second metal patterns 105-1P are arranged substantially parallel to each other.

A third metal layer 103-1 is formed as a layer below the first metal layer 104 and has a plurality of third metal patterns 103-1P. The third metal pattern 103-1P is a linear pattern that straddles the first metal pattern 101a in plan view from the lower layer side of the third metal layer 103-1 (lower side in FIG. 1B). The plurality of third metal patterns 103-1P are arranged substantially parallel to each other.

The first via 107 is a through wiring that connects the second metal layer 105-1 and the third metal layer 103-1, communicates the layer between these two metal layers, and one end 107a is the second metal layer 105. -1, and the other end 107b is connected to the third metal layer 103-1.

The primary coil 102-1 forms a helix, . , first via 107, third metal pattern 103-1P, . . . are repeatedly connected in this order. The pattern on both ends of the primary coil may be either the second metal pattern 105-1P or the third metal pattern 103-1P.

When the m-th (m is an integer of 2 or more) metal layer counted from the substrate side is the first metal layer 104, the second metal layer 105-1 means the (m+1)-th or more metal layer, and , the third metal layer 103-1 means the (m−1)-th metal layer and below.

The secondary coil 102-2 is formed using at least two metal layers (hereinafter referred to as fourth metal layer 105-2 and fifth metal layer 103-2) and a via (hereinafter referred to as second via 110). be done.

A fourth metal layer 105-2 is formed as a layer above the first metal layer 104 and has a plurality of fourth metal patterns 105-2P. The fourth metal pattern 105-2P is a linear pattern that straddles the first metal pattern 101P in plan view from the upper layer side of the fourth metal layer 105-2 (upper side in FIG. 1B). The plurality of fourth metal patterns 105-2P are arranged substantially parallel to each other.

A fifth metal layer 103-2 is formed as a layer below the first metal layer 104 and has a plurality of fifth metal patterns 103-2P. The fifth metal pattern 103-2P is a linear pattern that straddles the first metal pattern 101P in plan view from the lower layer side (the lower side in FIG. 1B) of the fifth metal layer 103-2. The plurality of fifth metal patterns 103-2P are arranged substantially parallel to each other.

The second via 110 is a through wiring that connects the fourth metal layer 105-2 and the fifth metal layer 103-2, communicates the layers between these two metal layers, and one end 110a is the fourth metal layer 105. -2, and the other end 110b is connected to the fifth metal layer 103-2.

The secondary coil 102-2 forms a spiral...fourth metal pattern 105-2P, second via 110, fifth metal pattern 103-2P, second via 110, fourth metal pattern 105- 2P, the second via 110, the fifth metal pattern 103-2P, . . . are repeatedly connected in this order. The pattern on both ends of the secondary coil may be either the fourth metal pattern 105-2P or the fifth metal pattern 103-2P.

When the m-th (m is an integer of 2 or more) metal layer counted from the substrate side is the first metal layer 104, the fourth metal layer 105-2 means the (m+1)-th or more metal layer, and , the fifth metal layer 103-2 means the (m−1)-th metal layer and below.

Materials for the first metal layer 104, the second metal layer 105-1, the third metal layer 103-1, the fourth metal layer 105-2, and the fifth metal layer 103-2 are known materials for forming wiring patterns. For example, copper, aluminum, tungsten, etc. can be used. As materials for the first via 107 and the second via 110, known materials for filling through holes, such as copper, aluminum, and tungsten, can be used.

From the viewpoint of thinning the interposer, the upper layers (the second metal layer 105-1 and the fourth metal layer 105-2) constituting the primary coil 102-1 and the secondary coil 102-2, respectively, and the lower layers (the third metal layer At least one of the layer 103-1 and the fifth metal layer 103-2) is preferably the same layer, more preferably both are the same layer. When the lower layers are the same layer and the upper layers are the same layer, the number of metal layers included in the interposer can be reduced to only three layers, the manufacturing process can be simplified, and the thickness of the interposer can be reduced. can be realized.

Both ends of the primary coil 102-1 are, as shown in FIG. 1(a), configured to be electrically connected to a power source that applies a voltage φ _in to be input to the transformer 100. FIG. Both ends of the secondary coil 102-2, as shown in FIG. 1(a), detect the voltage φ _out output from the transformer 100 and are electrically connected to a subsequent circuit that operates with the output voltage. configured to be able to

2(a)-(d) and 3(a)-(c) are cross-sectional views of an object to be processed in the manufacturing process of the transformer 100. FIG. FIGS. 4A to 4C are plan views of the objects to be processed in FIGS. 2A, 2C, and 3B, respectively, viewed from the upper layer side. 2(a), (c), and FIG. 3(b) are cross-sectional views of the object to be processed of FIGS. 4(a) to (c), taken along the β-β line.

The transformer 100 and the interposer 200 including the transformer 100 can be manufactured by the following procedure. First, as shown in FIG. 2(a), a layer directly below the transformer 100 is formed on one main surface 111a of the substrate 111, and then a second layer is formed on the layer directly below using a known method. A three metal pattern 103-1P and a fifth metal pattern 103-2P are formed. The third metal pattern 103-1P and the fifth metal pattern 103-2P to be formed are, as shown in FIG. 4A, a plurality of linear patterns arranged substantially parallel with a predetermined distance.

Next, using a known method, as shown in FIG. 2B, at least the third metal pattern 103-1P and the fifth metal pattern 103-2P are covered with silicon oxide SiO ₂ or the like. An insulating layer 112 is formed.

Next, as shown in FIG. 2C, a first metal pattern 104P is formed on the insulating layer 112 using a known method. The first metal pattern 104P has a ring shape (rectangular frame shape here) as shown in FIG. 1P, and another part (another side) overlaps the fifth metal pattern 103-2P.

Next, using a known method, as shown in FIG. 2D, an insulating layer 113 made of silicon oxide SiO ₂ or the like is formed to cover at least the first metal pattern 104P.

Next, through holes are provided through the insulating layer 113 using a known method so that a portion of the third metal pattern 103-1P and a portion of the fifth metal pattern 103-2P are exposed. Subsequently, each through-hole is filled with a conductive material such as copper, aluminum, or tungsten to form a first via 107 and a second via 110 as shown in FIG. 3(a).

Next, using a known method, as shown in FIG. 3B, by forming a second metal pattern 105-1P and a fourth metal pattern 105-2P, the core 101, the primary coil 102-1, A secondary coil 102-2 is formed and thus the transformer 100 can be obtained. The second metal pattern 105-1P and the fourth metal pattern 105-2P to be formed are, as shown in FIG. , two first vias 107 and two second vias 110 that sandwich the first metal pattern 104P.

Next, using a known method, as shown in FIG. 3(c), an insulation made of a predetermined material is formed so as to cover at least the second metal pattern 105-1P and the fourth metal pattern 105-2P. By forming the layers and the protective layer 114, the interposer 200 can be obtained.

(Modification 1)
FIG. 5 is a perspective view of a transformer 150 according to Modification 1 of transformer 100 described above. FIG. 1 illustrates the case where the core 101 is composed of only one layer of the first metal layer 104, but the core 101 includes layers other than the first metal layer as shown in FIG. 5 and has a stepped structure. may have. From the viewpoint of not interfering with electromagnetic induction, the number of layers constituting iron core 101 should be as small as possible, and as shown in FIG. 1, only one layer is more preferable. However, for example, if there is a predetermined structure M in the interposer and there is no space for a flat iron core consisting of only one layer, a stepped structure that avoids this structure M is effective. Become. As such a stepped structure, for example, as shown in FIG.

FIG. 6 is an image diagram of a circuit configuration of a semiconductor device 400 assumed when an interposer including the transformer 100 of this embodiment is applied as boosting means for memory devices such as DRAM and NAND flash. The circuit configuration of the semiconductor device 300 mainly includes an interposer 200 including two transformers (a first transformer 100A and a second transformer 100B), a memory device (not shown), a ring oscillator 116, an analog-to-digital (AD ) and a chip 300 on which the converter 117 and the like are mounted.

FIG. 7 is a diagram showing a main circuit configuration of ring oscillator 116. As shown in FIG. As shown in FIG. 7, the ring oscillator 116 is formed by connecting a plurality of inverters 118 in series. Each inverter 118 is configured to output a voltage φ' obtained by shifting the phase of the input voltage φ by 180°, and to input the voltage to the inverter 118 in the subsequent stage.

8A and 8B are diagrams showing the main circuit configurations of the first transformer 100A and the second transformer 100B of the interposer 200, respectively. In semiconductor device 400, ring oscillator 116 is configured to input voltage to the primary coils of first transformer 100A and second transformer 100B. Specifically, among the plurality of inverters 118 that make up the ring oscillator 116, the output terminals of two inverters (first inverter, second inverter) that are adjacent to each other so that the relationship between the preceding stage and the following stage or the following stage and the preceding stage is established. are electrically connected to the primary coil of the first transformer 100A and the primary coil of the second transformer 100B, respectively. In this case, the voltage φ _in input to the first transformer 100A and the voltage φ _in ′ input to the second transformer 100B are 180° out of phase. Therefore, the phase of the voltage φ _out output from the secondary coil of the first transformer 100A and the phase of the voltage φ _out ' output from the secondary coil of the second transformer 100B also differ by 180°. Become.

In addition, in either the first transformer 100A or the second transformer 100B, if the winding direction of the primary coil 102-1 and the winding direction of the secondary coil 102-2 are opposite, Even if voltages of the same phase are applied to both, the phases of the output voltages will differ by 180°. Therefore, in this case, both the primary coil of the first transformer 100A and the primary coil of the second transformer 100B may be connected to the same inverter 118 output terminal of the ring oscillator 116 .

FIG. 9 is a diagram showing the main circuit configuration of the AD converter 117. As shown in FIG. As shown in FIG. 9, AD converter 117 has a structure in which a plurality of MOS transistors 119 are connected in series, and capacitors 120 are connected to the respective gate electrodes. The AD converters 117 are adjacent to each other so that the AC voltages φ _out and φ _out ' output from the first transformer 100A and the second transformer 100B have a front-to-back or rear-to-front relationship, respectively. It is configured to be applied to respective capacitors connected to two MOS transistors (first transistor, second transistor). Since the two types of AC voltages φ _out and φ _out ′ that are applied have a phase difference of 180° with each other, they form a charge transfer charge pump circuit, are converted into DC voltages by the AD converter 117, and are converted into DC voltages in the memory device. supplied to

As described above, the transformer 100 according to the present embodiment is configured using three or more metal layers originally provided in the interposer that constitutes the power device. This transformer 100 is externally attached to an interposer in a conventional power device and has the same function as a charge pump circuit used as a booster circuit. Therefore, by applying an interposer including this transformer 100 to a power device mounted on a semiconductor chip, the number of stages of the charge pump circuit configuration as a booster circuit can be greatly reduced, and the chip area can be reduced accordingly. A reduction in power consumption can be achieved.

Reference Signs List 100, 150 Transformer 100A First converter 100B Second converter 101 Core 101a Part of core 101b Other part of core 101A, 101B ... divided portion 101H of iron core ... through hole 101P ... first metal pattern 102-1 ... primary coil 102-2 ... secondary coil 104 ... first metal pattern 105- 1 Second metal layer 105-1P Second metal pattern 103-1 Third metal layer 103-1P Third metal pattern 107 First via 107a Third One end 107b of one via... The other end of the first via 105-2... The fourth metal layer 105-2P... The fourth metal pattern 103-2... The fifth metal layer 103-2P... Fifth metal pattern 110 Second via 110a One end 110b of the second via 111 The other end 111 of the second via 111a One main surface of the substrate 112, 113 Insulation Layer 114 Protective layer 115 Via 116 Ring oscillator 117 AD converter 118 Inverter 119 MOS transistor 120 Capacitor 200 Interposer 300 Chip 400...Semiconductor device M...Structure

Claims (4)

a ring-shaped iron core;
a primary coil wound around a portion of the iron core;
A secondary coil that winds another part of the core, and an interposer that includes a transformer,
a ring oscillator that inputs a voltage to the primary coil of the transformer;
an AD converter that outputs a voltage from the secondary coil of the transformer,
In the interposer,
The iron core comprises a first metal pattern formed as a first metal layer,
A second metal pattern in which the primary coils are formed side by side as a second metal layer above the first metal layer, and a third metal pattern formed side by side as a third metal layer below the first metal layer. , a plurality of first vias connecting the second metal layer and the third metal layer,
the second metal pattern, the first via, the third metal pattern, the first via are repeatedly connected in order to form a spiral;
A fourth metal pattern in which the secondary coil is formed side by side as a fourth metal layer above the first metal layer, and a fifth metal pattern formed side by side as a fifth metal layer below the first metal layer. A pattern, comprising a plurality of second vias connecting the fourth metal layer and the fifth metal layer,
the fourth metal pattern, the second via, the fifth metal pattern, and the second via are repeatedly connected in order to form a spiral ;
A first transformer and a second transformer are provided as the transformers,
the primary coil of the first transformer is connected to a first inverter that constitutes the ring oscillator;
the secondary coil of the first transformer is connected to a first transistor that constitutes the AD converter;
the primary coil of the second transformer is connected to a second inverter that constitutes the ring oscillator;
the secondary coil of the second transformer is connected to a second transistor forming the ring oscillator;
In the ring oscillator, the first inverter and the second inverter are adjacent to each other so as to have a front-to-back or rear-to-front relationship, and
In the AD converter, the semiconductor device is characterized in that the first transistor and the second transistor are adjacent to each other so as to have a front-stage and rear-stage relationship or a rear-stage and front-stage relationship . 2. The semiconductor device according to claim 1, wherein the number of metal layers included in said interposer is three or more. 3. The semiconductor device according to claim 1, wherein said second metal layer and said fourth metal layer are the same layer. 4. The semiconductor device according to claim 1, wherein said third metal layer and said fifth metal layer are the same layer.

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