JP2011181577A - Boosting circuit, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a boosting circuit capable of reducing a chip area of a semiconductor chip. <P>SOLUTION: A boosting circuit 100 includes N (N is a natural number of 2 or more) capacitive elements (capacitive elements C0-C3). A K-th (1<K<N, K is a natural number) capacitive element (the capacitive element C2) among the N capacitive elements receives a (K-1)th boosted voltage boosted by a (K-1)th capacitive element (the capacitive element C1), and generates a K-th boosted voltage obtained by further boosting the (K-1)th boosted voltage to supply to a (K+1)th capacitive element (the capacitive element C3). An N-th boosted voltage is generated from one end (an output terminal OUT) of an N-th capacitive element. Among the N capacitive elements, at least one capacitive element (the capacitive elements C0 and C1) is formed in a second chip (a semiconductor chip CHIP1) different from a first chip (a semiconductor chip CHIP2) in which other capacitive elements (the capacitive elements C2 and C3) are formed, wherein the first and second chips are laminated with each other. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a booster circuit and a semiconductor device.

  In a semiconductor device typified by a DRAM (Dynamic Random Access Memory), a voltage higher than a DC voltage supplied from the outside of the semiconductor device may be supplied to an internal circuit existing in a semiconductor chip constituting the device. Here, examples of the internal circuit include a booster circuit that supplies a high voltage to a word line that drives a memory cell, or a back bias generator that makes a semiconductor substrate on which an N-channel MOS transistor is formed a negative voltage.

  By the way, as a booster circuit, a Cockcroft-Wallton circuit is known (see, for example, Patent Documents 1 and 2). The Cockcroft-Wallton circuit is a rectifier booster circuit in which a capacitive element and a rectifier element are combined and connected in series in multiple stages. One end of the circuit is driven by the secondary winding of the transformer, and a DC high voltage is extracted from the opposite end. Is. That is, according to the Cockcroft-Walton circuit, the AC voltage formed in the secondary winding of the transformer is rectified every half wave, and the rectified voltage is sequentially added by a multistage series circuit combining a capacitive element and a rectifying element, A high DC voltage is taken from the final stage of the multistage series circuit.

JP 2006-286302 A Japanese Patent Laid-Open No. 11-8159

  If a Cockcroft-Wallton circuit is formed on a semiconductor chip, a high voltage can be generated and supplied to the internal circuit. However, in order to generate a high voltage, a chip area of a semiconductor chip is increased by combining a capacitor element and a rectifying element and connecting them in multistage series. Further, in order to stably supply current to the internal circuit, the size of each of the capacitive element and the rectifying element is increased, and the chip area of the semiconductor chip is increased. That is, forming a circuit that generates a high voltage on a semiconductor chip, such as a Cockcroft-Walton circuit, has a problem of increasing the chip area.

  The present invention includes N capacitive elements (N is a natural number of 2 or more), and the Kth capacitive element (1 <K <N, K is a natural number) among the N capacitive elements is (K−1). ) Receiving the (K-1) th boosted voltage boosted by the (th) capacitive element, generating a Kth boosted voltage by further boosting the (K-1) th boosted voltage, and (K + 1) ) A booster circuit that supplies the Nth capacitive element and generates the Nth boosted voltage from one end of the Nth capacitive element, and at least one of the N capacitive elements is another capacitor. The booster circuit is formed on a second chip different from the first chip on which the element is formed, and the first and second chips are stacked on each other.

  According to the present invention, since a circuit that generates a high voltage, such as a Cockcroft-Wallton circuit, is formed on a plurality of semiconductor chips of at least two chips, the chip area can be reduced.

It is a logic circuit diagram of the booster circuit of the present invention. It is a figure showing the cross-sectional structure at the time of forming the logic circuit diagram of FIG. 1 on a semiconductor substrate. FIG. 6 is a logic circuit diagram of a booster circuit according to another embodiment of the present invention. It is a figure showing the cross-sectional structure at the time of forming the logic circuit diagram of FIG. 3 on a semiconductor substrate. FIG. 6 is a logic circuit diagram of a booster circuit according to another embodiment of the present invention. It is a structural diagram showing the system incorporating the booster circuit of the present invention.

A typical example of the technical idea for solving the problems of the present invention is shown below. However, it goes without saying that the claimed contents of the present invention are not limited to this technical idea, but are the contents described in the claims of the present invention.
A booster circuit (for example, a Cockcroft-Wallton circuit) has a combination of two rectifier elements and a capacitor element as one stage, and has an n-stage series connection, the amplitude V0 (the peak value is ± V0 / 2) is a circuit that outputs a DC output voltage of n × V0 from the output terminal. Various circuits are connected to the output terminal of the booster circuit as a load depending on the application. In order for the booster circuit to supply a stable DC voltage to the circuit connected to the output terminal, it is necessary to increase the drive capability of the booster circuit, for example, by increasing the size of the circuit rectifier element and the capacitor element.

However, providing the booster circuit on each semiconductor chip requires increasing the circuit constants of the rectifier element and the capacitor element, and increases the chip size of the semiconductor chip. Therefore, in a semiconductor device having, for example, an MCP structure assembled by stacking a plurality of semiconductor chips, it is conceivable that the booster circuit is configured by the entire stacked semiconductor chips. If the booster circuits are dispersed in the stacked semiconductor chips in this way, it is not necessary to provide a large booster circuit in each semiconductor chip.
That is, the technical idea of the present invention is a circuit for generating a boosted voltage obtained by cumulatively boosting a charge pump voltage using a plurality of capacitive elements, and the plurality of capacitive elements are distributed over a plurality of stacked chips. The technical idea is to arrange them.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a logic circuit diagram of a booster circuit 100 according to an embodiment of the present invention. In FIG. 1, the booster circuit 100 includes a capacitive element and a rectifying element provided in each of a semiconductor chip CHIP1 (second chip) and a semiconductor chip CHIP2 (first chip). Here, a region between the broken lines L1 and L2 is a region of the semiconductor chip CHIP1, and a region between the broken lines L2 and L3 is a region of the semiconductor chip CHIP2. The booster circuit 100 is configured by stacking a semiconductor chip CHIP1 and a semiconductor chip CHIP2.

  The semiconductor chip CHIP1 receives an alternating voltage from the node 1A and the node 1B and outputs a boosted voltage from the node 2A and the node 2B. The semiconductor chip CHIP2 further boosts the boosted voltage supplied from the semiconductor chip CHIP1, Output to 3A and node 3B. Among these, the node 3B becomes the output terminal OUT.

  The semiconductor chip CHIP1 includes a capacitive element C0 between the node 1A and the node 2A, a rectifier element (diode D0) between the node 1B and the node 2A (node 1C in FIG. 1), and between the node 1C and the node 2B. Are provided with a rectifying element (diode D1) and a capacitor C1 between the node 1B (node 1D in FIG. 1) and the node 2B. The diode D0 has an anode connected to the node 1B and a cathode connected to the node 1C. The diode D1 has an anode connected to the node 1C and a cathode connected to the node 2B.

  The semiconductor chip CHIP2 includes a capacitive element C2 between the node 2A and the node 3A, a rectifier element (diode D2) between the node 2B and the node 3A (node 2C in FIG. 1), and between the node 2C and the node 3B. Are provided with a rectifying element (diode D3) and a capacitive element C3 between the node 2B (node 2D in FIG. 1) and the node 3B. The diode D2 has an anode connected to the node 2B and a cathode connected to the node 2C. The diode D3 has an anode connected to the node 2C and a cathode connected to the node 3B.

  The semiconductor chip CHIP1 corresponds to a lowermost chip when the booster circuit 100 is formed by stacking chips. The node 1A and the node 1B of the semiconductor chip CHIP1 are connected to the node A and the node B to which an alternating voltage is supplied, respectively. Here, the symbol Ts in FIG. 1 indicates an AC generator, and generates, for example, a sine wave between the node A and the node B. That is, the AC generation unit Ts supplies the nodes A and B with signals whose phases are inverted by 180 degrees. In the following description of the operation of the booster circuit 100, the AC generator Ts has an AC voltage with a peak value E (amplitude is 2E) in which the voltage changes between a negative voltage (−E) and a positive voltage (+ E) every cycle. ) To the node A and the node B.

  That is, in the semiconductor chip CHIP1, the capacitive element C0 connected between the first input terminal (node 1A) and the first output terminal (node 2A) to which the first signal is input, the first signal and the phase , A capacitive element C1 connected between the second input terminal (node 1B) and the second output terminal (node 2B) to which a signal inverted by 180 degrees is input, the second input terminal (node 1B) and the first A rectifying element (diode D0) connected between the output terminal (node 2A) and a rectifying element (diode D1) connected between the first output terminal (node 2A) and the second output terminal (node 2B). ) And a first stage (first stage) of a booster circuit constituted by a combination.

  Further, the semiconductor chip CHIP2 has a capacitive element C2 connected between the first input terminal (node 2A) connected to the first output terminal (node 2A) of the semiconductor chip CHIP1 and the first output terminal (node 3A). A capacitive element C3 connected between the second input terminal (node 2B) connected to the second output terminal (node 2B) and the second output terminal (node 3B) of the semiconductor chip CHIP1, and a second input A rectifier (diode D2) connected between the end (node 2B) and the first output end (node 3A), and between the first output end (node 3A) and the second output end (node 3B) This constitutes one stage (second stage) of a booster circuit composed of a combination of a rectifying element (diode D3) to be connected.

Thus, the first stage constituting the booster circuit 100 is provided in the semiconductor chip CHIP1, and the second stage having the same configuration as the first stage is provided in the semiconductor chip CHIP2. That is, the booster circuit 100 is arranged in a distributed manner on a plurality of chips (in this case, two chips CHIP1 and CHIP2).
Next, the operation of the booster circuit 100 configured as described above will be described.

  When an AC voltage is supplied to the semiconductor chip CHIP1, the rectifier element (diode D0) causes the capacitor element C0 to be at the voltage level in the first negative half cycle (cycle in which the voltage level at the node A is lower than the voltage level at the node B) Charge to E. When the capacitance value of each of the capacitive elements C0 to C3 is C, the terminal on the AC generation unit Ts side is the (−) terminal, and the terminal on the output terminal OUT side is the (+) terminal, the capacitive element C0 includes (E × C ) Is charged.

  Next, the rectifying element (diode D1) moves the charge charged in the capacitive element C0 to the capacitive element C1 and charges the capacitive element C1 in the positive half cycle following the negative half cycle described above. In this half cycle, a reverse bias is applied between the anode and cathode of the diode D0, so that the charge of the capacitive element C0 does not flow to the AC power supply side. Further, the capacitive element C0 has a voltage level E at the (−) terminal and a voltage level 2E at the (+) terminal, whereby the difference in voltage level between the (+) terminal and the (−) terminal of the capacitive element C1 is 2E. Become.

  Next, in the negative half cycle following the positive half cycle described above, the rectifying element (diode D2) moves the charge charged in the capacitive element C1 to the capacitive element C2, and charges the capacitive element C2. In this half cycle, since a reverse bias is applied between the anode and cathode of the diode D1, the charge of the capacitive element C1 does not flow to the capacitive element C0 side. In addition, the capacitive element C1 has a voltage level E at the (−) terminal and a voltage level 3E at the (+) terminal, whereby the difference in voltage level between the (+) terminal and the (−) terminal of the capacitive element C2 is E and Become.

Next, in the positive half cycle following the negative half cycle described above, the rectifying element (diode D3) moves the charge charged in the capacitive element C2 to the capacitive element C3, and charges the capacitive element C3. In this half cycle, a reverse bias is applied between the anode and cathode of the diode D2, so that the charge of the capacitive element C2 does not flow to the AC power supply side. Further, the capacitive element C2 has a voltage level E at the (−) terminal and a voltage level 3E at the (+) terminal, whereby the difference in voltage level between the (+) terminal and the (−) terminal of the capacitive element C3 is 2E. Become.
That is, when the peak value of the AC voltage is E, the voltage level of the node 2B is 2E, and the voltage level of the node 3B is 4E. In this embodiment, the Cockcroft-Walton circuit is configured in two stages. However, in general, in the case where it is configured in n stages, the level of the DC voltage that can be taken out from the output terminal OUT is ideally Is 2 × n × E.

  As described above, in the above description of the operation, of the two capacitive elements constituting each stage constituting the booster circuit 100, the voltage level is first boosted, and the charged charge is transferred to the other capacitive element in the same stage. The capacitive element to be moved is a capacitive element (capacitive element C0 or C2) connected between the first input terminal and the first output terminal. In the above description, in the first stage, the capacitive element C0 is boosted first, and charges are transferred to the capacitive element C1. In the second stage, the capacitive element C2 is first boosted to move charges to the capacitive element C3. Of course, since the first stage and the second stage are connected to form a booster circuit, the voltage level of the previous stage capacitive element (capacitance element C1) is boosted first between the first stage and the second stage. Then, the charged electric charge is moved to the subsequent capacitor element (capacitor element C2).

  That is, the booster circuit 100 generally includes N (N is a natural number greater than or equal to 2) capacitive elements, and the Kth (1 <K <N, K is a natural number) of the N capacitive elements. The capacitive element receives the (K-1) th boosted voltage boosted by the (K-1) th capacitive element, and further boosts the (K-1) th boosted voltage. This is a booster circuit that generates a voltage, supplies it to the (K + 1) th capacitor element, and generates an Nth boosted voltage from one end (output terminal OUT) of the Nth capacitor element. Here, in the description of the above embodiment, N = 4, and the first capacitive element C0, the second capacitive element C1, the third capacitive element C2, and the fourth capacitive element C3 are arranged in this order. Then, the voltage is boosted to move the charge to the next capacitor element. By repeating this, it is possible to charge each capacitive element to the voltage level 2E as the maximum voltage and take out the boosted DC voltage (voltage level 4E) from the output terminal OUT.

Further, when the booster circuit 100 is configured by M semiconductor chips (M is a natural number of 2 or more) each including two capacitor elements and rectifier elements, the first and Lth stages ( 1 <L ≦ M, where L is a natural number), the connection relationship of the above elements can be expressed as follows.
The first stage constituting the booster circuit 100 is formed on the first semiconductor chip located at the lowest layer, and has a first input terminal (node 1A) to which a first signal is input and a first output terminal (node). 2A), a second input terminal (node 1B) and a second output terminal (node 2B) to which a signal whose phase is inverted by 180 degrees from the first signal is input. ) And a first rectifier element (diode D0) connected between the second input terminal (node 1B) and the first output terminal (node 2A). ) And a second rectifying element (diode D1) connected between the first output terminal (node 2A) and the second output terminal (node 2B).

  The Lth stage constituting the booster circuit 100 is formed on the Lth semiconductor chip counted from the first chip located in the lowest layer, and the first of the (L−1) th semiconductor chips. The (2L-1) th capacitor connected between the first input terminal (referred to as node LA) connected to the output terminal (node LA) and the first output terminal (referred to as node (L + 1) A). A second input terminal (node LB) and a second output terminal (node (L + 1)) connected to the element C (2L-2) and the second output terminal (node LB) of the (L-1) th semiconductor chip. B) and the (2L) th capacitive element C (2L-1) connected between the second input terminal (node LB) and the first output terminal (node (L + 1) A). (2L-1) th rectifier element (diode D (2L-2)) and the first output terminal (node (L + ) A) and the second output terminal (node (L + 1) B) second is connected between the (2L) th rectifying element (diode D (2L-1)), it consists of a combination of.

  With such a configuration, when two layers of the semiconductor chips CHIP1 and CHIP2 shown in FIG. 1 are stacked, that is, in a two-stage Cockcroft-Wallton circuit, 2 × (2E ) Can be taken out. Here, considering the case where M chips are stacked as the semiconductor chip, the above operation can be repeated in the third and subsequent stages to extract M × (2E) boosted voltage from the output terminal OUT.

  In FIG. 1, the booster circuit 100 is composed of two chips, semiconductor chips CHIP1 and CHIP2, within a range indicated by broken lines L1, L2, and L3. That is, the first stage and the second stage of the booster circuit are formed on two chips. This makes it possible to reduce the surface area occupied by the capacitive element and the rectifying element as compared with the case where the booster circuit 100 is formed on one chip.

  Note that this one-stage portion can be further divided into two groups and formed on a total of four chips. For example, in FIG. 1, ranges shown between the dashed line L1 and the dashed line L1H, between the dashed line L1H and the dashed line L2, between the dashed line L2 and the dashed line L2H, and between the dashed line L2H and the dashed line L3. Can be divided into four chips.

That is, the booster circuit includes first to M-th stages formed on the first to M-th (M is a natural number of 2 or more) chips from the bottom layer.
Here, the first stage has a first capacitive element connected between the first input terminal to which the first signal is input and the first output terminal, and the phase of the first signal is inverted by 180 degrees. And a first rectifier connected between the second input terminal and the first output terminal to which the received signal is input, and the second input terminal and the second output terminal are directly connected. Is done.
The second stage includes a second capacitive element connected between the second input terminal of the first chip connected to the second output terminal of the first chip and the second output terminal of the first chip; A first rectifier element connected between the first input terminal of the first chip connected to the first output terminal of the first chip and the second output terminal of the first chip; A direct connection is made between one input end and its first output end.

Further, the third and subsequent stages, that is, the L-th stage (2 <L ≦ M) of the first to M-th stages can be expressed as follows depending on whether L is an odd number or an even number.
That is, when L is an odd number, the L-th stage is connected between its first input terminal connected to the first output terminal of the (L−1) -th chip and its first output terminal. The (L) th capacitive element and the second output terminal connected to the second output terminal of the (L-1) th chip and the first output terminal connected to the first output terminal of the first (L-1) th chip. (L) It is comprised from the combination with the rectifier, and between its 2nd input terminal and its 2nd output terminal is connected directly.
On the other hand, when L is an even number, the L-th stage is connected between its second input terminal connected to the second output terminal of the (L-1) -th chip and its second output terminal. A first (L) -th capacitive element and a first input terminal connected to the first output terminal of the (L-1) -th chip and a second output terminal connected to the second output terminal. (L) It is comprised from the combination with the rectifier, and between its 1st input terminal and 1st output terminal is connected directly.

Further, when M is an odd number, the boosted voltage is output from the first output terminal of the Mth chip, and when M is an even number, the boosted voltage is output from the second output terminal of the Mth chip.
In this case, since it is sufficient to form one capacitive element and one diode on each chip, it is possible to further reduce the surface area occupied by the capacitive element and the diode on one chip.

Next, an embodiment in which the logic circuit shown in FIG. 1 is realized on a semiconductor substrate will be described.
FIG. 2 is a structural diagram of the logic circuit diagram of FIG. 1, and represents a cross-sectional view of the semiconductor chip when the booster circuit 100 is formed by stacking semiconductor chips CHIP1 and CHIP2 having the same configuration. .
In FIG. 2, the region of the semiconductor chip CHIP1 is a region in the range shown between the broken lines L1 and L2, and the region of the semiconductor chip CHIP2 is a region in the range shown between the broken lines L2 and L3. The semiconductor chip CHIP1 is provided below the semiconductor chip CHIP2, and the two chips are connected by a bump electrode BP31 and a bump electrode BP12, a bump electrode BP41 and a bump electrode BP22, and a bump electrode BPSS21 and a bump electrode BPSS12. Here, the connection point between the bump electrode BP31 and the bump electrode BP12 corresponds to the node 2A shown in FIG. 1, and the connection point between the bump electrode BP41 and the bump electrode BP22 corresponds to the node 2B shown in FIG.

  Further, the bump electrode BP11 and the bump electrode BP21 in the semiconductor chip CHIP1 are respectively connected to, for example, a wiring on the package substrate on which the booster circuit 100 is mounted, on the broken line L1 in FIG. The connection point between the bump electrode BP11 and the wiring on the substrate corresponds to the node A shown in FIG. 1, and the connection point between the bump electrode BP21 and the wiring on the substrate corresponds to the node B shown in FIG. To do. Then, the node A and the node B are respectively connected to an AC generator Ts (not shown in FIG. 2). The bump electrode BPSS11 is an electrode for supplying the ground voltage VSS to the P-type semiconductor substrate PSUB.

The bump electrode is connected to a contact on the surface of the P-type semiconductor substrate PSUB by a through electrode penetrating the P-type semiconductor substrate PSUB. The through electrode is an electrode that transmits a signal supplied to the bump electrode formed on the back surface of the substrate to the front surface side of the substrate, and is electrically insulated from the P-type semiconductor substrate PSUB. The through electrode is also provided above the semiconductor chip, and electrically connects the contact in the chip and the bump electrode.
For example, the bump electrode BP11 is connected to the contact CT11 on the surface side of the P-type semiconductor substrate PSUB via the through electrode PE11. Similarly, the bump electrode BP21 is connected to the contact CT21 on the surface side of the P-type semiconductor substrate PSUB via the through electrode PE21. Further, the bump electrode BPSS11 is connected to a contact CT161 on the surface side of the P-type semiconductor substrate PSUB via the through electrode PESS11.

Next, the internal structure of the semiconductor chip CHIP1 will be described.
In FIG. 2, the vertical wiring on the surface side of the P-type semiconductor substrate PSUB corresponds to a so-called contact, and the horizontal wiring corresponds to a so-called wiring layer.
A capacitive element C0 in FIG. 1 uses a depletion type MOS transistor formed on a P-type semiconductor substrate PSUB. The capacitive element C0 includes a gate electrode GP51, an N-type diffusion layer ND31, and an N-type diffusion layer ND41. The N type diffusion layer ND31 and the N type diffusion layer ND41 are connected to the wiring LN11 via the contact CT31 and the contact CT41, respectively. The wiring LN11 is connected to the bump electrode BP11 described above via the contact CT11 and the through electrode PE11. The bump signal BP11 receives the first signal from the AC generator Ts.
The gate electrode GP51 is connected to the wiring LN31 via the contact CT51. The wiring LN31 is connected to the bump electrode BP31 via the contact CT131 and the through electrode PE31. Here, the contact CT131 is located at the same position as the contact CT11 when the semiconductor chip CHIP1 is viewed from above. The bump electrode BP31 is connected to the bump electrode BP12 of the upper semiconductor chip CHIP2.

Further, the capacitive element C1 in FIG. 1 includes a gate electrode GP121, an N-type diffusion layer ND101, and an N-type diffusion layer ND111. The N type diffusion layer ND101 and the N type diffusion layer ND111 are connected to the wiring LN21 via the contact CT101 and the contact CT111, respectively. The wiring LN21 is connected to the bump electrode BP21 through the contact CT21 and the through electrode PE21. The bump signal BP21 receives the second signal from the AC generator Ts.
Further, the gate electrode GP121 is connected to the wiring LN41 via the contact CT121. The wiring LN41 is connected to the bump electrode BP41 via the contact CT141 and the through electrode PE41. Here, the contact CT141 is located at the same position as the contact CT21 when the semiconductor chip CHIP1 is viewed from above. The bump electrode BP41 is connected to the bump electrode BP22 of the upper semiconductor chip CHIP2.
The capacitive elements C0 and C1 are not limited to this configuration. For example, the capacitive elements C0 and C1 are formed between the gate electrode and the N well by forming an N type well surrounding the N type diffusion layer immediately below the gate electrode. A capacitor element may be used.

The rectifying element (diode D0) includes a P-type diffusion layer PD61 (anode electrode) and an N-type diffusion layer ND71 (cathode electrode) formed in the P-type semiconductor substrate PSUB so as to surround the P-type diffusion layer PD61. The P-type diffusion layer PD61 is connected to wiring LN21 through contact CT61. The N-type diffusion layer ND71 is connected to the wiring LN31 via the contact CT71.
The rectifying element (diode D1) is formed from a P-type diffusion layer PD81 (anode electrode) and an N-type diffusion layer ND91 (cathode electrode) formed in the P-type semiconductor substrate PSUB so as to surround the P-type diffusion layer PD81. Composed. P-type diffusion layer PD81 is connected to wiring LN31 via contact CT81. The N-type diffusion layer ND91 is connected to the wiring LN41 via the contact CT91.

  The P-type diffusion layer PD151 formed in the P-type semiconductor substrate PSUB is a diffusion layer for supplying a ground voltage to the P-type semiconductor substrate PSUB, and is connected to the wiring LN51 via the CT151. The wiring LN51 is connected to the bump electrode BPSS11 via the contact CT161 and the through electrode PESS11 and grounded. Further, the contact CT161 is connected to the bump electrode BPSS21 through the through electrode PESS21 and is connected to the bump electrode BPSS12 of the upper semiconductor chip CHIP2.

In FIG. 2, the semiconductor chip CHIP2 stacked on the semiconductor chip CHIP1 can have the same internal structure as the semiconductor chip CHIP1. This is because, as described above, in the semiconductor chip CHIP1, the positions of the contact CT11 connected to the input end and the contact CT131 connected to the output end are located at the same position in plan view from above the chip. Further, the position of the contact CT21 connected to the input end and the position of the contact CT141 connected to the output end are located at the same position in plan view from above the chip. For this reason, the semiconductor chip CHIP2 has a boosted voltage generated by the semiconductor chip CHIP1 from its input terminal only by stacking the semiconductor chip having the same internal structure as that of the semiconductor chip CHIP1 with the bump electrodes positioned on the semiconductor chip CHIP1. It is because it can be taken in.
In FIG. 2, each element such as a transistor other than the through electrode and the bump electrode is assigned the same reference numeral as that of the semiconductor chip CHIP <b> 1, and the description thereof is omitted.
The bump electrode BP12 is connected to the bump electrode BP31 of the semiconductor chip CHIP1. The bump electrode BP12 is connected to the capacitive element C2 via the through electrode PE12, the contact CT11, and the wiring LN11. Therefore, as shown in the logic circuit of FIG. 1, the (+) terminal of the capacitive element C0 and the (−) terminal of the capacitive element C2 are connected. Further, the (+) terminal of the capacitive element C2 is connected to the bump electrode BP32 through the wiring LN31, the contact CT131, and the through electrode PE32. The bump electrode BP32 corresponds to the node 3A in FIG.

  The bump electrode BP22 is connected to the bump electrode BP41 of the semiconductor chip CHIP1. The bump electrode BP22 is connected to the capacitive element C3 through the through electrode PE22, the contact CT21, and the wiring LN21. Accordingly, as shown in the logic circuit of FIG. 1, the (+) terminal of the capacitive element C1 and the (−) terminal of the capacitive element C3 are connected. Further, the (+) terminal of the capacitive element C3 is connected to the bump electrode BP42 via the wiring LN41, the contact CT141, and the through electrode PE42. The bump electrode BP42 corresponds to the node 3B in FIG. 1 and also corresponds to the output terminal OUT.

  The bump electrode BPSS12 is connected to the bump electrode BPSS21 of the semiconductor chip CHIP1. The bump electrode BPSS12 is connected to the P-type diffusion layer PD151 through the through electrode PESS12, the contact CT161, the wiring LN51, and the contact CT151. Thereby, the ground voltage is supplied to the P-type semiconductor substrate PSUB. Further, the contact CT161 is connected to the bump electrode BPSS22 through the through electrode PESS22.

  In the present embodiment, a case is described in which the booster circuit 100 includes two chips, semiconductor chips CHIP1 and CHIP2. Therefore, there is no bump electrode of the upper layer chip connected to the bump electrodes BP32, BP42 and BPSS22 of the semiconductor chip CHIP2. When a stacked structure of three chips or more is adopted, bump electrodes on and after the third chip are connected so that the corresponding capacitive elements are connected. That is, the Kth capacitive element is connected to the (K + 2) th capacitive element, and is connected in series up to the topmost chip. The (K-1) th capacitive element is connected to the (K + 1) th capacitive element, and is connected in series up to the topmost chip.

  As described above, the booster circuit of the present invention includes N (N is a natural number of 2 or more) capacitive elements (for example, capacitive elements C0 to C3 when N = 4). The Kth (1 <K <N, K is a natural number) capacitive element (for example, the capacitive element C2 when K = 2) is boosted by the (K−1) th capacitive element (capacitor C1). In response to the (K-1) th boosted voltage, a (K + 1) th capacitive element (capacitor C3) is generated by generating a Kth boosted voltage by further boosting the (K-1) th boosted voltage. And a booster circuit (boost circuit 100a) that generates an Nth boosted voltage from one end (output terminal OUT) of the Nth capacitor element, and includes at least one capacitor among the N capacitor elements. The elements (capacitance elements C0 and C1) are formed by other capacitance elements (capacitance elements C2 and C3). Is formed by the first chip second chip different from the (semiconductor chip CHIP2) (semiconductor chip CHIP1), first and second chips are boosting circuit, characterized in that it is laminated together.

  According to the present invention, since a circuit that generates a high voltage, such as a Cockcroft-Walton circuit, can be formed on a plurality of semiconductor chips of at least two chips, the chip size of the semiconductor chip on which the booster circuit is mounted There is an effect that can be reduced.

Further, one end of the capacitor elements of the lower layer chip (semiconductor chip CHIP1) in the first and second chips to be stacked is connected to the capacitor elements (capacitance elements C2 and C3) of the upper layer chip (semiconductor chip CHIP2). Capacitance elements (capacitance elements C0 and C1) are connected to the top first contact (contacts CT131 and CT141) in the chip. In addition, among the capacitive elements of the upper layer chip (semiconductor chip CHIP2), the capacitive element having one end connected to the capacitive element of the lower layer chip is connected to the lowermost second contact (contacts CT11 and CT21) in the chip. The The first contact (contacts CT131 and CT141) and the second contact (contacts CT11 and CT21) are connected.
Further, as described above, since the first contact and the second contact are located at the same position in plan view from above the chip, the booster circuit 100 is configured simply by aligning the bump electrodes and stacking them. can do. That is, since the booster circuit 100 can be configured by simply connecting the output terminal of the lower layer chip and the input terminal of the upper layer chip using the through electrode and the bump electrode, the first semiconductor chip CHIP1 and the second semiconductor chip CHIP2 Can be chips having the same structure. As a result, it is possible to share the manufacturing process for forming the first semiconductor chip and the second semiconductor chip, and the manufacturing cost of the booster circuit 100 can be reduced. 1 and 2 described above is a power supply unit configured using a semiconductor device, and is not limited to the semiconductor device, and can be used for various purposes as a general power supply.

Next, another embodiment of the present invention will be described.
3 and 4 are a logic circuit and a cross-sectional view, respectively, of a booster circuit 100a according to another embodiment of the present invention. Since FIG. 3 corresponds to FIG. 1 and FIG. 4 corresponds to FIG. 2, the same reference numerals are given to the same parts, and the description thereof is omitted.
3 is different from FIG. 1 in that the boosted voltage SVT output from the node 3B of the second semiconductor chip CHIP2 is converted into the internal circuit A1 in the first semiconductor chip CHIP1 and the internal circuit of the second semiconductor chip CHIP2. The point is that it is supplied to A2. FIG. 4 shows an embodiment in which the logic circuit shown in FIG. 3 is realized on a semiconductor substrate. In order to supply the boosted voltage SVT to the internal circuit A1 in the first semiconductor chip CHIP1 and the internal circuit A2 in the second semiconductor chip CHIP2, as shown in FIG. 4, the connection wire (wiring LNSV) is secondly connected. This can be realized by providing on the semiconductor chip CHIP2.

The boosted voltage SVT is short-circuited when, for example, the first and second semiconductor chips are semiconductor memory devices and have an electrical fuse for a redundant relief circuit (internal circuit) for a defective memory cell. Therefore, it can be used as a boosted voltage SVT. Note that the electric fuse may be an antifuse that electrically connects nodes constituting the internal circuit or a fuse that electrically disconnects nodes.
In particular, consider a case where an 8 GBit semiconductor memory device is formed by using 8 chips of a semiconductor memory device manufactured through the same manufacturing process having a capacity of 1 GBit using, for example, a through electrode. In this case, if the boosted voltage SVT needs 9V, if an AC voltage having an amplitude of 1V is used, the voltage is ideally boosted by 1V at each chip, and a voltage of 9V is obtained. In order to use the 9V boosted voltage SVT as a voltage used for programming the fuse in each chip, for example, as shown in FIG. 4, it is necessary to adopt a structure that can be supplied from the uppermost chip to each chip. In FIG. 4, the semiconductor chip CHIP2 is the uppermost chip.

The boosted voltage SVT is taken from the bump electrode BP42 of the semiconductor chip CHIP2. The bump electrode BP42 is connected to the bump electrode BPSV22 via the wiring LNSV.
The bump electrode BPSV22 is connected to the internal circuit A2 via the through electrode PESV22, the contact CT171, and the wiring LN171. The internal circuit A2 is a circuit that uses the boosted voltage SVT. The internal circuit A2 is, for example, a fuse program circuit that includes an antifuse and holds information of 0 or 1 in a nonvolatile manner by supplying a boosted voltage and cutting the fuse.
The contact CT171 is connected to the bump electrode BPSV12 on the back surface of the semiconductor chip CHIP2 through the through electrode PESV12. The bump electrode BPSV12 is connected to the bump electrode BPSV21 of the semiconductor chip CHIP1. The bump electrode BPSV21 is connected to the internal circuit A1 through the through electrode PESV21, the contact CT171, and the wiring LN171. The internal circuit A1 is a circuit having the same configuration as the internal circuit A2, and is programmed individually with the internal circuit A2 using the boosted voltage SVT. Further, the contact CT171 of the semiconductor chip CHIP1 is connected to the bump electrode BPSV11 on the back surface of the semiconductor chip CHIP1 through the through electrode PESV11.

  With such a configuration, the booster circuit 100a supplies the boosted voltage SVT generated in the uppermost semiconductor chip to each chip constituting the booster circuit, and the internal circuit of each chip using the boosted voltage SVT. Can be supplied to.

Next, a modified example of the arrangement of rectifying elements in each semiconductor chip will be described.
FIG. 5 is a logic circuit diagram of a capacitor element and a rectifier element in one chip when the booster circuit 100b of the present invention is dispersed in a semiconductor chip. FIG. 1 discloses the configuration of two capacitor elements and two rectifier elements (diodes) or one capacitor element and one rectifier element (diode) in one semiconductor chip. In FIG. 5, two capacitor elements and three rectifier elements (diodes) are configured in one semiconductor chip CHIP1A. Since the capacitive element has the same configuration as that shown in FIG. 1, the same reference numerals are given and description thereof is omitted. In FIG. 5, the rectifier elements are a diode DA, a diode DB, and a diode DC. Here, the size ratio indicating the current drive capability of the diode DA, the diode DB, and the diode DC (the larger the current supply capability, the higher the current supply capability) is 0.5: 1: 0.5. By combining the semiconductor chip CHIP1A shown in FIG. 5 with the upper chip and the lower chip, the diode DA is connected in parallel with the diode DC of the lower chip, and the diode DC is connected in parallel with the diode DA of the upper chip. The same size is realized.

A power supply system incorporating the booster circuit 100 described above will be described below with reference to FIG. As shown in FIG. 6, the power supply system includes a power generation unit 61, a booster circuit 100, an operation circuit 63, and a controller 64 arranged on the substrate S0. The booster circuit 100 is mounted on the substrate S0 via the solder balls SB65 to SB68 and the substrate S2. The operation circuit 63 is mounted on the substrate S0 via the solder balls SB69 to SB71 and the substrate S3. The controller 64 is mounted on the substrate S0 via the solder ball SB72 and the substrate S4.
The booster circuit 100 is configured to boost the AC voltage received from the power supply generation unit 61 and supply the boosted voltage SVT to the operation circuit 63.

  In FIG. 6, a power generation unit 61 converts AC power input from an AC power source and boosts the AC voltage from the solder balls SB61 and SB62 via the wiring L61 and the wiring L62 on the substrate S0, respectively. Supply to circuit 100. Further, the power generation unit 61 converts an AC voltage into a DC voltage by an internal AC-DC converter (AD converter 61a), and converts the DC voltage to the boost circuit 100 and the operation via the solder ball SB63 and the wiring L63. Supply to circuit 63. The booster circuit 100 and the operation circuit 63 are supplied with a DC voltage from the solder ball SB67 and the solder ball SB69, respectively, and operate.

The booster circuit 100 is configured by stacking semiconductor chips CHIP1 to CHIPn, boosts the AC voltage input from the solder balls SB65 and SB66, and outputs the boosted voltage SVT to the wiring L64 via the solder balls SB68. To do.
The operation circuit 63 receives the boosted voltage SVT from the solder ball SB70 to which the wiring L64 is connected, and is used for the operation of the internal circuit. The controller 64 outputs a control signal to the operation circuit 63 via the solder ball SB72, the wiring L65, and the solder ball SB71, and uses the boosted voltage SVT in the internal circuit according to the operation mode of the operation circuit 63. Is allowed or prohibited.
Here, the operation circuit 63 is, for example, a flash memory that uses a DC high voltage for the erase operation of the memory cell. The internal circuit is a drive circuit that drives, for example, a P-type well region in which a memory cell using the boosted voltage SVT is formed to a high voltage. As long as the boosted voltage SVT is used, the semiconductor device is not limited to a semiconductor device such as a flash memory, and may be a device using a high voltage other than the semiconductor device.

100, 100a, 100b ... booster circuit,
CHIP1, CHIP2, CHIP1A ... Semiconductor chip,
C, C0, C1, C2, C3 ... capacitive elements,
D, D0, D1, D2, D3, DA, DB, DC ... diode,
Ts ... AC generator,
A, B, 1A, 1B, 1C, 1D, 2A, 2B, 2C, 2D, 3A, 3B, LA, LB ... node, OUT ... output terminal,
BP11, BP31, BP12, BP32, BP21, BP41, BP22, BP42, BPSS11, BPSS21, BPSS12, BPSS22, BPSV11, BPSV21, BPSV12, BPSV22 ... bump electrodes,
PE11, PE31, PE12, PE32, PE21, PE41, PE22, PE42, PESS11, PESS21, PESS12, PESS22, PESV11, PESV21, PESV12, PESV22...
CT11, CT21, CT31, CT41, CT51, CT61, CT71, CT81, CT91, CT101, CT111, CT121, CT131, CT141, CT151, CT161, CT171 ... contact,
LN11, LN21, LN31, LN41, LN51, LNSV, LN171, L61, L62, L63, L64, L65 ... wiring,
GP51, GP121 ... gate electrode,
ND31, ND41, ND71, ND91, ND101, ND111 ... N-type diffusion layer,
PD61, PD81, PD151 ... P-type diffusion layer, PSUB ... P-type semiconductor substrate,
SVT: Boosted voltage, A1, A2 ... Internal circuit, 61 ... Power source generator, 63 ... Operation circuit,
64 ... Controller,
SB61, SB62, SB63, SB65, SB66, SB67, SB68, SB69, SB70, SB71, SB72 ... solder balls,
S0, S2, S3, S4 ... Substrate

Claims (13)

N capacitive elements are provided (N is a natural number of 2 or more), and the Kth capacitive element (1 <K <N, K is a natural number) among the N capacitive elements is the (K−1) th capacitive element. The (K-1) th boosted voltage boosted by the capacitor element is received, and the Kth boosted voltage is generated by further boosting the (K-1) th boosted voltage to generate the (K + 1) th And a booster circuit for supplying an Nth boosted voltage from one end of the Nth capacitive element,
Among the N capacitive elements, at least one capacitive element is formed on a second chip different from the first chip on which the other capacitive elements are formed, and the first and second chips are stacked on each other. A booster circuit characterized by the above. Among the capacitor elements of the lower layer chip in the first and second chips to be stacked, the capacitor element having one end connected to the capacitor element of the upper layer chip has one end connected to the uppermost first contact in the lower layer chip Connected to
Among the capacitive elements of the upper layer chip, one end of the capacitive element connected to the lower layer chip capacitive element is connected to the lowermost second contact in the upper layer chip,
2. The booster circuit according to claim 1, wherein the first contact and the second contact are connected.   The first and second chips are chips having the same configuration, wherein the first contact and the second contact are located at the same position in plan view from above the chip. The booster circuit according to claim 2.   4. The booster circuit according to claim 3, wherein the Nth boosted voltage is supplied to internal circuits having the same configuration in the first and second chips, respectively. Each of the booster circuits is composed of a first stage to an Mth stage formed on a first chip to an Mth chip (M is a natural number of 2 or more) from the lowest layer,
The first stage includes:
A first capacitive element connected between a first input terminal to which a first signal is input and a first output terminal;
A second capacitor connected between a second input terminal and a second output terminal to which a signal whose phase is inverted by 180 degrees from the first signal is input;
A first rectifier element connected between the second input end and the first output end;
A second rectifying element connected between the first output end and the second output end;
Consisting of a combination of
The L-th stage (1 <L ≦ M) of the first to M-th stages is:
A (2L-1) th capacitive element connected between its first input terminal connected to the first output terminal of the (L-1) th chip and its first output terminal;
A (2L) th capacitive element connected between its second input terminal connected to the second output terminal of the (L-1) th chip and its second output terminal;
A (2L-1) th rectifying element connected between the second input end of the device and the first output end of the device;
A (2L) th rectifying element connected between the first output terminal of the self and the second output terminal of the self;
Consisting of a combination of
2. The booster circuit according to claim 1, wherein the booster voltage is output from a second output terminal of the Mth chip. Each of the booster circuits is composed of a first stage to an Mth stage formed on a first chip to an Mth chip (M is a natural number of 2 or more) from the lowest layer,
The first stage includes:
A first capacitive element connected between a first input terminal to which a first signal is input and a first output terminal;
A first rectifier element connected between a second input terminal to which a signal whose phase is inverted by 180 degrees from the first signal is input and the first output terminal;
The second input end and the second output end are directly connected,
The second stage includes:
A second capacitive element connected between its second input terminal connected to the second output terminal of the first chip and its second output terminal;
It is composed of a combination of a first input terminal connected to the first output terminal of the first chip and a second rectifier element connected between the second output terminal of the first chip, The first input terminal of the self and the first output terminal of the self are directly connected,
The L-th stage (2 <L ≦ M) of the first to M-th stages is
If L is odd,
A (L) th capacitive element connected between its first input terminal connected to the first output terminal of the (L-1) th chip and its first output terminal;
A (L) -th rectifying element connected between its second input terminal connected to the second output terminal of the (L-1) -th chip and its own first output terminal;
The own second input end and the second output end of the own are directly connected,
If L is an even number,
A (L) th capacitive element connected between its second input terminal connected to the second output terminal of the (L-1) th chip and its second output terminal;
A (L) -th rectifying element connected between its first input terminal connected to the first output terminal of the (L-1) -th chip and its second output terminal;
The first input terminal and the first output terminal of the self are directly connected,
The boosted voltage is output from a first output terminal of the Mth chip when M is an odd number, and from a second output terminal of the Mth chip when M is an even number. 2. The booster circuit according to 1.   The first input terminal and the first output terminal in each of the first chip to the Mth chip, and the second input terminal and the second output of each of the first chip to the Mth chip. The ends are located at the same position in plan view, the first to Mth chips are stacked, the first output end of the lower layer chip, the first input end of the upper layer chip, the lower layer chip 7. The booster circuit according to claim 5, wherein the second output terminal of the chip and the second input terminal of the upper chip are respectively connected in cascade according to a stacking order.   8. The boosted voltage output from the Mth chip is supplied to the internal circuit having the same configuration in each of the Mth chip from the first chip. The booster circuit according to any one of the above.   9. The booster circuit according to claim 4, wherein the internal circuit includes a fuse element that stores a logic level of 0 or 1 in a nonvolatile manner when the boosted voltage is supplied. . A first chip provided with a first voltage generation circuit that is supplied with a first voltage and generates a second voltage that is greater than the first voltage;
A second voltage generation circuit that is stacked on the first chip, is supplied with the second voltage from the first chip, and generates a third voltage larger than the second voltage; Chips and
The semiconductor device is characterized in that the first and second voltage generating circuits are arranged at equal positions in each chip.   11. The semiconductor device according to claim 10, wherein the first voltage generation circuit and the second voltage generation circuit have the same circuit configuration. The first chip has first and second surfaces, and
A first terminal to which the first voltage is supplied to the first surface;
A second terminal to which the second voltage is supplied to the second surface,
The second chip has third and fourth surfaces, and
A third terminal connected to the second electrode on the third surface;
The semiconductor device according to claim 10, further comprising: a fourth terminal to which the third voltage is supplied to the fourth surface. The first chip includes a first through electrode penetrating the first chip;
The first and second surfaces have fifth and sixth terminals connected to the first through electrode, respectively.
The second chip includes a second through electrode penetrating the second chip;
The seventh and eighth terminals connected to the second through electrode on the third and fourth surfaces, respectively,
The sixth terminal of the first chip is connected to the seventh terminal of the second chip, and the third voltage is supplied to the seventh terminal. 10. The semiconductor device according to 10.

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