JP2015023781A - High-voltage generation device and charged particle beam device using the same - Google Patents
High-voltage generation device and charged particle beam device using the same Download PDFInfo
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本発明は、高電圧発生装置に係り、特に電子顕微鏡やイオン加速装置等の荷電粒子を加速する高電圧発生装置に関する。 The present invention relates to a high voltage generator, and more particularly to a high voltage generator for accelerating charged particles such as an electron microscope and an ion accelerator.
高電圧発生装置は電子線発生装置やイオンビーム発生装置、Ｘ線発生装置に必須の技術である。これらには通常直流高電圧電源を用いるが、直流高電圧を得るための多段倍電圧整流回路としてコッククロフト・ウォルトン回路（以下ＣＷ回路）が広く用いられている。特許文献１には電子顕微鏡のエミッタに高電圧を印加するための高電圧発生装置として、ＣＷ回路を適用した例が示されている。 The high voltage generator is an essential technology for an electron beam generator, an ion beam generator, and an X-ray generator. A DC high voltage power supply is usually used for these, but a Cockcroft-Walton circuit (hereinafter referred to as CW circuit) is widely used as a multistage voltage doubler rectifier circuit for obtaining a DC high voltage. Patent Document 1 shows an example in which a CW circuit is applied as a high voltage generator for applying a high voltage to an emitter of an electron microscope.
ＣＷ回路を用いた高電圧発生装置は、コンデンサやダイオードなどの電子部品の組み合わせによって構成されている。一方、十分な高電圧を発生するためには、各部品間の耐電圧を確保する必要があり、電圧が高ければ高いほど大型化せざるを得ない。絶縁材料を工夫する事によって、小型化することも考えられるが、同一の絶縁材料を用いた場合で比較すると、やはり電圧が高いほど構造が大型化する。 A high voltage generator using a CW circuit is configured by a combination of electronic components such as capacitors and diodes. On the other hand, in order to generate a sufficiently high voltage, it is necessary to ensure a withstand voltage between the components, and the higher the voltage, the larger the size. Although it is conceivable to reduce the size by devising the insulating material, as compared with the case where the same insulating material is used, the higher the voltage, the larger the structure.
耐電圧を保つために大型化すると効率の低下およびリップルの増大を招く。しかし、小型化すると電子部品などを用いた構造では耐電圧が低下してしまい、所望の電圧を得られない場合がある。さらに、大型化した高電圧発生装置を採用した場合に、電位供給箇所へ高電圧ケーブルを用いて電位を供給する。この場合に、ケーブルなどを通じて振動が伝搬し、電子顕微鏡等においては観察像へのノイズ源になる可能性がある。特許文献１には高電圧発生装置の小型化とリップル低下の両立については何ら論じられていない。 When the size is increased to maintain the withstand voltage, the efficiency is lowered and the ripple is increased. However, when the size is reduced, the withstand voltage is lowered in a structure using electronic parts or the like, and a desired voltage may not be obtained. Furthermore, when a large-sized high voltage generator is employed, a potential is supplied to a potential supply location using a high voltage cable. In this case, vibration propagates through a cable or the like, and may become a noise source for an observation image in an electron microscope or the like. Patent Document 1 does not discuss at the same time reducing the size of the high-voltage generator and reducing the ripple.
以下に、装置の小型化と低リップル化の両立を目的とする高電圧発生装置、及びそれを用いた荷電粒子線装置について説明する。 Below, the high voltage generator aiming at coexistence of size reduction and low ripple of an apparatus, and a charged particle beam apparatus using the same are demonstrated.
上記目的を達成するための一態様として、薄膜の積層によって形成されるダイオード、或いはコンデンサの少なくとも一方を含む素子形成層が複数積層されたコッククロフト・ウォルトン回路を有する高電圧発生装置、及び当該高電圧発生装置を備えた荷電粒子線装置を提案する。 As one aspect for achieving the above object, a high voltage generator having a Cockcroft-Walton circuit in which a plurality of element formation layers including at least one of a diode or a capacitor formed by stacking thin films are stacked, and the high voltage A charged particle beam apparatus equipped with a generator is proposed.
上記構成によれば、高い耐電圧性を備えつつ装置の小型化が可能となると共に、低リップル化を実現することが可能となる。 According to the above configuration, the apparatus can be reduced in size while having high voltage resistance, and low ripple can be realized.
ＣＷ回路は、直流高電圧を得るのに好適な回路である。ＣＷ回路の昇圧効率は式１で表すことができる。式１を見ると明らかなように、浮遊容量Ｃｓが大きいほど昇圧効率Ｆは低下する。Ｆは０から１の値をとり、値がより大きければ昇圧効率がより高い。ＣはＣＷ回路のコンデンサ容量でありＮは段数を表す。 The CW circuit is a circuit suitable for obtaining a DC high voltage. The boosting efficiency of the CW circuit can be expressed by Equation 1. As apparent from Equation 1, the boosting efficiency F decreases as the stray capacitance Cs increases. F takes a value from 0 to 1, and the larger the value, the higher the boosting efficiency. C is the capacitor capacity of the CW circuit, and N is the number of stages.
ＦはＣｓに対して単調減少関数であり、Ｃｓは小さい事が望ましい。しかし部品の耐圧の限界からある程度の大型化は必要であり、装置が大型化すれば表面積が増加し、Ｃｓが大きくなり昇圧効率は低下する。また、出力電圧のリップルに目を向けると、リップルＶｓｒは以下の式で表される。 F is a monotonically decreasing function with respect to Cs, and it is desirable that Cs be small. However, it is necessary to increase the size to some extent due to the limit of the pressure resistance of the component. If the device is increased in size, the surface area increases, Cs increases, and the boosting efficiency decreases. When attention is paid to the ripple of the output voltage, the ripple Vsr is expressed by the following equation.
ここでＥはＣＷ回路の入力電圧の振幅である。この式から、リップルも装置が大型化すれば同様に大きくなるとわかる。 Here, E is the amplitude of the input voltage of the CW circuit. From this equation, it can be seen that the ripple will increase as the device becomes larger.
そこで本実施例では、電子部品や樹脂などの通常ｍｍ以上で用いる絶縁材料ではなく、マイクロファブリケーション技術等によって形成されるμｍオーダーの薄膜を用いることによって、上記の相反する課題を解決出来る。スパッタリングなどで作成した薄膜は耐電圧が高く、例としてＳｉ3Ｎ4およびＳｉＯ2の複合膜において、５μｍで１ｋＶ以上の耐電圧がある。１ｍｍ当りに換算すると、２００ｋＶ／ｍｍである。通常ｍｍオーダーで用いる絶縁材料と比較して、膜内部のボイドなどの欠陥が少なく膜の品質が良いため、このような特徴が生まれる。 Therefore, in this embodiment, the above conflicting problems can be solved by using a thin film of μm order formed by a microfabrication technique or the like instead of an insulating material usually used for mm or more such as an electronic component or a resin. A thin film formed by sputtering or the like has a high withstand voltage. For example, a composite film of Si 3 N 4 and SiO 2 has a withstand voltage of 1 kV or more at 5 μm. When converted per 1 mm, it is 200 kV / mm. Compared with an insulating material usually used in the order of mm, such a feature is born because there are few defects such as voids inside the film and the film quality is good.
薄膜を積層することによってコンデンサのような素子を構成し、当該素子が形成された素子形成層が複数積層されたコッククロフト・ウォルトン回路によれば、高電圧発生装置の小型化および低リップル化を行う事が出来る。 According to the Cockcroft-Walton circuit in which elements such as capacitors are formed by laminating thin films and a plurality of element formation layers on which the elements are formed are laminated, the high voltage generator is reduced in size and ripples are reduced. I can do it.
高電圧発生装置は図１に示すように、電力供給ユニット、トランス１次側電流源および制御部、昇圧トランス、ＣＷ回路、フィルター回路、分圧器、フィードバック制御回路から構成される。図の矢印は電圧の出力先又は信号の出力先を示してしるが、この例に限定するものではなく、例えばフィルター回路から分圧器に入力される電圧がそのまま出力せずに再度フィルター回路を通る場合もある。また、例えばフィルター回路を用いないなど、構成要素の一部を省略する場合もある。さらに電力源として商用電源などを用いた場合は、電力源は高電圧発生装置に含まないが、バッテリーなどを用いた場合は電力源も高電圧発生装置に含める。 As shown in FIG. 1, the high voltage generator includes a power supply unit, a transformer primary current source and control unit, a step-up transformer, a CW circuit, a filter circuit, a voltage divider, and a feedback control circuit. The arrows in the figure indicate the voltage output destination or the signal output destination. However, the present invention is not limited to this example. For example, the voltage input from the filter circuit to the voltage divider is not output as it is, and the filter circuit is connected again. Sometimes it passes. Further, some components may be omitted, for example, a filter circuit is not used. Further, when a commercial power source or the like is used as a power source, the power source is not included in the high voltage generator, but when a battery or the like is used, the power source is also included in the high voltage generator.
これらの構成要素の全て又は一部をマイクロファブリケーション技術によって製作する事が考えられるが、ここでは一例として主に高電圧部分となるＣＷ回路、フィルター回路、分圧器を、マイクロファブリケーション技術を用いて製作した場合を述べる。 It is conceivable that all or some of these components are manufactured by microfabrication technology, but here, as an example, CW circuits, filter circuits, and voltage dividers that are mainly high-voltage parts are used using microfabrication technology. The case where it was manufactured is described.
ＣＷ回路をマイクロファブリケーション技術で製作する場合、市販の電子部品又はそれに類する部品を組み合わせるのではなく、積層構造で製作を行う。ここで先に述べた理由により浮遊容量を低減する事によって昇圧効率を高く保てるので、例えば１段あたり１．２ｋＶで３０ｋＶ出力するとして、約３０段のＣＷ回路で実現出来る。このときＣＷ回路に必要なダイオードも半導体製造技術を応用してμｍオーダーの大きさで積層構造により製作する。 When a CW circuit is manufactured by a microfabrication technique, a commercially available electronic component or a similar component is not combined, but a stacked structure is used. Since the boosting efficiency can be kept high by reducing the stray capacitance for the reason described above, it can be realized with about 30 stages of CW circuits, assuming that 30 kV is output at 1.2 kV per stage. At this time, a diode necessary for the CW circuit is also manufactured by a laminated structure with a size of μm order by applying semiconductor manufacturing technology.
図２は、薄膜を積層することによって形成したダイオード素子形成層の一例を示す図である。Ｓｉ基板２００上に化学蒸着（以下ＣＶＤ）によって絶縁膜２０１（例えば窒化ケイ素）を形成する。次に、スパッタによってメタル層２０２を形成し、スパッタ又はＣＶＤにて誘電体層２０３を形成、そして再度メタル層２０２を形成することによってコンデンサを作る事が出来る。 FIG. 2 is a diagram showing an example of a diode element formation layer formed by laminating thin films. An insulating film 201 (for example, silicon nitride) is formed on the Si substrate 200 by chemical vapor deposition (hereinafter referred to as CVD). Next, a metal layer 202 can be formed by sputtering, a dielectric layer 203 can be formed by sputtering or CVD, and a metal layer 202 can be formed again to form a capacitor.
次にＳｉ単結晶層を例えばスパッタとレーザーアニールによって形成し、イオン注入などによってｐｎ接合を作成しダイオード層を作成する。 Next, a Si single crystal layer is formed by sputtering and laser annealing, for example, and a pn junction is formed by ion implantation or the like to form a diode layer.
このような作成工程を繰り返すことによって、コンデンサとダイオードの形成層を繰り返し積層し、図４に例示するような適正な配線を施すことによって、ＣＷ回路を構成する。 By repeating such a production process, a capacitor and a diode formation layer are repeatedly laminated, and an appropriate wiring as illustrated in FIG. 4 is applied to constitute a CW circuit.
また、層製作時にパターン形成も行う事によって、コンデンサとダイオードを導電体によって接続し、さらに上記層製作を繰り返し組み合せる事によって、例えば図３に示す３段のＣＷ回路を図４に例示するように層構造にて製作する事が出来る。 Further, by forming a pattern at the time of layer fabrication, a capacitor and a diode are connected by a conductor, and the above layer fabrication is repeatedly combined, for example, a three-stage CW circuit shown in FIG. 3 is illustrated in FIG. It can be manufactured with a layer structure.
図３において、２０４は出力部であり、２０５は昇圧トランスの２次側である。破線２０６で囲まれた回路を積層構造にて製作する。ここではコンデンサ層２０７、ダイオード層２０８の繰り返しとして例示してあるが、配線層を適宜組み込む事も考えられる。また、ここではＣＷ回路の基本形を示しているが、対称型ＣＷ回路などの派生形も積層構造にて同様に製作可能である。 In FIG. 3, reference numeral 204 denotes an output unit, and 205 denotes a secondary side of the step-up transformer. A circuit surrounded by a broken line 206 is manufactured in a laminated structure. In this example, the capacitor layer 207 and the diode layer 208 are repeated, but a wiring layer may be appropriately incorporated. Although the basic form of the CW circuit is shown here, a derivative form such as a symmetric CW circuit can be similarly manufactured in a laminated structure.
図７は、ＣＷ回路のコンデンサ部と配線部が含まれる層の具体的な製造プロセスを示す図である。（１）先ず、基板２２３上に絶縁層２２２を積み上げ、マスク２２１を施す。（２）次に、エッチングにより絶縁層の一部を除去する。（３）絶縁層の除去部分に、コンデンサ電極となる金属層２２４を積み上げる。（４）金属層２２４上に高誘電体層２２６を積み上げ、次にコンデンサ電極層２２５を積み上げる。（５）次に、マスク２２１を除去するように、平坦化を行うことによって、コンデンサ電極層２２５上部を最上面とする。（６）次に配線部となる部分を非マスク部としたマスク２２７を施す。（７）マスク２２７の非マスク部のエッチングによりコンタクト形成用の穴をあける。（８）前ステップで形成された穴にコンタクト２２８を埋め込み、平坦化を行う。（９）平坦化処理の後、絶縁層２２９を積み上げる。（１０）絶縁層２２９の配線部を形成する部分を非マスク部とするマスク２３０を施す。（１１）エッチングによりコンタクト形成用の穴２３１をあける。（１２）コンタクト２３２を埋め込み、平坦化を行う。 FIG. 7 is a diagram showing a specific manufacturing process of the layer including the capacitor portion and the wiring portion of the CW circuit. (1) First, the insulating layer 222 is stacked on the substrate 223 and the mask 221 is applied. (2) Next, a part of the insulating layer is removed by etching. (3) A metal layer 224 to be a capacitor electrode is stacked on the removed portion of the insulating layer. (4) The high dielectric layer 226 is stacked on the metal layer 224, and then the capacitor electrode layer 225 is stacked. (5) Next, planarization is performed so that the mask 221 is removed, so that the upper part of the capacitor electrode layer 225 is the top surface. (6) Next, a mask 227 is applied with the portion to be a wiring portion as a non-mask portion. (7) A contact formation hole is formed by etching the non-mask portion of the mask 227. (8) The contact 228 is embedded in the hole formed in the previous step and flattened. (9) After the planarization process, the insulating layer 229 is stacked. (10) A mask 230 is formed with a portion of the insulating layer 229 where the wiring portion is to be formed as a non-mask portion. (11) A contact forming hole 231 is formed by etching. (12) The contact 232 is buried and flattened.
以上のプロセスによりコンタクトを形成し、コンデンサ部とダイオード部２３３を接続することによって、図８のようなＣＷ回路を形成する。図８はコンデンサ、ダイオード、及び配線部となる回路層が複数積層されたＣＷ回路の具体的な構成を示す図である。このようなＣＷ回路は、図７に例示したような加工工程と、ダイオード部２３３の形成工程を繰り返すことによって形成される。図８（ａ）はＣＷ回路の全体図、図８（ｂ）はＣＷ回路の一部８０１の回路図、図８（ｃ）はＣＷ回路の一部８０１の拡大図である。図８（ｂ）（ｃ）を比較するとわかるように、図７に例示した加工工程と、ダイオード部２３３の形成工程の繰り返しによって、ＣＷ回路に必要なダイオード部２３３、コンデンサ部８０２、８０３、コンデンサ部８０２、８０３、ダイオード部２３３間の接続、及び層間の接続を行うための配線部８０４，８０５を形成することが可能となる。ダイオード部２２３が含まれる層には、離間した２つのコンデンサ電極と、ダイオード部の一端を接続する金属層が形成される。 A contact is formed by the above process, and the capacitor portion and the diode portion 233 are connected to form a CW circuit as shown in FIG. FIG. 8 is a diagram showing a specific configuration of a CW circuit in which a plurality of circuit layers serving as capacitors, diodes, and wiring portions are stacked. Such a CW circuit is formed by repeating the processing step illustrated in FIG. 7 and the formation step of the diode portion 233. 8A is an overall view of the CW circuit, FIG. 8B is a circuit diagram of a part 801 of the CW circuit, and FIG. 8C is an enlarged view of a part 801 of the CW circuit. As can be seen by comparing FIGS. 8B and 8C, the diode part 233, the capacitor parts 802 and 803, and the capacitor required for the CW circuit are obtained by repeating the processing step illustrated in FIG. 7 and the formation process of the diode part 233. Wiring portions 804 and 805 for connecting the portions 802 and 803 and the diode portion 233 and connecting the layers can be formed. In the layer including the diode part 223, two separated capacitor electrodes and a metal layer connecting one end of the diode part are formed.
図９は、ＣＷ回路を構成する複数層の位置関係をより詳細に説明するための図である。本実施例のＣＷ回路は、第１の金属層、誘電体層、及び第２の金属層からなるコンデンサ部と、第１の配線部を有する第１の層、第１の層上に積層された第２の絶縁層であって、第１の配線部に接続されると共に第２の絶縁層を貫通する第２の配線部、及び第１の層の第２の金属層に接続されると共に第２の絶縁層を貫通する第３の配線部を有する第２の層、及び第２の層に積層されるダイオード部、当該ダイオード部の一端と第２の配線部を接続する第４の配線部、及び前記ダイオード部の他端と前記第３の配線部を接続する第５の配線部を有する第３の層とを含んでいる。このような３つの層が積層された積層層を複数積層することによって、コッククロフト・ウォルトン回路が形成される。 FIG. 9 is a diagram for explaining the positional relationship of a plurality of layers constituting the CW circuit in more detail. The CW circuit of the present embodiment is laminated on the capacitor layer composed of the first metal layer, the dielectric layer, and the second metal layer, the first layer having the first wiring portion, and the first layer. A second insulating layer connected to the first wiring portion and connected to the second wiring portion penetrating the second insulating layer and the second metal layer of the first layer. A second layer having a third wiring portion penetrating the second insulating layer, a diode portion stacked on the second layer, and a fourth wiring connecting one end of the diode portion and the second wiring portion And a third layer having a fifth wiring portion connecting the other end of the diode portion and the third wiring portion. A Cockcroft-Walton circuit is formed by laminating a plurality of laminated layers in which such three layers are laminated.
また、３つの層を積層した積層層間には絶縁層（第３の絶縁層）が配置されている。第３の絶縁層には、離間した２つのコンデンサ電極と、ダイオードの一端を接続するための電極（第６の配線部、第７の配線部）が形成されている。 In addition, an insulating layer (third insulating layer) is disposed between the three stacked layers. The third insulating layer is formed with two capacitor electrodes spaced apart and electrodes (sixth wiring portion and seventh wiring portion) for connecting one end of the diode.
上記のようなＣＷ回路によれば、高電圧発生装置の小型化および低リップル化の実現が可能となる。 According to the CW circuit as described above, it is possible to reduce the size and ripple of the high voltage generator.
また、上記の積層ＣＷ回路を同一基板上に１回路だけではなく複数回路製作し、その一部又は全てを並列接続として使用する事も出来る。並列接続とする利点として単独使用の場合と比較して電流の最大出力値を高くする事が出来る。 Further, not only one circuit but also a plurality of the above-mentioned laminated CW circuits can be manufactured on the same substrate, and a part or all of them can be used as a parallel connection. As an advantage of parallel connection, the maximum output value of current can be increased compared to the case of single use.
なお、ここでは元になるＳｉなどの基板面に対して垂直方向にＣＷ回路を形成していく方法を述べたが、それに限定するわけではなく、基板面に対して水平方向に回路を形成していく事も出来る。 Here, the method of forming the CW circuit in the direction perpendicular to the base substrate surface such as Si has been described. However, the present invention is not limited to this, and the circuit is formed in the horizontal direction with respect to the substrate surface. You can also go.
次に、走査電子顕微鏡（ＳＥＭ）について、高電圧発生装置をＳＥＭとは離間した位置に配置した例と、上述のような手法により形成されたＣＷ回路を含む高電圧発生装置をＳＥＭ上に配置した例を説明する。図５に例示するＳＥＭは電子ビームを加速するための加速電源（高電圧発生装置３０１）を、ＳＥＭ本体３１１から離間した位置に配置すると共に、加速電圧を、高電圧ケーブル３００を介して印加する例を示している。 Next, regarding the scanning electron microscope (SEM), an example in which the high voltage generator is arranged at a position separated from the SEM and the high voltage generator including the CW circuit formed by the above-described method are arranged on the SEM. An example will be described. In the SEM illustrated in FIG. 5, an acceleration power source (high voltage generator 301) for accelerating an electron beam is disposed at a position separated from the SEM body 311, and an acceleration voltage is applied via the high voltage cable 300. An example is shown.
ＣＷ回路を含む高電圧発生装置３０１は、加速管３０４に電子源３０２からウェーネルト電極３０３によって引き出された電子ビーム３０５を加速させる加速筒３０４の加速電圧として、当該加速筒３０４に印加される。電子ビーム３０５は、コンデンサレンズ３０６によって収束され、走査偏向器３０７によって走査されて、試料３０９に到達する。試料３０９に到達する電子ビーム３０５は対物レンズ３０８によって集束された上で試料３０９に照射される。試料３０９から放出された電子等は、検出器３１０によって捕捉され、図示しない画像形成装置によって画像化される。 The high voltage generator 301 including a CW circuit is applied to the acceleration cylinder 304 as an acceleration voltage of the acceleration cylinder 304 that accelerates the electron beam 305 extracted from the electron source 302 to the acceleration tube 304 by the Wehnelt electrode 303. The electron beam 305 is converged by the condenser lens 306, scanned by the scanning deflector 307, and reaches the sample 309. The electron beam 305 that reaches the sample 309 is focused by the objective lens 308 and then irradiated on the sample 309. Electrons and the like emitted from the sample 309 are captured by the detector 310 and imaged by an image forming apparatus (not shown).
上述のような形成法を採用しないＣＷ回路を含む高電圧発生装置３０１は電子光学系のカラム同じオーダーの大きさとなる。そのためカラムと分離したユニットとなり、高電圧ケーブル３００を用いて電位をカラムに供給しなければならない。 The high voltage generator 301 including the CW circuit that does not employ the formation method as described above has the same size as the column of the electron optical system. Therefore, the unit is separated from the column, and the potential must be supplied to the column using the high voltage cable 300.
一方、図２に例示するような薄膜多層構造型の素子層を含むＣＷ回路を含む高電圧発生装置を備えたＳＥＭを図６に例示する。ＣＷ回路の小型化が可能な事に加えて、浮遊容量の低減によってＣＷ回路の多段化が可能となり、１段当りの電圧が低くなるので、昇圧トランスを小型化することによって、昇圧トランス３１４、ＣＷ回路部３１５、フィルター回路３１２、及び分圧器３１５を、カラムに比較して十分小さい大きさにてカラム上部に実装可能となる。電力供給ユニット３１８、トランス１次側電流源および制御部３１７、及びフィードバック回路３１６はカラムと一体化していないものの、ケーブルは高電圧ケーブル３００のかわりに信号ケーブル３１９を用いる事が出来る。 On the other hand, FIG. 6 illustrates an SEM provided with a high voltage generator including a CW circuit including a thin film multilayer structure type element layer as illustrated in FIG. In addition to being able to reduce the size of the CW circuit, it is possible to increase the number of stages of the CW circuit by reducing the stray capacitance, and the voltage per stage is reduced. The CW circuit unit 315, the filter circuit 312 and the voltage divider 315 can be mounted on the top of the column with a sufficiently small size compared to the column. Although the power supply unit 318, the transformer primary side current source and control unit 317, and the feedback circuit 316 are not integrated with the column, the signal cable 319 can be used instead of the high voltage cable 300.
上記高電圧発生装置は、ＳＥＭ以外に、透過型電子顕微鏡（ＴＥＭ）、或いは試料にイオンビームを照射するイオンビーム照射装置のような他の荷電粒子線装置への適用が可能である。 In addition to the SEM, the high voltage generator can be applied to other charged particle beam devices such as a transmission electron microscope (TEM) or an ion beam irradiation device that irradiates a sample with an ion beam.
２０１ 絶縁膜
２０２ メタル層
２０３ 誘電体層
２０４ 出力部
２０５ 昇圧トランスの２次側
２０７ コンデンサ層
２０８ ダイオード層
201 Insulating film 202 Metal layer 203 Dielectric layer 204 Output unit 205 Secondary side 207 of step-up transformer Capacitor layer 208 Diode layer
Claims (7)
薄膜の積層によって形成されるダイオード、或いはコンデンサの少なくとも一方を含む素子形成層が複数積層されたコッククロフト・ウォルトン回路を有することを特徴とする高電圧発生装置。 In a high voltage generator having a Cockcroft-Walton circuit consisting of a diode and a capacitor,
A high voltage generator comprising a Cockcroft-Walton circuit in which a plurality of element forming layers including at least one of a diode or a capacitor formed by stacking thin films are stacked.
前記コンデンサが形成された素子形成層には、誘電体となる薄膜を挟むように導電性の薄膜が形成されていることを特徴とする高電圧発生装置。 In claim 1,
A high-voltage generator, wherein a conductive thin film is formed on an element forming layer on which the capacitor is formed so as to sandwich a thin film serving as a dielectric.
前記ダイオードが形成された素子形成層には、ｐｎ接合層となる薄膜が形成されていることを特徴とする高電圧発生装置。 In claim 1,
A high voltage generating device, wherein a thin film to be a pn junction layer is formed in an element forming layer in which the diode is formed.
誘電体となる薄膜を挟むように導電性の薄膜が形成されている第１の素子形成層と、ｐｎ接合層となる薄膜が形成された第２の素子形成層を有し、当該第１の素子形成層と第２の素子形成層は交互に積層されていることを特徴とする高電圧発生装置。 In claim 1,
A first element formation layer on which a conductive thin film is formed so as to sandwich a thin film that becomes a dielectric, and a second element formation layer on which a thin film that becomes a pn junction layer is formed. The high-voltage generator is characterized in that the element formation layers and the second element formation layers are alternately stacked.
前記薄膜はスパッタリングによって形成されることを特徴とする高電圧発生装置。 In claim 1,
The high voltage generator according to claim 1, wherein the thin film is formed by sputtering.
前記加速電源は、薄膜の積層によって形成されるダイオード、或いはコンデンサの少なくとも一方を含む素子形成層が複数積層されたコッククロフト・ウォルトン回路を含むことを特徴とする荷電粒子線装置。 In a charged particle beam apparatus equipped with an acceleration power source for accelerating a beam emitted from a charged particle source,
The acceleration power source includes a Cockcroft-Walton circuit in which a plurality of element formation layers including at least one of a diode or a capacitor formed by stacking thin films are stacked.
当該第１の層上に積層された第２の絶縁層であって、前記第１の配線部に接続されると共に前記第２の絶縁層を貫通する第２の配線部、及び第１の層の第２の金属層に接続されると共に前記第２の絶縁層を貫通する第３の配線部を有する第２の層と、
当該第２の層に積層されるダイオード部、当該ダイオード部の一端と前記第２の配線部を接続する第４の配線部、及び前記ダイオード部の他端と前記第３の配線部を接続する第５の配線部を有する第３の層とを含み、
当該第１の層、第２の層、第３の層から構成される積層部が、第３の絶縁層を介して複数積層され、当該第３の絶縁層は、前記１の積層部の第４の配線部と他の積層部の第１の金属層を接続する第６の配線部と、前記１の積層部の第５の配線部と前記他の積層部の第１の配線部を接続する第７の配線部を有することを特徴とするコッククロフト・ウォルトン回路。 A capacitor portion that is laminated in the order of the first metal layer, the dielectric layer, and the second metal layer in the removed region from which a part of the first insulating layer is removed, and a portion other than the removed region of the first insulating layer A first layer having a first wiring portion penetrating the first insulating layer;
A second insulating layer stacked on the first layer, connected to the first wiring portion and penetrating through the second insulating layer; and a first layer A second layer connected to the second metal layer and having a third wiring portion penetrating the second insulating layer;
The diode portion stacked on the second layer, the fourth wiring portion connecting one end of the diode portion and the second wiring portion, and the other end of the diode portion and the third wiring portion are connected. And a third layer having a fifth wiring portion,
A plurality of stacked portions each including the first layer, the second layer, and the third layer are stacked with a third insulating layer interposed therebetween, and the third insulating layer is the first stacked portion of the first stacked portion. A fourth wiring portion connecting the first wiring layer and the first metal layer of the other laminated portion, and a fifth wiring portion of the first laminated portion and the first wiring portion of the other laminated portion. A Cockcroft-Walton circuit comprising a seventh wiring portion.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5477577A (en) * | 1977-12-02 | 1979-06-21 | Fuji Electric Co Ltd | Production of composite semiconductor device |
| JPH11261060A (en) * | 1998-03-10 | 1999-09-24 | Fuji Electric Co Ltd | Insulated gate switching element |
| JP2005235468A (en) * | 2004-02-18 | 2005-09-02 | Jeol Ltd | Charged particle beam device and energy correction method of charged particle beam |
| JP2007097760A (en) * | 2005-10-03 | 2007-04-19 | Olympus Medical Systems Corp | Capacitance type ultrasonic vibrator device |
| JP2010104085A (en) * | 2008-10-21 | 2010-05-06 | Shindengen Electric Mfg Co Ltd | High-voltage generation device |
| JP2011181577A (en) * | 2010-02-26 | 2011-09-15 | Elpida Memory Inc | Boosting circuit, and semiconductor device |
-
2013
- 2013-07-24 JP JP2013153173A patent/JP6196831B2/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5477577A (en) * | 1977-12-02 | 1979-06-21 | Fuji Electric Co Ltd | Production of composite semiconductor device |
| JPH11261060A (en) * | 1998-03-10 | 1999-09-24 | Fuji Electric Co Ltd | Insulated gate switching element |
| JP2005235468A (en) * | 2004-02-18 | 2005-09-02 | Jeol Ltd | Charged particle beam device and energy correction method of charged particle beam |
| JP2007097760A (en) * | 2005-10-03 | 2007-04-19 | Olympus Medical Systems Corp | Capacitance type ultrasonic vibrator device |
| JP2010104085A (en) * | 2008-10-21 | 2010-05-06 | Shindengen Electric Mfg Co Ltd | High-voltage generation device |
| JP2011181577A (en) * | 2010-02-26 | 2011-09-15 | Elpida Memory Inc | Boosting circuit, and semiconductor device |
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