TW200305190A - Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding - Google Patents

Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding Download PDF

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Publication number
TW200305190A
TW200305190A TW092103048A TW92103048A TW200305190A TW 200305190 A TW200305190 A TW 200305190A TW 092103048 A TW092103048 A TW 092103048A TW 92103048 A TW92103048 A TW 92103048A TW 200305190 A TW200305190 A TW 200305190A
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Taiwan
Prior art keywords
bonding pad
copper
item
plasma
scope
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TW092103048A
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English (en)
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TWI287243B (en
Inventor
John Leonard Sudijono
Yakub Aliyu
Mei-Sheng Zhou
Simon Chooi
Subhash Gupta
Sudipto Ranengra Roy Subipto
Kwok Keung Paul Paul Ho
Xu Yi
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Chartered Semiconductor Mfg
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Publication of TW200305190A publication Critical patent/TW200305190A/zh
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Publication of TWI287243B publication Critical patent/TWI287243B/zh

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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23GCLEANING OR DE-GREASING OF METALLIC MATERIAL BY CHEMICAL METHODS OTHER THAN ELECTROLYSIS
    • C23G5/00Cleaning or de-greasing metallic material by other methods; Apparatus for cleaning or de-greasing metallic material with organic solvents
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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Description

200305190 五、發明說明(1) (一) 、【發明所屬之技術領域】 m有關於使用於積體電路中接合塾的形成,並 法特別疋有關於一種黏附一鋼線於一鋼接合墊上之改良方 (二) 、【先前技術】 接t墊係電性連接到在半導體晶片結構中的裝置元 i ,且提供晶片暴露的接點區,以容許電性連接到元 口P到晶片,典型地,一接人绩(你丨^〇如、产 人墊二,人 ( )在一端上接合到接 。墊且在另一鳊上接合一部份的導線架(lead 。 紗 1 ϊ ΐ墊可由銅所組成,然而’銅(Cu)接合墊表面的自 然乳化處理會導致形成Cu02,*接 目 銅金屬墊之間造成一個不良的高接點阻值。會在幻線及 f,專利第5, 985, 765號(Hsiao等)揭露一種蝕刻 於一接合墊(BP)上的鈍態保護層開口之製程,一且 = 刻率的蓋層係形成於接合墊上,以當蝕刻熔較 絕緣層中希望的深度時防止其過度截刻。 】在#又厚 美國專利第5, 824, 234號(J0U等)係描述一種移除 在蝕刻製程中的含氟聚合物及金屬氟化物之製程,係‘ 在一接合墊上,以減少接點阻值。 美國專利第5,559,056號(Weiler)描述一種製造接人 ^之方法,其係利用一金屬蓋層覆蓋於接合墊上,該接口合 墊係由兩罩幕及蝕刻步驟所產生,接合墊將禁得起周圚二 度約為2〇(TC,Weilei^g述一覆蓋及排列方法,其係防圍f
第7頁 200305190
:2化層的腐蝕’且阻止在接合墊及接合線間的金屬層間 #保i ^ ί!!第5,719:087號(Chen等)係描述—種製程, 由以入雪:墊免於受到損壞’其係在最後保護層之前藉 二:=料的保護蓋層覆蓋接合塾,該保護層在最 二保遵層中係保護接合墊免於受到適當蝕刻接觸窗的溶 液0 (三)、【發明内容】 因此,本發明之一主要目的,係在於提供一種黏附一 線於一金屬接合墊上之方法,其係減少接觸窗電阻。 再者,本發明之另一目的,係在於提供一種黏附一銅 線於一銅接合墊上之方法,其係在銅線及銅接合墊提 一種較牢固的接觸窗。 又,本發明之又一目的,係在於提供一種黏附一鋼線 於一銅接合墊上之方法,其係提供較佳的可靠性。 其他目的將陳述於後。 其已發現本發明的上述及其他目的可以下列方法完 成,特別地是,在製程室内係提供一種具有暴露金屬接合 墊的半導體晶片結構,該接合墊具有一頂部表面,氫電& 係由一電漿源產生於製程室内,預清洗金屬接合墊,且用 氫電漿鈍化,以移除任何形成在金屬接合墊頂部表面的金 屬氧化物,然後一線接合到鈍化的金屬接合墊上。
第8頁 200305190 五、發明說明(3) " ---- (四)、【實施方式】 因此’第1圖係顯示一積體電路的金屬接合墊丨6,該 積體電路係包括有半導體晶片結構1 0於一反應室内。 曰半導體晶片結構10可被了解的是可能包括有一半導體 晶片或結構、主動及被動元件形成於晶片内、傳導層及介 電層(如複晶層間氧化物(丨P0 )、金屬層間介電質(丨MD )等 等)形成覆蓋於晶片表面上,,,半導·體晶片結構”此詞意指 包括有形成於一半導體晶片上的元件及覆蓋於晶片上的 除 或藉由 金 成,且 藉由隔 路的頂 許電性 在 開,就 的積體 第 的例子 金 在周圍 如,銅 非在別的地方特別指明,所有結構層(等等)可形成 習用技藝中的已知傳統方法所獲致。 屬接合塾16可由鋁(A1)或鋁銅合金(A卜Cu)所組 最好由銅所組成,且接觸到底部電路12,該電路可 f介電層1 4而被覆蓋,鈍態保護層係顯示於積體電 4且穿過已餘刻接觸窗孔洞開口接合塾1 6上,以容 接觸到接合墊1 6。 積體電路製造的最後階段中將接觸窗孔洞3 0蝕刻 像在要將個別的電路晶片切開之前,一晶片由許多 電路所組成。 1圖所不的接合墊結構丨丨,係僅僅為一接合墊結構 ’且並不侷限於此。 合墊16可具有自然氧化層2〇覆蓋於其上,其係 =蜒中藉由金屬接合墊丨6與水蒸汽反應造成的,例 妾合墊16會有Cu〇2層20覆蓋於其上,其在接合製程
200305190 五、發明說明(4) 期間係會在線2 4 (參閱第3圖)及金屬 受歡迎的接觸電阻。 ^塾16之間造成不 如必要的,在非重要的區域( 11,以便使任何損壞減到最小,係由不I罩幕接合墊 率,須^的是對於現在智能的接=進 :第2圖所示,接合墊結構u可被 幕 =,其内係產生有氫電t,本發明的製程最固好各二 -接5工具内,該接合工具係具有—各別的電漿室。 =,第4A圖係顯示-封閉區1〇〇,該封閉區1〇〇係具 m漿工具1〇2及,合工具104 ’ #由轉換機械裝置1〇6而 、 起’其係藉由晶片100(未顯示)在工具1〇2及104 之間轉換,封閉區1 〇係以N2清洗。 第4B圖係說明另一種排列,其中兩工具係在一個裡 面’在雙工具110内(H2電漿工具及接合工具)晶片1〇係牢固 於晶片塊1 0 8上,電漿源11 2與封閉區11 〇 (在此向下電漿) 相接,電漿源1 1 2提供H2電漿1 1 2到封閉區11 〇中,接合工具 功能可為一熱壓或一熱超音波。 氫電漿22係由一電漿源(未顯示)所產生,其可為直接 (如具有RF的平行板)或向下,以便於更進一步的降低損 壞,氫來源可為NH3、H2、N2 + H2、He + H2、或Ar + H2,且氫電 漿係形成於下列的參數之下: 功率:平行板約從50到200瓦;或 向下約從250到700瓦; 時間:約從10到60秒,且最好小於30秒;
第10頁 200305190 五、發明說明(5) h2流(如同所選擇的):約從100到1 000sccm ;
He或N2流(如同所選擇的):約從1〇〇到1〇〇〇3(:(:111 ; NH3流(如同所選擇的)::約從5〇到5〇〇5〇(:111。 第5A圖及第5B圖係說明廣義的感應叙合電漿(icp)钱 刻機結構例子,如第5 A圖所示的,在一第一 ICP蝕刻機内 晶圓1 0係牢固於晶片塊1 〇 8上且接地1 2 〇,半圓的板11 4係 將晶片塊1 0 8隔開,無線電頻率(rF )之交流電流過線圈 112a ’以提供Η?電漿22,如第5B圖所示,在一第二ICP钮刻 機内晶圓10係牢固於晶片塊丨〇8上,部份直角板n 4b係將 晶片塊1 0 8隔開,無線電頻率(RF)之交流電流過線圈 1 1 2 b,以提供H2電漿2 2。 比電毁2 2係預清洗且鈍化金屬接合墊1 6,以移除氧化 層20,純化會使更進一步的金屬接合墊氧化減慢,且以形 成鈍化金屬接合塾16,。 如第3圖所示,當接合墊結構1 1仍在氫電漿環境22内 時’線24會接合到鈍化金屬接合墊16,,因此減少接觸窗 電阻’鈍化金屬接合墊丨6,與線24亦容許一較強接觸窗, 且使得具有較佳的可靠度。 線2 4可藉由一熱壓或熱超音波方法而接合到接合 16,〇 線24可由金(Au)或銅(Cu)銅金所組合而成,且最好係 由銅所組成。 雖然本發明已參考其較佳實施例而被特別地表示並說 月惟熟習本技藝之人士應瞭解地是各種在形式上及細節
200305190 五、發明說明(6) 上的改變可在不背離本發明之精神與範疇下為之。 圖號說明: 10 半導體晶片結構 11 接合墊 12 電路 14 隔離介電層 16 接合墊 16’ 鈍化金屬接合墊 22 H2電漿 24 線 30 接觸窗孔洞 100 封閉區 102 H2電漿工具 104 接合工具 106 轉換機械裝置 10 8 晶片塊 11 4 a 半圓的板 114b部份直角板 1 2 0 接地
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根據本發明黏附一線到一金屬墊上之方法的特徵與優點 由下列配合附圖的說明而更清楚地被瞭解,包括有·” ; 面圖 第1圖到第3圖係概略說明本發明一較佳實施例 廿 。 y之橫剖 第4A圖到第4B圖係概略說明可實施於本發明 例工具配置。 钱乃T的實施 第5Α圖到第5β圖係概略說明可實施於本發》ί威廄私人Φ將、Ak先丨恤. ^ @實 例IC P (感應輕合電聚)餘刻機 施
第13頁

Claims (1)

  1. 200305190
    1 · 一種接合一線到一金屬墊之方法,係包括有步驟· 提供一半導體晶粒結構,其係具有一暴露的金屬接合 墊於一反應室内;該接合墊具有一頂部表面; 口 在該反應室中的一電漿源產生一氫電聚; 以該氫電漿預清洗及鈍化該金屬接合墊,以移除形成 於該金屬接合墊頂部表面上的任何金屬氧化物;及 接合一線到該清洗及純化的金屬接合塾。 2 如申晴專利範圍第1項所述之方法,其中該金屬接人 墊係由選自於Al、Al-Cu、及Cu組成的組群材料中, 且該線係由選自於Au、一銅合金及銅組成的組群材料 中 〇 3 ·如申請專利範圍第1項所述之方法,其中該電漿源係 為直流。 4 ·如申請專利範圍第1項所述之方法,其中該電漿源係 為一具有RF的平行板。 5 ·如申請專利範圍第1項所述之方法,其中該電漿源係 為向下。 6 ·如申請專利範圍第1項所述之方法,其中該氫源係選 自於N H3、H2、N2 + Hz、H e + H2、及A r + H2所組成的組群中 7 ·如申請專利範圍第1項所述之方法,在氫電漿產生之 前尚包括有罩幕該半導體晶粒結構以暴露出該金屬接 合墊之步驟。 8 ·—種接合一銅線到一銅金屬墊之方法,係包括有步驟
    第14頁 200305190
    提供一半導體晶粒結構,其係且有一 入亂认^ ^ ^ ^ f ^ ^ 暴露的銅金屬接 合墊於一反應至内;該銅接合墊且 在該反應室中的一電漿源產生一氫^漿頂"卩面’ 以該氮電衆預清洗及鈍化該銅金屬接合墊,以移除形 成於該銅金屬接合墊頂部表面上的任何銅金屬氧化 物;及 接合一銅線到該鈍化的銅金屬接合塾。 9如申清專利範圍第8項所述之方法,其中該電漿源係 為直流。 1 〇 ·如申請專利範圍第8項所述之方法,其中該電漿源 係為一具有RF的平行板。 1 1 ·如申請專利範圍第8項所述之方法,其中該電漿源 係為向下。 1 2 ·如申請專利範圍第8項所述之方法,其中該氫源係 選自於NH3、H2、N2 + H2、He + H2、及Ar + H2所組成的組群 中。 1 3 ·如申請專利範圍第8項所述之方法,在氫電漿產生 之前尚包括有罩幕該半導體晶粒結構以暴露出該鋼金 屬接合墊之步驟。 1 4 · 一種接合一銅線到一銅金屬墊之方法,係包括有步 驟: 提供一半導體晶粒結構,其係具有一暴露的銅金屬接 合墊於一反應室内;該銅接合墊具有一頂部表面;
    200305190 六、申請專利範圍 在該反應室中的一電漿源產生一氫電漿;該氫源係選 自於NH3、H2、N2 + H2、He + H2、及Ar + H2所組成的組群 中; 以該氫電漿預清洗及鈍化該銅金屬接合墊,以移除形 成於I»玄銅金屬接合塾頂部表面上的任何銅金屬氧化 物;及 法,其中該電漿 接合一銅線到該鈍化的銅金屬接合墊 5 ·如申請專利範圍第1 4項所述之方 源係為直流。 16 17 之方法,其中該電漿 之方法,其中該電漿 •如申請專利範圍第1 4項所述 源係為一具有RF的平行板。 如申睛專利範圍第1 4項所述 源係為向下。
    第16頁
TW092103048A 2002-04-11 2003-02-14 Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding TWI287243B (en)

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