TW199246B - - Google Patents
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- Publication number
- TW199246B TW199246B TW081104947A TW81104947A TW199246B TW 199246 B TW199246 B TW 199246B TW 081104947 A TW081104947 A TW 081104947A TW 81104947 A TW81104947 A TW 81104947A TW 199246 B TW199246 B TW 199246B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- input
- node
- pull
- output
- Prior art date
Links
- 230000000875 corresponding effect Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 5
- 230000002079 cooperative effect Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 102100040678 Programmed cell death protein 1 Human genes 0.000 claims 3
- 101710089372 Programmed cell death protein 1 Proteins 0.000 claims 3
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims 1
- 210000003625 skull Anatomy 0.000 claims 1
- 230000000694 effects Effects 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 240000002834 Paulownia tomentosa Species 0.000 description 1
- 235000010678 Paulownia tomentosa Nutrition 0.000 description 1
- 206010041349 Somnolence Diseases 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/760,414 US5160860A (en) | 1991-09-16 | 1991-09-16 | Input transition responsive CMOS self-boost circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW199246B true TW199246B (esLanguage) | 1993-02-01 |
Family
ID=25059041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW081104947A TW199246B (esLanguage) | 1991-09-16 | 1992-06-23 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5160860A (esLanguage) |
| EP (1) | EP0533332A1 (esLanguage) |
| JP (1) | JPH05291939A (esLanguage) |
| KR (1) | KR930006978A (esLanguage) |
| TW (1) | TW199246B (esLanguage) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3623004B2 (ja) * | 1994-03-30 | 2005-02-23 | 松下電器産業株式会社 | 電圧レベル変換回路 |
| JPH09162713A (ja) * | 1995-12-11 | 1997-06-20 | Mitsubishi Electric Corp | 半導体集積回路 |
| US6104229A (en) * | 1996-05-02 | 2000-08-15 | Integrated Device Technology, Inc. | High voltage tolerable input buffer and method for operating same |
| US5973512A (en) * | 1997-12-02 | 1999-10-26 | National Semiconductor Corporation | CMOS output buffer having load independent slewing |
| US7755939B2 (en) * | 2008-01-15 | 2010-07-13 | Micron Technology, Inc. | System and devices including memory resistant to program disturb and methods of using, making, and operating the same |
| US8750049B2 (en) * | 2010-06-02 | 2014-06-10 | Stmicroelectronics International N.V. | Word line driver for memory |
| JP7580036B2 (ja) * | 2019-05-30 | 2024-11-11 | パナソニックＩｐマネジメント株式会社 | ドライバ回路、及びスイッチシステム |
| WO2021220479A1 (ja) * | 2020-04-30 | 2021-11-04 | 株式会社ソシオネクスト | 入力回路 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3579275A (en) * | 1969-01-07 | 1971-05-18 | North American Rockwell | Isolation circuit for gating devices |
| GB1375958A (en) * | 1972-06-29 | 1974-12-04 | Ibm | Pulse circuit |
| US4381460A (en) * | 1980-05-27 | 1983-04-26 | National Semiconductor Corporation | Bootstrap driver circuit |
| US4692638A (en) * | 1984-07-02 | 1987-09-08 | Texas Instruments Incorporated | CMOS/NMOS decoder and high-level driver circuit |
| US4618786A (en) * | 1984-08-13 | 1986-10-21 | Thomson Components - Mostek Corporation | Precharge circuit for enhancement mode memory circuits |
| JPS61294695A (ja) * | 1985-06-20 | 1986-12-25 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JPH0193927A (ja) * | 1987-10-06 | 1989-04-12 | Fujitsu Ltd | プログラム可能な論理回路 |
| JPH0282713A (ja) * | 1988-09-19 | 1990-03-23 | Fujitsu Ltd | スイッチング補助回路 |
-
1991
- 1991-09-16 US US07/760,414 patent/US5160860A/en not_active Expired - Fee Related
-
1992
- 1992-06-23 TW TW081104947A patent/TW199246B/zh active
- 1992-08-03 EP EP92307061A patent/EP0533332A1/en not_active Ceased
- 1992-09-01 JP JP4233789A patent/JPH05291939A/ja not_active Withdrawn
- 1992-09-09 KR KR1019920016600A patent/KR930006978A/ko not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0533332A1 (en) | 1993-03-24 |
| US5160860A (en) | 1992-11-03 |
| KR930006978A (ko) | 1993-04-22 |
| JPH05291939A (ja) | 1993-11-05 |
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