TH4822B - Cache write delay for small dual-bus computing systems using 80386 and 82385. - Google Patents

Abstract

In a small computer system using 80386/82385, the temporal requirement of 82385 per non-cache memory segment is more limited than the temporal requirement of 80386. The invention currently works with writeable signals (CWE) of 82385 and delay. Those signals in the event of a read failure, the CWE delay, relax the temporal demands on non-cache memory segments and at the same time have no effect on the wait state determinants for non-cache memory. read failure

Claims (3)

1. Improved Multi-Bus Cath 80386/82385 microcomputer system for initiating the delayed written cath state that follows. Read error state To improve the order of the system per section Slower memory assembly The aforementioned microcomputer system contains 80386 processors for executing instructions that are executed. Error reading, each of which was completed in one command cycle. Cath subsystem, including the 82385 cath control, memory cath And the local bus attached to the aforementioned 82385 cath controller, and the aforementioned cath memory with the 80386 main memory tracer associated with the local bus by means of the processor-controlled path system bus. And the Cath subsystem during the Perform read errors each time for moving data from Main memory to the local bus and for data transfer as Say from the local bus that goes to the processor during operation Read each mistake at the time allotted by the processor. The main memory is associated with the local bus by the system bus method, the processor-controlled route, and the cath subsystem during operation. Perform a read error each time for transferring data from Main memory to the local bus and to transfer for From the local bus to the processor during read operations Each time is missed at the time allotted by the telecaster. A logical path in response to the cath write state produced by the aforementioned cath controller during a read-error operation. These units include (a) a path that responds to the read-bus state of the generated system. By controlling such a cath during the error reading operation and in response to the signal that allows the cath to be written from The write-able output of the 82385 Cath-82385 controller is for building on the terminal that allows the signal to be written. Is delayed relative to the signal that makes it possible to write it. The written signal ends before the time. (B) a logical gate with one input associated with the Enables the writings of the aforementioned cath 82385 controls and the second input associated with the said writeable terminal and the channel. The output that is associated with the write-in input of the said cache memory. Writable and concatenated with delayed signals for determining the Can write to the memory of Cath on the input field. Of memory And (c) a buffer path for delaying the signal. Select a chip from the aforementioned 82385. For each such chip select signal And one channel out For each such chip select signal Trajectory outlet That buffer is linked to the chip selection terminal of the unit. Remembering that Cath Signs that allow you to write to the Cath memory And all such chip select signals Effectiveness to initiate a Cath state write state at the allotted time. 2. Microcomputer system consisting of One processor One Cath memory and one Cath control. Connected together by a dedicated bus at And main memory connected With a dedicated bus that passes through the system bus And one path buffer Between the system bus and the local bus The processor executes a command that is executed. Writes and commands with read errors, each completed in one command cycle. The cath controller responds to Prometheus' writing operations. A processor to generate a signal that allows it to be written to memory. Remember to write the information that was identified by the operation. Write to memory the Cath Effective control methods during the The processor to the data is in main memory. In memory To transfer data Desired from the unit Main memory to a dedicated bus that passes through the system bus and buffer path, and to transfer data required from the dedicated bus. That goes to the processor at the interval between read operations Missing the processor defined by the processor. The cath controller responds to the read error. For a signal generator that allows it to be written to memory of the cathode, the signal that ends before the specified time interval and the delay logic responds to the signal that can be written to memory. Remember Kath during each errant reading operation to establish Delay signal for transfer The required information from the bus Only the one that goes to the Cath memory during the read operation is missed. Each such time at one time after the said session. 3. Microcomputer system consisting of A processor for executing program commands including performing read, read, and write operations, each completed. During the execution of one order Cath memory and processor-associated cath control It is a local bus pathway and is responsive to action. Processor read and write to transfer data between Such memory And the processor said when the data That is indicated by read and write operations are stored in or Must be stored in the memory of the said cath Cath-loud control Mention that defines the signal that can be written to the cache memory. Yes, during the writing practice to begin the writing of the verses. The processor's data into memory, the cath. The main memory of the system is associated with the local bus by means of Of one system bus and one interlock between system buses And local bus Pathways for effective transfer during reading operations. Of Trosesser When the data indicated by the read operation is not stored in the said cache memory. That is practice Reading is missed in order to transfer the indicated data from memory. It goes to local bus for both the processor and Cath memory by system bus and interlocking method The processor and its controls, respectively, including The way of timing, execution of the processor's reading and trajectory. The writing timing of effective cath control. During each erroneous reading operation for transfer by lam Extinguishes the identified data from the local bus to the process. Sir, during the operation, the read failed at the specified time. By the processor and for generating signals that can be written down Such memory can be ended before the specified time. Provided when the said information is required for transfer to Also, the processor and its logical path, the unit responds to the signal that it makes to write to the memory. Remember that Cath during the read operation to determine the error. Indicated delay signal for initial data transfer From the aforementioned local bus to the aforementioned cath memory During the reading operation at the time after the specified time (3 clauses, 4 pages, 5 pictures)