SU1675898A2 - Microprocessor system - Google Patents

Abstract

The invention relates to computing and can be used to create computing systems for various purposes. The purpose of the invention is to reduce the program memory capacity when there is a need to loop program sections. The microprocessor system contains microprocessor 1, memory 2, peripheral device 3, second shaper 5 read-write signals containing the element HE 16, the first 17 and the second 18 elements AND , the first shaper 4 signals Read - write, containing the first 19 and second 20 elements AND, the first 21 and second 22 elements OR. In addition, the system contains the first 23, second 24 and third 25 registers, the comparison circuit 26, the shift register 27, the AND 28 element, the OR-NOT 29 element. The essence of the invention is that in the proposed microprocessor system it is possible to jam any portion of the performed the program that is stored in the memory device does not make any changes to this program 1 slug. sl 00 th

Description

The invention relates to computing, can be used to create computing systems for various purposes, and is an improvement of the technical solution by author. St. No. 1172455.

The purpose of the invention is to reduce the capacity of the program memory when there is a need to loop program sections.

The essence of the invention is that in the microprocessor system, it is possible to loop any part of the executed program that is stored in the memory device without making changes to this program.

The drawing shows a block diagram of a microprocessor system.

The microprocessor system contains a microprocessor 1, a storage device 2, a peripheral device 3, the first signal-generating unit 4 Read-write, the second signal-shaping unit 5 Read-write, information input-output 6 of the microprocessor, address output 7 of the microprocessor, control output 8 write to the microprocessor peripheral device, controlling the output 9 of the record to the microprocessor's memory, controlling the output (0 reading from the microprocessor's memory, controlling the output 11 of the microprocessor) From the microprocessor peripheral device, the control inputs of the write 12 and read 13 to (from) the memory device (a) of the microprocessor, the control inputs of the write 14 and read 15 to (from) the peripheral device (a). The second shaper 5 signals Read - write contains the element NOT 16, the first 17 and second 18 elements And, the first shaper 4 signals Read - write contains the first 19 and second 20 elements And, the first 21 and second 22 elements OR. In addition, the system contains the first 23, ator 24, and third 25 registers, the comparison circuit 26, the shift register 27, the AND 28 element, the OR-NOT 29 element, the input 30 sign of the program looping mode, the input 31 specifying the address of the looping program section, information inputs 32-34.

The microprocessor system works as follows. In the presence of a signal Log. At the input 30, the microprocessor 1 executes the program recorded in the wiring device 2. When executing the working program, for various reasons, an abnormal situation may occur. To localize and eliminate it, it is necessary to loop the program on

Claims (1)

the site, the implementation of which leads to an emergency situation. Looping of the program section can be accomplished using a three-byte unconditional branch command. This command returns the processor to rerun the program section, starting at the address specified in the second and third bytes of the command. At the input 32 of the microprocessor system, the code of the unconditional branch command is given, at the inputs 33 and 32, the high and low bytes of the transition address, at input 31, the code of the last address of the looped program section. In the presence of a signal Log. 1 at input 30 of microprocessor system and signal Read memory device at output 10 of microprocessor 1, information from inputs 34, 33 and 32 is written to registers 23, 24 and 25 respectively. When the program is filled, the code set at address output 7 of the microprocessor coincides 1, with the address code which is located at the input 31 of the system, a Log signal appears at the output of the comparison circuit 26. 1, which is on the leading edge of the signal Read is written to the first digit of the register 27, previously set to the zero state (the initial installation circuit is not shown in the drawing), through the OR-NOT 29 element Log.1 signal from the first output of the register 27 prohibits the passage of the signal Reading through the element 18 on the input 13 of the readout of the storage device 2 and allows the issuance of the code of the unconditional transfer command code from the register 23 to the information input-output 6 of the processor 1. The following reading cycles are performed, which are performed by the processors 1 when executing an unconditional jump command, results in a sequential shift of the log. 1 to the second and third bits of the shift register 27, which in turn is accompanied by issuing 6 junior and senior bytes of the transition address from registers 24 and 25 to the information input / output. When issuing information from registers 24 and 25 to the information input / output in the processor 1 signal supply Reading to the read input 13 of the storage device 2 is blocked by a signal from the output of the element OR NOT 29, the claims of the invention. Microprocessor system according to the author. St. Ms 1172455, characterized in that, in order to reduce the memory capacity of programs when there is a need for looping program sections, it additionally contains three registers, a shift register, a comparison circuit, an AND element and an IL-AND-NOT element whose output is connected with the third input of the second element AND the second signal conditioner Read - write, the first to the third inputs of the OR-NOT element are connected respectively to the first to the third outputs of the shift register and the read control inputs from the first to third registers, write inputs which are connected to the output of the element I, the gate input of the comparison circuit and the synchronous input of the shift register, the information input of which is connected to the output of the comparison circuit, the first and second information inputs of which are connected five Here, respectively, to the input of setting the address of the looped section of the system program and to the address output of the microprocessor, which controls the readout output from the storage device of which is connected to the first input of the And element, the second input of which is connected to the input of the looping mode feature of the system section, connected to the information input / output of the microprocessor, the first to the third information inputs of the system are connected to the information inputs from the first to the third registers.