SU980015A1 - Instantaneous value phase meter - Google Patents

Description

The invention relates to phase-measuring technique and can be used in various fields of technology, experimental physics and hydroacoustics to measure the phase difference of continuous sinusoidal signals and the phase difference of the filling signals of radio pulses.

A phase meter is known using a phase shift measurement method < ₀ based on measuring the time interval between the moments of transition of the input voltages through zero values by counting the number of pulses received at the input of the counting unit for a constant measurement time. It contains two pulse shapers, triggers, AND elements, a quantizing pulse generator, a pulse counter, and a frequency divider [ ²⁰ ].

The disadvantages of the phase meter are the impossibility of measuring the phase difference during one signal period (instantaneous phase) and the need to use highly stable generators to generate counting pulses and to form a measurement time interval.

Closest to the proposed principle of operation is a digital phase difference radio signal for one period, containing a measuring trigger, the inputs of which are connected to the outputs of the pulse shapers from the input signals, the pulse train generator and pulse counter, as well as the trigger signal circuit, are included at the shapers input the normalizing amplitudes of the compared radio signals are sharpeners, while one of the pulse shapers is made controlled by the feedback circuit, which includes. second delay elements [2] are connected in series.

980.0

The disadvantages of the known phase meter are the necessity of using a highly stable pulse generator (burst generator) and the inability to measure with this phasometer phase differences of signals whose frequency (period) is not constant. The latter is due to the fact that the known phase meter has a circuit whose temporal characteristics provide a measurement of the phase shift of signals with a frequency of 215 kHz. The transition to measuring the phase shift of signals with a different frequency when using such a phase meter will require changing the frequency of the pulses of the burst generator and changing the duration of the pulses generated by the elements of the phase meter.

The purpose of the invention is the expansion of functionality by 20 providing the ability to measure the phase difference for one period of the signals at a variable frequency of the input signals.

This object is achieved in that the instantaneous values of the phase meter comprising two PFN, generator of pulses, the count pulse generator, a digital readout unit ³⁰ connected in series Tel'nykh first temporal selector and a first pulse counter, entered the first inverting multiplexer coupled to the outputs of the first counter pulses connected after-. Consistently constant register ³⁵ and a second inverting multiplexer soedi-, nennye successively second temporary hydrochloric selector ^1, the second pulse counter and the third inverting multi- 'plexor ^40, the switch, the calculation unit synchronization, connected in series a clock generator, decoder and first Distribution levels converter ⁴⁵ therein, and an element connected in series and controlled inverter codes, decoder codes and second level converter, wherein the outputs of the multiplexers are connected bitwise d ⁵⁰ ug other and are connected to data inputs of the inverter-controlled multiplexer control inputs connected to outputs of the decoder control input digits allocator 55 outputs input control operations which are connected to the inputs of the first level converter and the inputs of the elements

4 ment And, the last input of which is connected to the output of the clock generator, the outputs of the first and second level converters are connected to the control inputs of the switch, the information inputs of which are connected to the control outputs of the computing unit, and the information outputs - with the control inputs of the computing unit, the outputs of the pulse shapers are connected to information inputs of the strobe generator, the first and second control inputs of which are connected respectively to the first and second outputs of the sync block the information outputs of the strobe generator are connected to the control inputs of the first and second time selectors, the information inputs of which are connected to the output of the counter pulse generator, the first and second inputs of the synchronization unit are connected respectively to the second information output of the strobe generator and the last control input of the decoder distributor, the third output of the synchronization unit is connected to the control input of the clock generator, the output of the element And chen to entry controls inverter, digital readout unit connected to the computing unit outputs.

The drawing shows the electrical structural diagram of the device.

The phasometer contains two drivers 1 and 2 pulses, driver 3 strobe pulses, generator 4 counting pulses, a digital reading unit 5 and connected in series with the first time selector 6 and the first counter 7 pulses, the first inverting multiplexer 8 connected to the output of the first counter 7 pulses connected in series a constant register 9 and a second inverting multiplexer 10 connected in series with a second time selector 11, a second pulse counter 12, a third inverting multiplexer 13, a switch 14, computing unit 15 with time division of control signals, synchronization unit 16 with three inputs and three outputs. Serially connected clock generator 17, decoder distributor

9 and a first level converter 19, a multi-input logic element AND 20 and connected in series with a controlled inverter 21 codes, a code decoder 22 and a second level converter 23.

Shapers 1 and 2 are controlled by the input signals U * and the phase meter. They form two sequences of rectangular pulses with a constant amplitude, duty cycle equal to 2, a frequency equal to the frequency of the input signals of the phase meter, and steep edges, the time shift of which is equal to the shift of the moments of transition through the zero value of the input voltage.

Shaper 3 strobe pulses generates two pulses of a rectangular shape. The duration of the first pulse is equal to the duration of the time interval between the moments of transition through the zero value of the input voltage of the phase meter, and the duration of the second period of the input voltage. The leading edges of the two pulses practically ²⁵ coincide in time with the moment of transition through the zero value of the first input voltage U. The operation of the shaper 3 is controlled by the synchronization unit 16. A generator of 4 counting ^m pulses generates pulses with a sufficiently high repetition rate. Digital reading unit 5 provides a reading of the measurement result. The first time selector 6 35 is controlled by the first output pulse of the generator 3 strobe pulses. It passes the pulses of the generator 4 to the input of the counter 7 only during the formation of the first strobe. ⁴⁰

Counter 7 is a binary-decimal pulse counter and provides a count of pulses received at its input through selector 6. Each of its bits works with a code 1-2-4-8. 45 The number of pulses counted by the counter 7 during the action at the control input of the selector 6 of the first output pulse of the strobe pulse generator 3 is proportional to the phase difference of the input voltages of the phase meter.

The first inverting multiplexer 8 is used to alternately connect the output codes of the bits of the counter 7 to the inputs of the inverting time selector. The constant register 9 stores binary codes of the ЗЗО number in its three bits. The purpose of the second time selector 11, the second pulse counter 12 and the third inverting multiplexer 13 i is similar to the purpose of the elements 6 and 8, except that the selector 11 is controlled by the second output pulse of the pulse strobe generator 3, the duration of which is equal to the • period of the input signals of the phase meter. The number of pulses arriving at the second counter is proportional to the period of the input signals of the phase meter.

The switch 14 contains analog keys, ► connecting the inputs of the control signals of the computing unit 15 with its control inputs. The operation of the analog switches is controlled by the output voltages of the pre-> level converters 19, .23 supplied to the control inputs of the switch 14. The computing unit 15 provides a division of the number of pulses counted during the measurement by the first counter 7. by the number of pulses counted by the second counter 12, multiplying the result of dividing by the number of ZBOs and issuing the codes of the measurement result by a digital readout block 5. Computing block 15 is an integrated circuit whose main purpose is to work in simple calculators x It uses the time separation of control signals for entering numbers and signals for entering mathematical operations. Connection using the keys of the switch 14 of one of the inputs of the control signals of the computing unit 15 with one of its outputs of the control signals leads to the input of one of the digits of the number or to the input and execution of one of the mathematical operations (·> ^x > ⁼ ) ·

Block 16 synchronization provides the desired sequence of operations performed by the elements of the phase meter and adjustable delay the start of the process of measuring the phase with respect to the leading edge of the triggering pulse supplied to its third input. The latter allows you to select a specific period of the signal during which the phase value will be measured. The clock generator 17 is used to generate clock pulses that control the operation of the distributor-distributor 18, which forms a sequence shifted relative to each other! pulses that control the input of 15 digits into the computing unit and the input of mathematical operations. 5 necessary to obtain the value of the Phase difference.

The first level converter 19 provides the conversion of the levels of the input control signals of operations received from the output group of the decoder ^{, 0 of the} torus distributor 18 into the signal levels supplied to the control inputs of the switch 14 connected to the keys for input operations.

The four-input element And 20 and ¹⁵ inverting controlled inverter 21 are used to prevent the codes of the digit 0 code, which in such a phasemeter circuit is formed at the outputs of the invert ²⁰ multiplexers 8,10 and 13 in the absence of digital input signals at the inputs of the decoder 22 . The latter is observed when the computing unit performs input operations ²⁵ (:, X, =). In addition, the inverter 21 provides inversion of the output codes of multiplexers inverting the output codes of the decimal digits of the counters 7 and 12 and the register 9- ^{30; as a} result of connecting to the input of the element And 20 the output of the clock generator 17, a pause is obtained between input operations to the neighboring computing unit 15 35 digits of the number of pulses counted by the counters 7 and 12 and the number 360, the code of which is stored in the register 9. A pause is necessary for the normal operation of the computing unit 15 and 40 occur at time intervals and the output voltage of generator 17, clock pulses is equal to 0.

Decoder 22 provides the conversion of binary digit codes into 45 decimal codes that control the input of numbers. The second level converter 23 is used to convert the input voltage levels of the decoder 22 to the signal levels supplied to the control inputs of the switch 14 connected to the digital input keys of this switch.

When measuring the phase difference of the filling signals of two radio pulses, the phase meter operates as follows.

On the time intervals of the action of the radio pulses at the inputs of the input drivers 1 and 2 of the pulses, these shapers form two sequences of pulses having a duty cycle of 2, the steep leading edges of which are shifted by a time interval equal to the shift of the moments of the transition through the zero value of the fill signals of the input radio pulses. Simultaneously with the beginning of the formation of radio pulses, a short trigger pulse U ^ _{Qn is} supplied to the third input of the synchronization block 16. Under the action of the triggering pulse, a delay pulse is generated at the first output of the synchronization unit 16, which is fed to the first control input of the strobe pulse generator 3.

When the first leading edge of the pulse with duty cycle 2 appears at the first information input of the shaper 3 of the strobe pulses of the first after the end of the delay pulse generated by the synchronization unit 16, the strobe shaper generates two strobe pulses. The first strobe pulse having a duration T proportional to the phase shift is fed to the control input of the first time selector 6, and the second strobe pulse having a duration equal to the period T of the fill signal is fed to the control input of the second time selector 11. Under the action of the strobe pulses, the time selectors 11 and 6 open and transmit to the inputs of binary decimal counters 7 and 12 pulses the pulses of the generator 4 counting pulses ^ having a period of T _s . During the action of the strobe pulses, the counters 7 and 12 respectively calculate the number of pulses proportional to the phase shift and the number of pulses (^ proportional to the period of the fill signal.

I

Under the action of the trailing edge of the strobe pulse with a duration equal to the period of the fill signal coming from the second output of the formation. of the strobe pulse generator to the first input of the synchronization block 16, a control voltage is generated in it, under which the clock pulse generator 17 is turned on and starts to generate clock pulses controlling the operation of the distributor-decoder 18. The decoder-distributor 18 should have the number of outputs equal to the sum of decimal times 980015 rows of counters pulses 7 and 12 and number 6. The duration of the output pulses of the decoder-distributor is equal to the period of the clock pulses of the generator 17, slightly exceeding the 5th minimum Permissible interval between adjacent operations input calculation unit 15, a pulse period equal to the period of clock pulses multiplied by the number of decoder rows The yields ^{1c-raspredelitelya.Esli} each of the counters 7 and 12 pulses comprises five decimal places ^ the number of outlets 18 equal to 16 deshifratoraraspredelitelya and further ¹³ operation of the phase meter will occur as follows.

Under the action of the first five output pulses of the distributor-decoder 18, which are supplied to the control inputs 2C of the first inverting multiplexer 8, the latter alternately supplies inverted binary decimal codes of the first counter 7 pulses to the inputs of the controlled inverter ²⁵ , starting with the high-order codes. In this case, the decoder 22 codes converts the binary codes of the digits into a decimal code, the voltages of which are converted by the second transformer 30 of the 23 levels into voltages that control the operation of the switch keys 14. The alternate opening of the switch keys 14 under the influence of the output voltages of the converter 23 levels z $ provides input to the computational block 15 numbers, whose codes are stored in the first counter 7 pulses.

Under the action of the sixth output pulse of the distributor-decoder 40 18, a division operation is introduced into the computing unit 15. This is achieved as a result of the conversion of the sixth pulse voltage levels by the first converter 19 to a voltage 45, which controls the switch key 14, providing input of division operations.

Under the influence of the 7-11th output pulse of the decoder-distributor. 50, a number N ₂ is entered into the computing unit 15, KOflbi of which is stored in the second pulse counter 12.

Under the action of the 12th output pulse decoder ⁵⁵ distributor 18 to the computing unit 15 is introduced multiplication and division is performed of N _(the number Nd.

Under the action of 13 ^_ 15 ^_ the output pulses of the decoder-way valve 18 to the computing unit 15 is entered number 3 & 0, which codes are stored in the register 9 constant.

Under the action of the 16th output pulse in the computing unit 15, the operation of multiplication and the output of the result of calculating the phase difference are performed. The leading edge of the 1st pulse arriving at the second input of the synchronization block 16 starts the reset pulse shaper of this block. The reset pulse sets the elements of the synchronization block 16 to its initial state, as a result of which the clock pulse generator 17 is turned off and the control of the computing block 15 is stopped, which until the next turn on of the clock pulse generator 17 will only output the measurement result to the reference block 5 · From the second output <block 16 synchronization reset pulse arrives at the second control input of the shaper 3 of the strobe pulses and sets its elements in the initial state, continuing until the moment on at the control input trailing edge of a delayed pulse. This completes the cycle of measuring the phase difference of the signals filling the radio pulses. When measuring the phase difference of continuous sinusoidal signals, the triggering pulses are periodically fed to the third input of the synchronization block 16 with a period exceeding the sum of the period of the fill signal, the duration of 16 clock pulses and the time sufficient to count one measurement result. If a blocking element is introduced into the synchronization block 16, which ensures for some time after the arrival of the first triggering pulse that the synchronization block is insensitive to the next triggering pulses, then the frequency of the triggering pulses can be arbitrary.

The introduction of new nodes into the phase meter makes it possible to measure the phase difference of signals with a frequency that varies over a wide range.

Claims (2)

1.Smirnov P.T. Digital phase meters. L., Energie, E7, p.33, fig.3. 2. USSR author's certificate number 578625, cl. G 01 R 25/00, 1972.