SU1117592A1 - Device for checking measuring equipment metrological characteristics - Google Patents

Abstract

1. DEVICE FOR MONITORING METROLOGICAL CHARACTERISTICS OF MEASUREMENT MEANS, containing a reference frequency generator, a trigger connected in series and a gate, as well as the first counter, the first and second reversible counters, a digital-analogue converter, the first and second display units, the first code comparison circuit, and a frequency divider, the first and second display units, the first code comparison circuit, and the frequency divider, the first and second display units, the first code comparison circuit, and the frequency divider, the first and second display blocks, the first code comparison circuit, and the frequency divider, the first and second display blocks, the first code comparison circuit, and the frequency divider, the first and second display units, the first comparison circuit, and the frequency divider. characterized in that, in order to enable the formation of test signals that vary according to a triangular law and according to a law like transient with varying non-linearity, into it the first binary multiplier, the first gate, the second binary-ten multiplier, the nonlinearity coefficient setting block and the first pulse adder, as well as the delay block and the digital frequency converter, are entered in series, the first and second information inputs of the first pulse accumulator are connected to the information outputs of the block set the nonlinearity coefficient and the second binary-decimal multiplier, and the output of the first pulse adder is connected to the counting input of the first reversible count the counter, the counting input of the delay unit is combined with the counting inputs of the first binary-decimal multiplier and the first counter and connected to the output of the triggering unit; the control input of the delay unit is combined with the reverse inputs of the first and second reversible counters and connected to the output of the higher bit of the second reversible counter , the output of the delay unit is connected to the control (the left input of the valve, the information input of the digital frequency converter is connected to the output of the first revolving counter and the information input digits. the analogue converter, the input of the frequency divider is connected to the output of the first binary-decimal multiplier, the input of the second reversible counter is connected to the output of the frequency divider, and the first information input of the first socket of the code comparison circuit is connected to the bit inputs of the second reverse counter. 2. The device according to claim 1, wherein the each binary-decimal multiplier is formed by a second pulse accumulator, a second counter and two groups of second gates, the information output of the second pulse adder is connected to the counting input of the second counter, the outlets of which are connected to the information inputs of two groups of second valves, the outputs of the first group

Description

The second valve gates are combined with a binary-decimal multiplier output, the inputs of which are the locking inputs of the first valve group, and the outputs of the second valve group are connected to the second information input of the second adder.

3. The device according to and. 1, characterized in that the digital-frequency converter contains a clock pulse generator, a third counter, a forward code to a reverse code converter, a code adder, a second code comparison circuit, a delay element, a depiffrator and a third code comparison circuit, wherein the output of the clock generator is connected to the counting the input of the third counter, the information input of the direct code converter is inversely combined with the input

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the digital frequency converter, the information inputs of the second code comparison circuit are connected to the third counter outputs and the high bit output of the code adder, the control input of the delay cell is connected to the second cxejvibi code comparison output, the data inputs of the third code comparison circuit are connected to the decoder bit outputs, output the delay element and the second circuit are compared to codes, the bit inputs of the decoder are connected to the output of the low bit of the code adder, the output of the third code comparison circuit is connected to Sodom tsifrochastotnogo transducer and control codes Yusch th input of the adder, and the output transducer direct the return code to the information codes input adder.

The invention relates to a measuring technique, namely, devices for generating test signals when monitoring the metrological characteristics of measuring instruments. To control the metrological characteristics of the measuring instruments, it is necessary to use test signal generators. For this purpose, various measuring generators and sources of exemplary voltages are used. However, with the help of these devices it is possible to control only the static characteristics of the measuring instruments, while the time-varying signals are actually measured. Therefore, it is necessary to use generators of time-varying test signals. A device for forming a linearly varying reference voltage is known, comprising a reference voltage source, a switch, keys, an integrator, and comparison circuits. The device allows to form a triangular-variable voltage with two speeds of O. The drawbacks of the device are limited accuracy and stability due to the analog form-frame method, the impossibility of fixing the signal at an arbitrary level on command, including external devices such as comparators, selectors, etc., a limited type of output signal and a sweep shape (impossibility of modeling transition process curves), the impossibility of scaling the sweep by amplitude and time, and The time of measurement of the monitored means is to ensure the equality of the average values of the parameter during the rise and fall. Therefore, the device does not provide the functions necessary to automate the control of modern measuring instruments. The closest to the proposed is a device for generating signals of a special form, comprising a master oscillator, blocks for forming a period, a delay and a duration, and a block for forming an amplitude. The device excludes gene instability, provides for the formation of signals of a special form - pulsed G2}. However, the known device has limited functionality and does not provide for the formation of test signals that change according to a triangular law and curve like a transient with varying nonlinearity, scaling the sweep by duration and amplitude, the formation of a frequency signal, the measurement of the time of the monitored means. The purpose of the invention is to enable the formation of test signals varying according to a triangular law and transition type curves with varying nonlinearity, as well as taking into account the measurement time of the monitored means and the generation of analog and frequency signals. The goal is achieved by the fact that in a device for controlling metrological characteristics, measuring instruments containing a reference frequency generator, a trigger connected in series and a gate, as well as the first counter, the first and second reversible counters, a digital-analog converter, the first and second display units, the first comparison circuit codes and a frequency divider, entered in series the first binary decimal multiplier, the first gate, the second binary ten decimal multiplier, the block. the linearity and the first pulse adder, as well as the delay unit and the digital-frequency converter, the first and second information inputs of the first pulse generator are connected to the information codes of the nonlinearity coefficient setting unit and the second binary-decimal multiplier, and the output of the first pulse adder is connected with the counting input of the first reversible counter, the counting input of the delay unit is combined with the counting inputs of the first binary-decimal multiplier and the first counter and connected to the output of the trigger unit, the pack The main input of the delay unit is combined with the inputs T of the first and second reverse meters and connected to the high bit output of the second reversible counter, the output of the delay unit is connected to the control input of the valve, the information input of the digital frequency converter is connected to the output of the first reversible counter and an information input of a digital-analog converter; a frequency division input is connected to the output of the first binary-decimal multiplier; the input of the second reversible counter is connected to the output of the divider; Toty, and the first information input of the first code comparing circuit - a discharge outlet dnym br second down counter. In addition, each binary-decimal multiplier is formed by a second pulse adder, a second counter and two groups of second gates, the information output of the second pulse adder is connected to the counting input of the second counter, the bit outputs of which are connected to the information inputs of two groups of second gates, the outputs of the first group the second valves are connected by the d output of the binary-decimal multiplier, the inputs of which are the locking inputs of the first group of valves, and the outputs of the second group of valves are connected to the second info The input of the second adder. In addition, the digital frequency converter contains a clock pulse generator, a third counter, a direct code to reverse converter, a code adder, a second code comparison circuit, a delay element, a decoder, and a third code comparison circuit, with the clock pulse output connected to the counting input the third counter, the information input of the direct-to-reverse code converter is combined with the input of the digital-frequency converter, the information inputs of the second code comparison circuit are connected to the outputs of the third counter By the output of the higher bit of the code adder, the control input of the delay element is connected to the code of the second code comparison circuit, the information inputs of the third code comparison circuit are connected to the decoder bit outputs, the output of the delay element and the output of the second code comparison circuit, bit inputs the decoder is connected to the output of the lower bit of the code adder, the output of the third code comparison circuit is connected to the output of the digital frequency converter and the control input from the code mapper, and the output of the direct converter code in the reverse - with the information input of the adder codes. FIG. 1 is a block diagram of the deviceJ in FIG. 2 is a diagram of a binary-decimal multiplier, in FIG. 3 shows a digital frequency converter circuit; in fig. 4-6 are diagrams explaining the operation of the device. The device contains a reference frequency generator 1, a start node 2 formed by trigger 3 and valve 4, the first binary-decimal multiplier 5, valve 6, the second binary multiplier 7, block 8 for the nonlinearity coefficient, the first adder 9 pulses, the first reversible counter 10., the first block t1 of the indicator, the digital-frequency converter 12, the analog converter 13, the delay block 14, the first counter 15, T. ORO the display unit 16, the frequency divider 17, the second, the reversible counter 18, the first code comparison circuit 19, 20 start bus and bus 21 stop. Binary-decimal multipliers 5 and 7 contain a second adder 22 pulses, a second counter 23 and two groups of gates 24 and 25. Digital-frequency converter -12 is formed by a generator of 26 clock pulses,. a third counter 27, a second code comparison circuit 28, a delay element 29, a code adder 30, a third code comparison circuit 31, a decoder 32 and a forward-to-reverse converter 33. The change of the test signal (Fig. 4, curve a) occurs according to a triangular law, variants of the same signal, pr scaling in amplitude and in time, are shown by curves b, c, and d. The formation of curve b (Fig. 5) of the transient type a triangular test signal (curve a) using the deflection function (curve c), the amplitude of which varies and changes accordingly. the convexity of curve b. In the diagram of FIG. 6 shows how the measurement time of the monitored means is taken into account: the falling part a is delayed by a time equal to the time and measurement b, which starts synchronously with the start pulse c. The device works as follows. Before starting, the time code for measuring the monitored means is set at the inputs of block 14, which can be equal to zero or a certain amount, the speed and amplitude codes of the sweep at the inputs of multipliers 5 and 7, respectively, in percent of the highest value, the number at the inputs of the code comparison circuit 19 the sweep area where the controlled facility is started up, at the end of block 8, the nonlinearity coefficient of the transient type curve. When a command to start the sweep is issued, bus 12 is unlocked at start node 2 and the pulses from the output of generator 1 begin to flow to the inputs of nodes 5, 14 and 15. From this point in time, the following operation takes place: counting and indication of sweep time in the counter 15 and the display unit 16, the formation of parameter increments by multiplying 5 and 7, as well as the start-up pulses of the controlled means by the divider 17, the counter 8 and the code comparison circuit 19. The frequency of oscillator 1 is scaled by the first binary-decimal multiplier 5 according to the speed of the ramiper and is fed to the input of the divider 17, due to which the same number of start pulses are always generated at different sweep speeds. The pulses from the output of the multiplier 5 through the open valve arrive at the input of the second binary-decimal multiplier 7, which scales the sweep in amplitude (Fig. 4, VIG curves). Then, the increment pulses of the parameter arrive at the inputs of block 8 and adder 9. Depending on which sweep schedule is fulfilled, the setting value of block 8 may be zero (a triangular signal) or a certain value (transition curve). The nonlinearity is formed as follows. From the fundamental frequency of the pulses coming from the output of the multiplier 7, is subtracted and then added to it; the pulse frequency of the deflection function (Fig. 5c), as a result of which the ramp-up of the parameter is converted to non-linear. The parameter code accumulated in the counter 10 is fed to the inputs of block 11, digital frequency converter 12 and digital-analog converter 13. At the moment when the sweep code reaches the high bit output of counter 18, the signal changes, causing the counter 18 and counter 10 to reverse. subtraction and in the case of the measurement time of the monitored means, not equal to zero, the delay block 14 is started, the shut-off valve 6 is for the time equal to the measurement time of the monitored means (Fig. 6 b), due to which the start of The leveraged means by a simultaneous pulse (Fig. 6 g) is shifted relative to the falling portion in such a way that the average values of the parameters, measured with increasing and decreasing, are equal. This makes it possible to estimate and obtain the arithmetic mean value of the error when approaching the same parameter value from above and below. The device is terminated either at the end of the sweep cycle, or by an external command. In the second case, devices of the type of comparators are checked by applying to their input signals varying along a curve of the type of transitional process. At the moment when the signals reach the trigger level of the comparator, the signal from its output goes to the bus 21 and the device stops. A comparison of the setting level and the readings of unit 11 allows one to assess the accuracy of the monitored device. The work of binary-decimal multiplicates lei 5 and 7 is as follows. The input frequency is fed to the adder 22 and then to the input of the counter 23 from the outputs of which the binary-weighted frequency components are fed to the groups of valves 24 and 25. At the control inputs of the group of valves 25 a constant number 6 is set, resulting in one overflow account When sixteen pulses arrive at its input from the output of the groups 25 of the valves 25, six pulses arrive, i.e. for sixteen pulses arriving at the input of the counter 23, ten are fed through the input of multiplier 5 (7) and further through the adder 22, and six are added from the output of the groups of gates 25 also through the adder 22. From this it follows that the largest number that can be removed from multiplier 5 (7) for one overflow of counter 23, equal to ten, the code of which is set at the control inputs of the valve group 24. Thus, multiplier 5 (7) realizes the transformation of the number and number of sequences with a ratio of 1/10, 2 / 10, ... 10/10,. The denominator of which is fixed ovan, and the numerator is given as binary-binary codes. Digital frequency Converter 12 operates as follows. The code entering the converter 12 from the output of the counter 10 is converted by means of the converter 33 into a code opposite to the input one (for example, using the ROM 155PE) and fed to the inputs of sum 30 and performing the cyMNOtpOBaHHe input code with itself each time a pulse arrives from the output of circuit 31. The high bits of adder 30 are compared in circuit 28 with counter code 27, which is in continuous counting mode, and at the instant that the codes from the output of circuit 28 are equal, a pulse arrives, which is fed to the input of delay element 29. The signal from the output of the circuit 31 arrives when this pulse reaches a tap that is connected to the discharge opened by the unit from the corresponding output of the decoder 32, and the same pulse of the adder 30 performs the summation of the code from the output of the inverter 33 with the code in the adder 30 . Assume that from the output of converter 33, a period code of 21.1 µs is supplied. The bits of the adder 30, containing the integer part of the period code, are connected to the inputs of the code comparison circuit 28 and, if the counter 27 is in the zero state, then the first pulse from the output of the circuit 28 comes in 21 µs. Since the lower bits of the adder 30, which contain the fractional part of the period code O, 1 µs, are connected to the inputs of the decoder 32, then from the output of circuit 31 a pulse, the device’s output arrives delayed by O, 1 µs, and the total duration of the period is 21 , 1 µs, with the same pulse, the code 21.1 µs is added to the adder 30 and the code in it becomes equal to 42.2 µs. When the code in the counter 27, equal to 42 μs, from the output of the circuit 28, a pulse also arrives after 21 μs, but from the output of the circuit 31, the pulse arrives already in 0.2 μs. Since in the previous period the fractional part of 0.1 µs has already been formed, it is obvious that the next pulse will also be equal to 21.1 µs. The described process continues uninterruptedly and, as shown by the analysis of the operation of the device and its verification by n & The layout at a generator frequency of 23.1 MHz, the speed of the adder 30, as well as its periodic overflow does not matter. When the code changes at the output of the inverter 33, the output periods are processed with a very small dynamic error; The introduction of dual decimal multipliers allows scaling of the sweep both in time and in amplitude. The delay unit makes it possible to take into account the measurement time of the monitored means, which is necessary to ensure the equality of the average values of the measured parameter during the plant and the decline in the metrological certificate of the monitored means. Entering {above the block, specifying the nonlinearity coefficient and the pulse adder allows to convert a triangular-change ation signal with a curvilinear pattern 1

but changing as in transient modes of the CCD, and with variable non-linearity, which is necessary for research and control of comparators-type devices. The proposed scheme of a digital frequency converter makes it possible to reduce the discreteness of the generated frequency without increasing the speed of the element digital

base.

The invention develops the problems of automating the monitoring of static and dynamic characteristics of measuring instruments and has wide functionality, which allows it to be used to control multi-channel measuring equipment used in GTE tests, instead of using the reference engine for this, to save fuel and energy resources, to increase throughput the ability to stand and simplify experimental studies of the developed equipment.

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2

Vi (Pi)

Claims (3)

1. DEVICE FOR MONITORING METROLOGICAL CHARACTERISTICS OF MEASUREMENT MEASUREMENTS, comprising a reference frequency generator, a trigger and a valve connected in series, as well as a first counter, a first and second reversible counters, a digital-to-analog converter, a first and second display unit, a first code comparison scheme and a frequency divider, characterized in that, in order to enable the formation of test signals that vary according to the triangular law and according to the law of the type of transient with variable non-linearity, it is introduced the first binary decimal multiplier, the first gate, the second binary decimal multiplier, the nonlinearity coefficient setting unit and the first pulse adder, as well as the delay unit and the digital-frequency converter, the first and second information inputs of the first pulse adder are connected in series with the information outputs of the nonlinearity coefficient setting unit and second binary decimal multiplier, and the output of the first pulse adder is connected to the counting input of the first reversible counter the first input of the delay unit is combined with the counting inputs of the first binary decimal multiplier and the first counter and connected to the output of the trigger unit, the control input of the delay unit is combined with the inputs of the reverse of the first and second reversible counters and connected to the high-order output of the second reversible counter, block output the delay is connected to the control-: input of the valve, the information input of the digital-frequency converter is connected to the output of the first reversive of the counter and the information input of the digital-to-analog converter Vatel, the frequency divider input coupled to the output. the first binary-decimal multiplier, the input of the second reversible counter is connected by the output of the frequency divider, and the first information input of the first circuit for comparing codes is with the bit inputs of the second reversible counter. 2. The device according to p. ^ Characterized in that each binary-decimal multiplier is formed by a second pulse adder, a second counter and two groups of second valves, the information output of the second pulse adder is connected to the counting input of the second counter, the bit outputs of which are connected to the information inputs of two groups of second valves, the outputs of the first corpse 1 1 17592 of the second gates are combined with the output of the binary decimal multiplier, the inputs of which are the locking inputs of the first group of gates, and the outputs of the second group of gates are connected to the second information input of the second adder. 3. The device according to claim 1, characterized in that the digital frequency converter comprises a clock pulse generator, a third counter, a direct code converter, a code adder, a second code comparison circuit, a delay element, a decoder and a third code comparison circuit, wherein the generator output clock pulses connected to the counting input of the third counter, the information input of the direct code converter inverse is combined with the input of the digital frequency converter, the information inputs of the second code comparison circuit are connected the outputs of the third counter and the high-order output of the code adder, the control input of the delay element is connected to the output of the second code comparison circuit, the information inputs of the third code comparison circuit are connected to the bit outputs of the decoder, the output of the delay element and the output of the second code comparison circuit, the bit inputs of the decoder are connected to the output low-order bit, code adder, the output of the third code comparison circuit is connected to the output of the digital-frequency converter and the control input of the code adder, and the output of The direct code browser in reverse with the information input of the code adder.