SU1124346A1 - Analog-digital multiplying device - Google Patents

Abstract

ANALOG-DIGITAL MULTIPLE DEVICE containing a control unit, the first integrator, whose input through the first key is connected to the first input of the device and through the second key - to the output of the reference voltage source, -a output - to the first input of the first comparator, the second input of which is connected to a zero potential bus, and an output — to the first input of the control unit; a third key, the information input of which is connected to the second input of the device; a pulse generator, the output of which through the fourth key is connected to the input of the counter, bloka.upravleni he first output connected to the control input of the first switch, the second output controlling unit is connected to a control input of the second switch, the third control unit is connected to the output. The fourth key control input, characterized in that, in order to improve speed and accuracy, the device comprises a second integrator, a second comparator, an adder, a accumulating adder, a quad, a fifth and sixth keys, and a control unit contains a clock generator, an inverter, two differentiating element, two elements OR, two LK-triggers, the element AND and the element EXCLUSIVE OR, the output of the source of the reference voltage through the FIFTH key is connected to the input of the second integrator connected to the output of the third key, the output The second integrator is connected to the first input of the second comparator, the second input of which is connected to the zero potential bus, and the output to the input of the first differentiating element of the control unit, which is the second input of the control unit, the output of the counter is connected to the input of the quadrator, the output of the pulse generator is connected via the sixth key with the input of the summation of the accumulating adder,) the stroke of the counter is connected to the information input of the accumulating adder, the outputs of the quad and the accumulating adder are connected to the corresponding inputs of the adder, the control inputs of the third and fifth keys are connected respectively to the first and second outputs of the control unit, and the output of the EXHAUST OR OR control unit, which is its fourth output, is connected to the control input of the sixth key, the output of the clock generator is first output: the house of the control unit, connected to the inverter inlet and to the first inputs of the first and second SHS elements, the input of the second differentiating element is the first input of the control unit, the outputs of the first and second th differentiating elements connected to the second inputs of the first and second elements OR, the output of each of which through the corresponding 1 1st 3 -K-trigger connected to the inputs of the element And and

Description

element is EXCLUSIVE OR, the output of the inverter is the second output of the control unit, and the output of the element is the third output of the control unit.

one

The invention relates to computing and can be used to obtain information about the product of two similar quantities, as well as an external device in automatic control systems.

An analog-to-digital computing device is known, which allows to obtain the product of two analog quantities with the presentation of the result in a dhfrov form. Obtaining a product in this device consists in that one of the factors is digitized by an analog-digital converter, then this digital equivalent of the first factor is fed to the input of a digital-to-analog converter, which is used to multiply the other factor and then the analog the value, proportional to the product, is converted to digital form using an analog-digital converter CLL

However, this device has a rather low accuracy, so the KA analog-digital and digital-to-analog converters have their own conversion errors, and the entire device implements analog-to-code-to-code conversion, i.e. The aylo-digital converter will contribute to the total error of multiplication - twice, the digital-to-analog converter - once.

Closest to the proposed is an analog-digital multiplier device containing keys, the signal inputs of the first and second are connected to the inputs of the device, and the signal input of the third key is connected to the output source of the reference voltage source, the output of the first key is connected to the input of the integrator connected by the output with the input of the comparator, the output of which is connected to the first input of the control unit.

a pulse counter connected by an counting input to the output of the switch, the information input of which is connected to the output of the pulse generator, the control inputs of the keys connected to the output of the control unit. The multiplier device works in two cycles. In the second cycle, the second factor is measured while simultaneously multiplying in the counter. In the first cycle, the measurement is performed by the method of double integration and the result of the measurement is entered into the counter. At the beginning of the second clock cycle, the counter code is reversed. Starting from the second cycle, the second value is fed to the input of the integrator and a direct integration process is performed. The time of direct integration is proportional to the value of the first factor and, in general, less than the time of direct integration in the first cycle, and the voltage on the tag 4) ator at the moment of filling the counter is proportional to the product of the multiplying device values. Upon filling the counter, it zeroes out and begins the reverse integration, during which the counter accumulates: the digital equivalent of product 2. In this device, the analog-digital conversion introduces an error twice in the total error of the analog-digital multiplication, i.e. This multiplication method provides greater accuracy than the first device described. The disadvantages of this device are low speed and accuracy. If we consider the errors of the analog-digital conversion that occur in each cycle separately, it becomes clear that the conversion error, ceteris paribus, in the first cycle is less than in the second. Since, of all the garbage dumps, the component with the frequency of the supply (50 Hz) makes the most significant contribution to the measurement error, then, as a rule, the time of direct integration is chosen equal to or a multiple of the power frequency industrial frequency period. Therefore, a decrease in the time of direct integration entails an increase in the error of conversion, which is the case in the second cycle of operation of this device, the time of the direct integration of which is directly proportional to the first factor. The disadvantages of the known device also include the fact that a special second cycle is allocated for measuring the second factor and obtaining a product, which leads to a decrease in the speed of the devices and an increase in the dynamic measurement error. The purpose of the invention is to increase speed and accuracy. This goal is achieved by the analog-digital multiplying device containing the control unit, the first integrator, the input of which through the first key is connected to the first input of the device and through the second key - to the output of the reference voltage source, and a comparator, the second input of which is connected to the zero potential bus, and the output - to the first input of the control unit, the third key whose information input is connected to the second input of the device, a pulse generator, the output of which through the fourth to It is connected to the input of the meter, the first output of the control unit is connected to the control input of the first key, the second output of the control unit is connected to the control input of the second key, the third output of the control unit is connected to the control input of the fourth key, the second integrator, the second comparator adder, accumulator, adder, quad, fifth and sixth keys, and the control unit contains a clock generator, an inverter, two differentiating elements, two OR elements, two NK triggers, the AND element and the EXCLUSIVE OR element, the output of the source E | Talonnogo voltage through the fifth key is connected to the input of the second integrator connected to the output of the third key, the output of the second integrator is connected to the first input of the second comparator, the second 1 64 input of which is connected to the zero potential bus, and the output to the input of the first the differentiating element of the control unit, which is the second input of the control unit, the counter input is connected to the quad input, the output of the pulse generator is connected via the sixth key to the summing resolution input of the accumulating sum a, the output of the counter is connected to the information input of the accumulating adder, the outputs of the quad and accumulating adder are connected to the corresponding inputs of the adder, the control inputs of the third and fifth keys are connected respectively to the first and second outputs of the control unit, and the output of the EXCLUSIVE OR control unit, which is its fourth output is connected to the control input of the sixth key, the output of the clock generator, which is the first output of the control unit, is connected to the input of the inverter and to the first 11 inputs of The first and second elements OR, the input of the second differentiating element is the first input of the control unit, the outputs of the first and second differentiating elements are connected to the second inputs of the first and second elements OR, the output of each of which through the corresponding 3-K-trigger is connected to the inputs of the element And an EXCLUSIVE OR element, the output of the inverter is the second output of the control unit, and the output of the AND element is the third output of the control unit. Figure 1 shows the structural diagram of the proposed device; 1FIG.2 - time diagrams of work; FIG. 3 is a control block diagram. The device contains keys 1–4, sources 5 of the reference voltage, integrators 6 and 7, coaters 8 and 9, control unit 10, pulse generator 11, keys 12 and 13, counter 14, quad 15, accumulating adder 16, adders 17. Block control 10 includes a clock generator 18,3-K-triggers 19 and 20, the elements OR 21 and 22, the differentiating elements 23 and 24, the elements And 25 and 26, the inverter 27. The device works as follows. Before each measurement cycle, the units of the device are set to a state in which their output signals are zero. At time point to S11, the control unit 1Q outputs the signal, opening the keys 1 and 2, and thus the inputs of the integrators 6 and 7 are supplied with analog values x and y, represented as voltages. Keys 3 and 4 are open. The process of direct integration begins, which ends after a time multiple of the network frequency period, for example, after 20 ms at time C. Selecting the time of direct integration with a multiple of 20 ms ensures the noise immunity of both conversion channels from the network frequency interference. At time t, the keys open 1 and 2 and the keys 3 and 4 are closed; when the source 5 of the reference voltage is connected to the integrator inputs, the reverse integration process starts. Simultaneously, pulses from the generator 11 of pulses to the input of the counter 14 and to the input of the quad 15 begin to pass through the key 13. At time tJ, the voltage at the integrator's output (6 or 7), to the input of which, during direct integration, the lowest of the factors .e, x, becomes equal to U, 0. At this time, the comparator of the same channel (8 or 9) signals the end of measurements that go to the control unit 10, At this moment the control unit 10 prohibits the passage of pulses through the key 13 and allows the passage of pulses through the key 12 and to the input Resolution of the accumulation of accumulator accumulator accumulator 16, At the time% ends the construction of the square by the square 15 and the counting of pulses by the counter of 14 pulses. The length of the time interval is proportional to the magnitude of X. At time tj and the conversion channel comparator, a signal is produced. The end of measurement, which is fed to the corresponding input of the control unit. At this moment, the control unit 10 prohibits the passage of pulses through the key 12 to the input of the P decision to sum the accumulating adder 16 The duration of the time interval Jt-z i is proportional to the value of y The time slots and At.y are filled with pulses. With 6, the number of pulses placed on these segments is proportional to X and y-x, respectively. Accordingly, a number proportional to the output of the quad is formed, and a number proportional to x (y-x) is formed at the output of the accumulating adder. Thus, at the output of the adder 17, by the time of the end of the measurement, the largest of the quantities produces a number proportional to () xy. The proposed device has a faster response compared to the known one by parallel measurement of both factors and simultaneous multiplication. In the proposed device, the times are direct integration are constant, different among themselves and are multiples of the power frequency, which provides greater accuracy in comparison with the prototype by increasing noise immunity. Thus, the proposed device is more accurate and faster than the prototype. The control unit operates as follows. The clock generator 18 generates a signal, opening keys 1 and 2, with a duration of .20 ms, and locking v keys 3 and 4. Before the start of the first clock cycle, the 3-K triggers 19 and 20 are in zero state. At the end of the first clock cycle, the signal from the clock generator1) and 18 through the OR 21 element sets the trigger 19 to the state one, and through the OR 22 element sets the trigger 20 to the state one. Upon the arrival of the signal The end of the measurements coming from the output of the comparator 8 through the first differentiating circuit 23 and through the element OR 21, the three GGG 19 setting to zero, C is added by the signal's passage. The end of the measurement coming from the output of the comparator 9 through the second differentiating chain 24 and through the element OR 22, the trigger 20 is set to the zero position. Increasing the speed and accuracy determines the technical and economic effect from the use of the invention.

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Claims (1)

ANALOG-DIGITAL MULTIPLE DEVICE containing a control unit, a first integrator, the input of which is connected through the first key to the first input of the device and through the second key to the output of the reference voltage source, and the output to the first input of the first comparator,. the second input of which is connected to the zero potential bus, and the output - with the first input of the control unit, the third key, the information input of which is connected to the second input of the device, a pulse generator, the output of which through the fourth key is connected to the counter input, the first output of the control unit is connected to the control input of the first key, the second output of the control unit is connected to the control input of the second key, the third output of the control unit is connected from. the control input of the fourth key, characterized in that, in order to improve performance and accuracy, the device contains a second integrator, a second comparator, an adder accumulating an adder, a quadrator, a fifth and a sixth key, and the control unit contains a clock generator, an inverter, two differentiating elements, two OR elements, 'two E-K-flip-flops, the AND element and the EXCLUSIVE OR element, while the output of the reference voltage source through the fifth key is connected to the input of the second integrator connected to the output of the third key, the output is second the second integrator is connected to the first input of the second comparator, the second input of which is connected to the zero potential bus, and the output is connected to the input of the first differentiating element of the control unit, which is the second input of the control unit, the output of the counter is connected to the input of the quadrator, the output of the pulse generator through the sixth key is connected to the input of the resolution of summing $ 8 accumulating adder, the output of the counter is connected to the information input of the accumulating adder, the outputs of the quadrator and accumulating adder are connected to the corresponding the input inputs of the adder, the control inputs of the third and fifth keys are connected respectively to the first and second outputs of the control unit, and the output of the EXCLUSIVE OR control unit, which is its fourth output, is connected to the control input of the sixth key, the output of the clock generator, which is the first output of the control unit, connected to the inverter input and to the first inputs of the first and second elements OR, the input of the second differentiating element is the first input of the control unit, the outputs of the first and second differential switching elements are connected to the second inputs of the first and second OR elements, the output of each of which through the corresponding J-K trigger is connected to the inputs of the AND element and the EXCLUSIVE OR element, the output of the control interface, and the output of the AND element of the vert is the second output of the third control unit output.