SU807476A1 - Frequency multiplier - Google Patents

Description

Union of Soviet

Socialist

Republics

(..> 807476

DESCRIPTION

Inventions

X AUTHOR'S CERTIFICATE (61) Additional to author. certificate-wu (22) Declared 3107.78 (21) 2653032 / 18-09 with the addition of application No. - (23) Priority -

Published 2 3.0 281. Bulletin N9 7

Date of publication of the description 23.02.81 (51) M. Cl

H 03 B 19/00 (53) UDC 621.374.4 (088.8)

The invention relates to a frequency measuring technique of infra-low frequencies and can be used in equipment for analyzing a waveform, in * non-linear distortion meters, in phase meters with frequency multiplication, etc.

A frequency multiplier is known which comprises a reference frequency generator, a frequency divider with a variable division coefficient and a first counter, as well as a second counter, a control unit and a first pulse shaper, the input of which is the input of the frequency multiplier flj.

A disadvantage of the known frequency multiplier is the insufficient accuracy of the multiplication factor when operating in a wide frequency range of 2Q and the distortion of the sinusoidal shape of the output signal.

The purpose of the invention is to increase the accuracy of the multiplication coefficient in a wide range of multiplied frequencies while providing a sinusoidal output signal.

This goal is achieved by the fact that in the frequency multiplier containing serially connected

The reference frequency generator, a frequency divider with a variable division coefficient and a first counter, as well as a second counter, a control unit and a first pulse shaper, the input of which is the input of the Chartota multiplier, the first AND element is introduced, the first controlled generator and the second pulse shaper are connected in series, as well as the second element AND, the code memory block and the second controlled generator, the output of which is the output of the frequency multiplier, the counting input of the second counter and syn the timing inputs of the first and second controlled generators are combined and connected to the output of the reference frequency generator, the outputs of the first and second pulse shapers are connected to the control inputs of the first. and second counters, respectively, the outputs of the first counter are connected. to the code inputs of the first controlled generator, the outputs of the second counter 'connected to the corresponding code inputs of the second element and the first code inputs of the first ele. Menta And, the second code inputs of which are connected to the corresponding outputs of the code memory block, and the output is to the input of the control unit, the output of which is connected to the control input of the second element I.

The drawing is a structural _ Nye circuitry predlagaemo- th ^e frequency multiplier.

The frequency multiplier contains a control unit 1, the first and second drivers 2 and 3 pulses, the generator. torus 4 of the reference frequency, frequency divider 5 with a variable division ratio (DPKD), the first and second counters 6 and 7, the first and second controlled generators 8 and 9, the first and second elements of DO and 11 I, block 12 of code 15 memory, input 13 and output 14 of the frequency multiplier.

The frequency multiplier operates as follows.

The input signal U _{BX with a} frequency of f _x 20 is fed to the input 13 of the frequency multiplier, and then to the pulse shaper 2, where it is converted into rectangular pulses equal in duration to the period T _{x of the} input signal. Quantizing pulses with a frequency f ₀ from generator 4 through DPKD 5, made, for example, in the form of a 36-fold conversion circuit, with a frequency ^{ί =} 'arrive at the counting input of the counter .6 and are calculated by it during the duration of the operation of a rectangular pulse arriving at the control input of the counter 6. At the same time, the code output N _x is fixed at the code output of counter 6, which is determined by the following expression

- ^f o t - ^f °

Zb 1 O ' ^{1 x} 36 1 0nf _χ

This code goes to the code input of the controlled generator 8 and sets the frequency f _p proportional to the given code r Зб <1 0 ^h f _x 'at its output

Next, the signal frequency through the shaper 3 pulses is fed to the control input of the counter 7 and opens its counter input for a time equal in duration to the period T _{P of the} signal with frequency ff,. Quantizing pulses of frequency f ₀ from the generator 4 are fed to the counting input of the counter 7 and miscalculated by him during the time T _g . In this case, a code is fixed at the code outputs of counter 7, which is determined by the following expression ^N <Z ' ^f 0 ^T r ^{= f} O ^{/ f} r ^{, 36, 1} = 36Ί (Λίχ

Code Nj. then it is transferred through element 11 AND and block 12 of code memory 65 to the code inputs of the controlled generator 9 and sets the frequency f _0bix proportional to this code at its output,

Chykh = 36-io ⁿ f _x ,

When the frequency of the signal f * changes, the code is changed which is compared in the AND element 10 with the code of the code memory block 12, and if they are different in any category, the 10 AND signal is a signal that opens the 11 And element through the control unit 1, and into the code memory block 12 the new code is read from counter 7.

Thus, in this device, the equality fout ⁼ 36 * 1 0 ° fo · 'is monitored and maintained

So, for example, with a multiplication coefficient K = 3600, a frequency r ₀ = 10 * Hz and a frequency range of 10 ~ ⁵ ... 10 ³ Hz, the multiplication error is ^ 3.6 · 10 ~ ² %.

The technical and economic effect is to increase the accuracy of the multiplication coefficient in a wide range of multiplied frequencies while providing a sinusoidal output signal.

Claims (1)

1. USSR author's certificate in application I 2602441 / 18-09, cl. H 03 H 19/00, 04/10/78 (prototype).