SU757880A1 - Arrangement for graduating calorimetric apparatus - Google Patents

Description

The invention relates to calorimetry and can be used in devices for the calibration of calorimetric installations.

A device for calorimeter calibration is known, which contains a current stabilizer and a load resistance [1}. In this device, for the calibration process, the method of calibration tables is used, which consists in the compilation of tables of power values released on the load for each value of the stabilized current and each value of the load resistance. The power released on the load is calculated by the known value of the stabilized current and the load resistance value, which is measured during the calibration process, or by the voltage drop across the load resistance, which is also measured during the calibration process by a separate device. The need for calculations and the compilation of calibration tables, as well as the use of additional equipment, lead to a decrease in the efficiency and complexity of the calibration process.

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The closest in technical essence and the achieved result to the described device is a calorimeter calibration device,

5 containing current stabilizer, load resistance and timer [2].

The disadvantages of this device is the low efficiency and complexity of calibration, which are determined by the need for additional calculations.

The aim of the invention is to increase the efficiency and simplify the process of calibration of calorimetric 15 installations.

To achieve this goal, a voltage-frequency converter, a frequency divider with a variable division factor, first and second binary-decimal pulse counters, a memory register, first and second digital display units, and a control unit, whose inputs are respectively connected to the stabilizer, are introduced into the device. current and timer, and the outputs - to the load resistance, to the current stabilizer, to the voltage-to-frequency converter, to the first inputs of the first and second binary-decimal

s

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counters, to the memory register and the first input of the frequency divider, the second input of which is connected to the voltage-to-frequency converter, and the output is connected to the second inputs of binary-decimal counters, the output of the first counter through the memory register is connected to the first digital display unit, and the output of the second counter connected to the second digital display unit.

The drawing shows a block diagram of the device.

The device contains a current stabilizer 1, voltage to frequency converter 2, frequency divider 3, first binary decimal counter 4 pulses, memory register 5, first digital display unit 6, second binary decimal pulse counter 7, second, digital display unit 8, block 9 controls and timer 10.

The current stabilizer 1 is connected to the load resistance 11 through the control unit 9, the input of which is connected to the output of timer 10, the outputs of the control unit 9 are connected to the second inputs of the frequency divider 3 with variable division factor, binary decimal counters 4 and 7, and memory register 5. The voltage-to-frequency converter 2 input is connected to load resistance 11, the voltage-to-frequency converter 2 output is connected to the first input of frequency divider 3, the output of which is connected to the first inputs of binary decimal counters 4 and 7, the output of the first counter 4 is connected to the first input of memory register 5, the output of which is connected to the input of the first digital display unit 6., the output of the second binary decimal counter 7 pulses is connected to the input of the second digital indication unit 8.

The device works as follows.

Current stabilizer 1 supplies a stable current to the load resistance 11. The voltage incident to the load resistance is fed to the input of the converter 2 "voltage is often the same." The pulses from the output of converter 2, whose frequency is proportional to the voltage drop on the load resistance 11, are fed to the divider input 3 frequencies with variable division factor. The division factor of the frequency divider is proportional to the conversion ratio of the voltage to frequency converter and inversely proportional to the value of the current flowing in Through the load. The frequency of the pulses at the output of the divider P is equal to

K ·

that

where - the conversion factor of the voltage converter to frequency;

and - the voltage drop across the load resistance;

K ₂ - the coefficient of the frequency divider with a variable division factor;

And - the value of the stabilized current flowing through the resistance of the load.

Thus, the frequency of the pulses at the output of the frequency divider, that is, the number of pulses per 1 s, is equal to the power released by the load resistance. The output pulses of the frequency divider are counted by binary decade counters · 4 (“power”) and 7 (“energy”). The output of the counter 4 is connected to the input of the register 5 of the memory, to the output of which the digital indication unit 6 is connected. The rewriting of information from counter 4 into the memory register 5 is performed every second. Setting to “zero” counter 4 is also performed every second with some delay relative to the rewriting of information. Thus, the digital indication unit 6 highlights the digital value of the power released on the load resistance 11. The output of the counter 7 is directly connected to the input of the digital display unit 8. The counter 7 counts the pulses during the entire time of energy release. The values of the stabilized current and the division ratio of the divider frequency 3 is set using the switch located in the control unit 9. In addition, the control unit generates a reset, write and set to zero signals necessary for operation of counters 4 and 7 and memory register 5. The time of release of energy at the load resistance is set by timer 10.

The use of the proposed device eliminates the need for additional measuring equipment (high-end voltage, resistance meters, timers, etc.) for calibrating calorimeters. There is no need to pre-compile the calibration tables for each specific load resistance or to calculate the power and energy released on the load resistance in the process of calibration, which significantly reduces the complexity of the calibration process and increases the efficiency of the process.

When performing calibration with

using a known device

on the compilation of the calibration table, we for one resistance load5

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ki requires at least 5 hours. The device allows graduation without prior generation of calibration tables, regardless of the spread of load resistance values. five

With a large energy release time, graduation from a known device necessitates measuring the load resistance value, which may change during the calibration process, or the need to measure the voltage drop across the load resistance and then calculating the power and energy released on the load resistance. The proposed device indi- cates the values of power and energy released on the load resistance directly during the calibration process.

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Claims (1)

Claim A calibration device for calorimetric installations that contains a current stabilizer, a timer, and a load resistance, different in that, in order to increase efficiency and simplify the calibration process, 3θ converters are introduced into it. voltage to frequency recipient, variable division factor frequency divider, first and second binary decimal pulse counters, memory register, first and second digital display units and a control unit whose inputs are respectively connected to a current regulator and a timer, and outputs to a load resistance , to the current stabilizer, to the voltage to frequency converter, to the first inputs of the first and second binary-decimal counters, to the memory register and the first input of the frequency divider, the second input of which is connected to the pr the forming voltage frequency, and an output connected to second inputs of the binary-decimal counters, the output of the first counter via a memory register connected to the first block of digital indication ,, and the second counter output is connected to the second digital display unit.