SU974585A1 - Line switching-over device - Google Patents

Description

(5 LINK TRANSMITTER

The invention relates to computing and communication technology and can be used for switching highways in multi-machine computing complexes. A switch of lines is known, comprising connected between the first and second lines of antiparallel connected groups, each of which consists of serially connected along the first inputs of the first and second elements AND, with the st inputs of the first element AND of the first group and the second element AND the second Groups connected to the control bus f 1 The disadvantage of the known devices is the low noise immunity due to the absence of interlocking groups during the passage of signals. . A switch of lines is also known, containing connected between the first and second lines of counter-parallel-connected groups, each of which consists of the first and second elements AND connected in series along the first inputs, the second inputs of the first element AND of the first group and the second element AND of the second group connected to the control bus, the memory element, non-inverting output of which is connected to the second input of the first element AND of the second group, resistor-capacitive. the delay element included at the input of the memory element and the control unit 2j. The disadvantage of this switch is the greater complexity, due to the presence of memory and delay elements in each group, the OR element and matching inverters. The purpose of the invention is to simplify the switch lines. The goal is achieved by the fact that in the line switch, there are anti-parallel connected groups connected between the first and second lines, each of which consists of And connected in series through the first inputs of the first and second elements, and the second inputs of the first element And of the first group and the second element And the second group are connected to the control bus, the memory element, the non-inverting output of which is connected to the second input of the first element And the second group, a resistor-capacitive delay element connected to during the memory element, and the control unit, the control unit is made as an unequal element, the first input of which is connected to the output of the first element AND of the first group, the second input with the output of the first element AND of the second group, and the output through a resistor-capacitive delay element resistor is connected to synchronization input and input Reset of the memory element, the inverting output of which is connected to the information input and connected to the second Btoporo input of the AND element of the first group. Figure 1 shows the functional diagram of the proposed switch in figure 2 - timing diagrams of operation The switch of lines (figure 1) contains the first 11 and second 1.2 lines, the first 2.1 and second 2.2 groups. The first (second) group consists of the first 3.1 (3-2) and second 4.1 (, C.2) elements I connected in series along the first inputs. In addition, the line switch contains a control unit that includes the control bus 5, the element 6 memories (three | - ger), a resistor-capacitive delay element 7 and an unequality element 8. . . . The resistor-capacitive delay element 7 includes a series-connected resistor 9 and a capacitor 10. The first input of the element 3.1 of the group 2.1 is connected to the first line 1.1 and to the output of the element I..2 of the group 2.2, and the first input of the element 3-2 to the second line and to the output of the element And kl group 2. one . The second input element And 3-1 group 2.1 and the second input element And 4.2 group 2.2 connected to the bus 5 control switch. The second input of element 3.2 of Group 2.2 is connected to the non-inverting output of the memory element 6, and the second input of element AND A1 of group 2.1 to the inverting output and information input of memory 6. The first input of element 8 is unequal and is associated with the output of element AND 3..1 of group 2.1, and the second input with output of element 3.2 of group 2.2. The output of the unequal element 8 through the resistor 9 of the delay element 7 is connected to the combined inputs Reset and Synchronize the memory element 6, and through a series of resistor 9 and the capacitor 10 of the delay element 7 to the common, power supply pole (not shown in Fig. 1 ). The input $ of the memory element is connected to the positive pole of the source (the value is logical 1). The elements AND 3 and-A of each group are elements with three states: Zero, Unit and Open (high output impedance. The state of the element depends on the signal at the control (second /) input. If the signal at the control input is equal to one The element is in the third state. If this signal is zero, the state of the element is determined by the state of the first input (line. Resistor-capacitive element 7, the delay is used to implement the necessary time shift of the signals in the lines. As element 6 memory is used by fro 2a shows the signal on line 1.1; fig.26 shows the signal on line 1.2; fig.2b shows the signal at the second input of the AND 3.2 element (the signal at the forward output of the memory element 6); 2d is the signal at the output of element 3.2 of group 2.2 (the signal at the output of element ii of group 2.2); fig.2d is the signal at the inverse output of memory element 6; fig.2e is the signal at the output of element 4.1 of group 2.1; in Fig. 2g, the signal on the control bus 5 (the zero value of the signal is shown); in FIG. 2, the signal at the sync input of the memory element 6 (signal at the input Reset the memory element; the shaded areas correspond to the open state (the third state (FIG. 2d and e). The switch of the lines works as follows (Figures 1 and 2 ) On the control bus 5, an enable (logical) or prohibit signal (logical transmission 1. Let transmission, for example, be permitted (Fig. 2g). 3 depending on the state of lines 1.1 and 1.2, there are four different combinations. Let, for example, the initial moment both lines are in the single state, and the trigger 6 in zero (figa, b id). In this case, its non-inverting output contains a zero signal (figv) and the output of element 3.2 of group 2.2 -: a signal that matches the signal in line 1.2, i.e. (Rig.2g.) The same signal at the output of the AND element k.2, since Resolution was sent to the control bus 5 Figure 2g.) For the same reason, at the output of the AND 3-1 element of group 2.1 there is a single signal Sigf.2a Since a unit is fed to the second input of the AND 4.1 of the group 2.1 (Fig. 2d), the +.1 element is in the Open state (Fig. 2e). From the outputs of the elements 3.1 and 3.2 of the groups 2.1 and 2.2, single signals are supplied to the unequal element 8 and the zero signal from its output is removed through the delay element 7 to the Reset and Sync inputs (FIG. 2h) of the memory element 6. Thus, with single signals on lines x 1.1 and 1.2, there is no transfer from line to line. As soon as Zero appears on line 1.1 (Fig. 2a), it is removed from the output of element 3.1 of group 2.1 and fed to the input of element 8 of unequalities, from the output of which it removes a single signal. The latter through delayed capacitive element 7 delays t is fed to the Reset input and the synchronization output of the memory element 6 (Fig. 2h). The front trigger circuit 6 is implemented in such a way that the signal at the input Reset works out ahead of the synchronization input. At the time of the occurrence of a single signal at the input of the Synchronization of the memory element 6, the state of the latter changes to a single one (FIG. 2B and 2D), as a result of which AND 3.2 of Group 2.2 enters the third state (FIG. 2 g), and And .1 group 2.1 transmits the zero signal (Fig. 2e. Thus, when the signal ratio of lines 1.1 and 1.2 is zero and one, respectively, the transfer of the zero signal 5 from line 1.1 to line 1.2 (group 2.1 is closed, group 2.2 is open) occurs. Now a zero signal appears in line 1.2 (FIG. 2B) since The element “3.2” of group 2.2 keeps the unit “(Oig.2c), the state of element And 3.2 does not change, the third state of FIG. 2d remains, and consequently, there is no change in the rest of the scheme (Fig. 2e, e and h), i.e., transmission from line 1.1 to line 1.2 is maintained (transmission continues from the line in which it previously ranged to Zero). This continues until the signal Zero in line 1.1 does not change to the Unit signal ( figa). At the same time, a single signal appears at the output of the AND element of group 2.1, and a zero signal appears at the output of the 8 inequality element, which through the delay element 7 delayed T arrives at the Reset and Synchronization inputs of the memory element 6 (FIG. 2h) and changes it condition. At the second input of the element And 3.2, a Zero appears (fig. 2b), the output also has a Zero (fig.2g}, as a result of which the element And E.1 goes into the third state (fig.2e), as a result of which group 2.1 opens and the transmission from line 1.2 to line 1.1 occurs. When a zero signal disappears in line 1.2 (fig. from the output of element AND 3.2, a single signal is fed to the input of element 8 of unequalities (fig.2g, from the output of which the zero signal is still removed) Reset and Synchronize the memory element 6 (Fig. 2z, keeping the state of the latter unchanged. Transmission from the line 1.2 is terminated and the line switch returns to its original state. Using the invention allows the switch to be significantly improved compared to the prototype while retaining the basic characteristics. This switch contains 1.8 times less cases (capacitor plus resistor is considered to be one case). The invention is a switch of lines, containing the included first and second lines of anti-parallel connected 797 58 groups, each of which is a connection-T and T of the series connected in series on the first inputs of the first of the second element And, the second inputs of the nepj00GO element —And the first group and the second 5th element And the second group are connected to the control bus; a memory element, the non-inverting output of which is connected to the second input of the second element And the second group, capacitive to delay element, included at the input of the memory element, and control block, from the following: in order to simplify, the control unit is designed as an unequal value element, the first input of which is connected with the release of the first element And the first group, the second input - output of the first cell and B (Torah group, and an output through the resistor resistor; 20 5.8 of the capacitive delay element is connected to the synchronization input and the Reset element input, a memory whose invert output is connected to the information input and connected to the second input of the second AND element of the first group. Sources of information taken into consideration in the examination of 1. Dro3-FH / FP: Uri bus Switch. AorlJ, 1973, Document But CSS-MO-F-101-19, .k-kO Line Log Is rlunit. 2. Technical documentation PN SM "501 (bus switch) 263.089. .496.33, a block of elements of the BZ U expander control). M., Institute of Electronic Uprdvl yu their machines, 1980, album If 3, Appendix 2 (prototype).

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Claims (1)

lines, containing the first and second types of switches, a switch • connected between the lines is counter-parallel connected7 974585. groups, each of which consists of series-connected at the first inputs of the first and second elements of AND, and the second inputs of the nepj- __....___________ _{_} ____________ _{_ of the} first element And of the first group and the second ~ 5 input and connected to the second-capacitive The delay element is connected to the synchronization input and the input. '' Reset of the element, the memory whose inverting output is connected to the element And the second group is connected to the control bus, the memory element whose non-inverting output is connected to the second input of the first element And the second group, p zistorno capacitive th. the delay element included at the input of the memory element and the control unit are different in that, for the purpose of simplification, the control unit is made in the form of an ambiguity element, the first input of which is connected to the output of the first AND element of the first group, the second input - with the output of the first element AND of the second, group, and the output through the resistor to the resistor 15th input of the second element And of the first group.