SU432667A1 - PHASE-PULSE MULTIPLE-TERM ELEMENT - Google Patents

Description

one

The phase-impulse multi-valued element implements the function of multi-valued logic of the form and can be used to build discrete schemes for industrial automation automation (computational and digital measuring equipment, instrumentation, etc.).

A phase-pulsed multi-valued element is known, which contains binary memory elements, input buses connected to the first binary element, and buses connecting the constant generator.

The disadvantages of a phase-pulse multi-valued element are low speed and a large number of binary elements with memory.

In order to increase the speed of the phonon-multi-valued element with the minimum number of binary elements not dependent on the logic value, the output of each previous binary element with memory is connected to the input of the installation to the zero state of the subsequent binary element with memory, and the inputs of The unit state of all binary elements with memory and the INPUT of the installation in the zero state of the last binary element with memory are connected to the buses and the connections of the constant generator. In addition, to reduce the amount of hardware Nree cyclically inverting one argument, the input bus

one argument is connected to the input of the installation to the zero state of the last binary element with memory.

The drawing shows the scheme of the proposed pulse-phase multi-valued element.

The phase-imimage multivalued element consists of three sequentially included binary elements 1, 2 and 3, two of which (elements 2 and 3) are binary elements with memory and are connected to the constant generator busbars at inputs 4 and 5.6. The binary element / when implementing the phase-pulse multi-valued element of the th-valued function is a disjunctor for the rt-inputs to which the input buses 7 are connected. The output of the binary element / is connected to the input of the installation of the zero of the binary element 2 with memory, to the input of the installation of which connected to the constant generator corresponding to the clock on the cycle immediately preceding the first cycle of the digital period.

The output of the memory double element 2 is connected to the input of the zero setting of the double element of the memory 3, to the other input 6 of the zero setting of which the constant generator bus is connected, which provides the pulse with the same beat as the first cycle of the digital period. To the input 5 of the installation of the unit of the binary element 3, a niche of the constant generator with the clock immediately following the first digital clock is connected to it. The output of binary element 3 with memory. Is connected to the output 8 of the phase-mummy multi-valued element.

Beli phase- | Impulsive set-valued eleMCHT is used: As a cyclic inverter, the unit | INVTNNAA input bus of the argument is connected to the input of the installation of the binary element 5c with our BIMCCTO output of the previous binary element 2 with memory. Binary elements 1 and 2 are disabled in this case.

The work of the phase-multipolar multi-valued element can be considered in a concrete example with k 5, 10 cycles in the digital period.

The information on the inputs of the "7" enters the gyu to the odd clock cycles tt, / 3. fs, t and / g. At the input 4, the pmiculums are continuously supplied according to the cycle to, and to the inputs 5 and 6, the pulses are given to the cycles t and ti, respectively. At the same time, at output 8, information is output with a shift of two cycles: 4, / 5, tT, / 9 p / j - where the upper index of the tact indicates the digital / period period relative to the first one under consideration.

Job options are divided into two groups.

In the first group, there are no pulses at the inputs t on the inputs 7. Since the presence of one pulse in the digital period for each of the "input buses is necessary, then the pulses at the inputs b.n 7 appear in cycles (,, t, ti, PLI / g. Since the input 4 already has an impulse, according to the IQ cycle, and to the input 5 - by r / g, the very first impulse that came to one (or several) input bus 7 translates binary elements with memory into the zero state, and binary element 2 with memory will provide the appearance of a pulse at the output p sets the binary element 3 with memory to the zero state, and at the exit 5 a pulse appears.

Any subsequent pulses of the same digital period at the inputs of spr 7 do not cause the appearance of pulses at output 8. The pulse received at input 6 according to the beat t also does not cause them to pulse at output 5, since binary memory element 3 is set to a single state only per clock / 2 pulse, fed from the generator, is set to input 5.

In the second group, one appears on the input buses 7: Or several pulses per cycle (i) this impulse, getting to the input of a binary zero element 2 with memory, causes it to be transferred from state “1 to state” ensures the formation of a pulse at the output of element 2. But by this time (/) binary element 3 is in an eh state, and, since it is set to one in unit state, it is in clock / 2 mode.

has already been transferred to the state of "O in tact". All the following pulses at the inputs of spy 7 do not change the state of the circuit: binary element 2 with the memory is in the state "O, and binary element 3 with the axis is in the institute "one.

The t pulse of the second digital period (regardless of the PPPO value) iia bus inputs 7) from the constant generator generates a pulse at input 6, providing translation of binary element 3 with memory from one state to zero, which causes the appearance of a phase output -p; lulse multivalued element 8.

Thus, the phase-pulse multi-element element provides the delay of the first VHO. Single pulse (() for the digital period and the transmission of the second and subsequent pulses (3, (b, (, e) to the output without delay.

Subject matter

Claims (2)

1. Phase-pulse: a 1-digit element containing binary memory elements, input buses connected to the primary binary element, and connection buses of the constant generator, characterized in that, in order to increase speed, the output of each previous binary element from -; The mine is connected to the installation input to the zero state of the subsequent binary memory element, and the installation inputs are in the same state of all binary elements with memory and the installation input to the zero state of the last binary memory element is connected to the connected constant generator. 2. An element according to claim I, characterized in that, in order to reduce the number of equipments during cyclic and invertting of one signal, the input bus of one argument is connected to the input of the installation to the zero state of the last binary memory element.