SU962985A1 - Device for sencing information from network electric model - Google Patents

Description

The invention relates to analog digital computing and can be applied in a hybrid computing system for collecting and pre-processing information and transferring it from the grid electric model to a digital computing machine (DVM).

A device for retrieving information from a grid electric model is known, which comprises a selection unit, a sample decoder, a control unit, analog-digital converters, keys, a correction unit, and a software control unit Lenin f1} ..

However, the known device has a low reliability in operation.

Closest to the proposed technical entity is a device that contains the nporpaNWHoho control unit, the comparison unit,. ana-digital-digital converters, a correction unit, a selection unit, a switch, a converter control unit and multiplexers 2 J.

A disadvantage of this device is its low speed.

The purpose of the invention is to increase the speed of the device.

. The goal is achieved by; that the device for retrieving information from the grid electric model contains a software control unit, the first output of which is connected to the first input of the sample decoder, the output of which is connected to the address input of the selection unit, the output of which is connected to the information input

10 of the switch, the outputs of which are connected to information inputs of analog-digital converters, information outputs of which are connected to the inputs of the first and second multiplexes 15, control output, analogue digital converter converters are connected to a group of inputs of the correction unit, the output of which is connected to the second input of the decoder of the sample, block cara20 associated with the correction unit and the program control unit, the second output of which is connected to the input of the code-controlled reference source 25 voltages, the output of which is connected to the control input of the switch, the control input of which is connected to the third output of the program control unit, the fourth output of which

30 is connected to the input of the converter control unit, the outputs of which are connected to the control inputs of the analog-digital converters, the y-inputs of the first and second multiplexers are connected to the fifth and sixth outputs of the software control block, the additional one is inserted into the arithmetic unit first and second multiplexers, adder, first second and third registers, memory block, the first and second inputs (DO adder are connected to the outputs of the first and second multiplexers arithmically The first output of the adder is connected to the first input of the comparison unit and to the input of the first register, the output of which is connected to the first input of the first multiplexer of the arithmetic unit, the second input of which is connected to the output of the second register, whose input is connected to the second output of the program control unit , the second output of the adder is connected to the first input of the memory unit, the first output of which is connected to the second input of the comparison unit, and the second output to the first input of the second multiplexer of the arithmetic unit, the second input which is connected to the output of the third register having an input connected to the output of the first multiplexer, a memory unit subkey to duplex link software control unit. In FIG. 1, 2, and 3 are diagrams of the device. The device contains a software control unit 1, a decoder 2 samples, a selection unit 3, an input commutator 4, analog-digital converters C ADC 5-8, multiplexes 9 and 10, a correction unit 11, an arithmetic unit 12, a comparison unit 13. code-controlled source 14 of these voltages, converter control unit 15. The arithmetic unit 12 contains an adder 16, multiplexers 17 and 18, a private sum register 19, a memory block 20, a reference code register 21, a register counter 22. The program control unit 1 contains a buffer memory block 23, a stack unit 24 of addresses of faulty ADC ,, .multiplexer 25 address microcommand, register 2.6 microcomacd, memory block 27, incrementor 28, program counter register 29, return address stack memory block 30, programmable control memory block 31, state register 32, multi. The type of 33 states, DVR 34. The device operates as follows. The information input of the device is connected to the grid electric model (not shown). The information output of the device is connected to a digital computer (not shown). Control inputs and outputs are connected to a digital computer. From the digital computer to the program control unit 1, the program of operation of the device is recorded. The program control unit 1, according to the program, launches the decoder 2 samples, the control unit 15, the converter, the output converter 9, and the additional 10 multiplex. Ry. In the arithmetic unit 12 and in the code-controlled source 14 of the reference voltages, the code of the reference voltages is recorded, depending on the selected range and step of the reference voltage of the control of the ADC 5-8. The two-way communication buses in the correction unit 11 write a reference code depending on the number of ADCs in the device, the code determining the number of low-order bits of the output ADC code not counted under the control of the ADC is entered into the arithmetic unit 12, and in block 13 compare The reference code, for comparison with the control code. In the proposed example, in block 13, zero is entered, a code. . According to the program, the decoder 2 samples connects the selected node points of the SITCH electric motor to the 4-input switch, which, at the command of b / go 1 of the program control, connects the grid points to the ADC inputs. 6-8, and to the Input ADC.5 connects the output of the code-coupled source 14 reference voltages. The converter control unit 15 launches according to the program of A / D converters 6–8, which begin to convert nodal potentials. ADC 5 operates in auto-control mode. The reference voltage from the output of the code-controlled source 14 of the reference voltages through the switch 4 inputs is fed to the input of the ADC 5, the output code of which through an additional multiplexer 10, triggered by a command from the program control unit 1, is fed to the third input of the arithmetic unit 12 and then to the input register counter 22. Additional code from the output of register counter 22 is fed to the second input of the second multiplexer 18. The reference code recorded in the register 21 of the reference code is fed to the second input of the first multiplexer 17. From the outputs of the first 17 and second 18 multiplexers, the codes go to the first and second inputs of the adder 16. From the first output of the adder 16, the private amount code arrives at the input of the partial amount register 19 and from its output to the first input of the first multiplexer 17. At the second output of the adder is a control signal.

 If the code at the output of the checked ADC 5 is greater than the reference code, then the control input of the memory block 20 from the second output of the adder 16 is supplied. 1. By this signal, the memory block 20 depends on the code recorded in its input register and depending on the number of unaccountable low-order bits of the output code of the ADC, gives the correction code to the first input of the second multiplexer 18. on the second in Which receives the mask code from the second output of the memory block 20, and on the third input the zero code is valid. If there is no signal 1 in the checked bits of the code at the output of the block; 13 comparison, an O signal appears, meaning that the ADC is healthy and, if present, a signal 1, which is fed to the input of software control unit 1. By this signal, the latter provides information for registering a non-faulty ADC and sends a signal to the control input of the 4-input switch, which excludes the faulty ADC from the operation of the device. The software control unit 1 issues a correction code to the correction unit 11 and the converter control unit 15, which continue to launch healthy ADCs with a corrected time delay.

I IF the code at the output of the tested ADC 5 is less than the reference code, then the control input of the programmable logical Ml TpHutd from the second output of the adder 16 received a signal O and from the first input of the memory block 20 to the first input of the second multiplexer 18. A zero code arrives is summed up from the private sum code from the output of register 19 of the partial sum, and then, the above scheme works in a manner similar to that described above. According to the program from the software control unit 1, the control of the A / D converter 5 is carried out in a predetermined range of reference voltages. If the tested ACC 5 is healthy and converts, for example, Kenya in a given range with a given accuracy, the program control unit 1 outputs a switch to 4 inputs, through which the output control signal source 14 of the reference voltage is connected to the input of the next ADC 6, and the input of the ADC 5 connect to the next nodal point of the grid electric models.

The proposed device, due to the presence of new elements and the connections between them, allows to increase the speed of the analog-digital complex by using the maximum possible number of analog-digital converters.

Claims (1)

Apparatus of the Invention A device for retrieving information from a grid electric model, comprising a software control unit, the first output of which is connected to the first input of the sample decoder, the output of which is connected to the address input of the selection unit, the output of which is connected to the information input of the switch, the outputs of which are connected to the informational inputs analog-to-digital converters whose information outputs are connected to the inputs 5 of the first and second multiplexers, the control outputs of the analog-to-digital converters are connected to a group of inputs of the correction unit, the output of which is connected to the second input of the sampling decoder, a comparison unit connected by a two-way communication line to the correction unit and the program control unit, the second output of which connected to the input of the code-controlled source of reference voltages, the output of which is connected to the control input of the switch, the control input of which is connected to the third output of the program control unit Whose fourth output is connected to the input of the control unit pre-. formers whose outputs are connected to the control inputs of analog-digital converters, the control inputs of the first and second 5 multiplexers are connected to the fifth and sixth outputs of the program control unit, respectively, so that, in order to improve speed, an arithmetic unit is inserted in the device containing the first and second multiplexers, the adder, the first, second and third registers, the block memory, with the first and second inputs of the adder 5 are connected to the outputs of the first and second multiplexers of the arithmetic unit, the first output of the adder is connected to the first input of the comparison unit and to the input of the first register, the output of which is connected to the first input of the first multiplexer of the arithmetic unit, the second input of the first multiplexer of the arithmetic unit is connected to the output of the second the register, whose input is connected to the second output of the program control unit, the second output of the adder is connected to the first input of the memory unit, the first output of which is connected to the second input comparing unit, the second output 0 of the memory unit is connected to the first input of the second multiplexer of the arithmetic unit, the second input of the second multiplexer of the arithmetic unit is connected to the output of the third register, 5, the input is connected to the output of the first multiplexer, the memory unit is connected to a two-way communication line of the program control unit. Sources of information taken into account in the examination USSR certificate 06 G 7/06, 1976. USSR certificate 06 G 7/04, 1979 pus.j f6 J 25 27 GB