SU1267272A1 - Digital integrating voltmeter - Google Patents

Abstract

The invention can be used in measuring the average differential component of two voltages of arbitrary shape. The purpose of the invention is to increase the sensitivity and expansion of functional capabilities. The device contains controllable attenuators 1 and 2, keys 3, 4, 8, 11, 12 and 29, controllable phase shifters 5, 6, converter 7 phase - code, storing blocks 9 and 30, shaper 10 of the difference signal, shaper .13 total signals, blocks 14, 15 and 16 comparisons, sawtooth voltage generator 17. The clock generator 18, the inverter 19, the logical unit 20, the key elements, 21 and 22, the reference generator 23, the integrators 24, 25 and 26, the comparator 27 and the reading unit 28. Introduction of the totalizer 31 and 35 of the total signal, the keys 32 and 33, the integrator 34, the differential signal generator 36 and the formation of new connections between the elements of the device i allow the synchronization of the 1Q clock generator in the trunk of all modes of operation of the voltmeter to the sum of the input signals and makes it possible to measure the input signal levels simultaneously with their differential component. 6 Il.

Description

1 The invention relates to electrical measuring equipment and is intended to measure the average differential value of two voltages of arbitrary shape. The purpose of the invention is to increase the sensitivity and enhancement of functionality as a result of using the synchronization of the clock generator in all operating modes of the voltmeter of the sum of the input signals and enabling measurement of the levels of the input signals simultaneously with the measurement of their differential component. Figure 1 shows the functional diagram of the digital integrating voltmeter; figure 2 is a functional diagram of the logic unit; FIGS. 3 and 4 are functional diagrams of the first and second key elements; on fig.Z - timing charts of the clock generator; figure 6 timing diagrams of the voltmeter. The voltmeter contains the first 1 and second 2 controlled attenuators, the first 3 and second 4 keys, the first 5 and second 6 controlled phase shifters, the converter 7 is the phase – code, the third key 8 is the first storage unit 9, the first driver 10 of the differential signal is the fourth 11 and Fifth 12 keys, the first driver of the total signal 13. First 14, second 15 and third 16 comparison blocks, sawtooth voltage generator 17, clock generator 18, inverter 19, logic unit: 20, first 21 and second 22 key elements, reference generator 23, first 24, second 25 and third 26 integrators, comparator 27, readout block 28, sixth key 29, second storage unit 30, second shaper 31 of the sum of the measured signal, seventh 32 and eighth 33 keys, quarter integrator 34, third shaper 35 of the sum signal and second shaper 36 of the difference signal. Signal input of the first control

The attenuator 1 is connected to the first input signal bus, the signal input of the second controlled attenuator 2 via the first switch 3 is connected to the signal input of the first controlled attenuator 1 and through the second switch 4 to the bus of the second input signal, the output of the first controlled output is connected to the start input of the sawtooth generator 17, the first and second outputs of logic unit 20 are connected to 55 first and second control inputs of the first key element 21, and the third and fourth outputs of logic unit 20 to nepB OMj and the second controller2 of the tenuator 1 are connected to the signal input of the first controlled phase shifter 5 and the first input of the converter 7 phase - the code, the output of the second controlled attenuator 2nd sig-. the primary input of the second controlled phase shifter 6 and the second input of the converter 7 phase is the code, the output of which is connected to the control inputs of the first and second controlled phase shifters 5 and 6 through the serially connected third key 8 and the first storage unit 9 5 is connected to the first input of the first driver 10 of the differential signal and through a quarter key 11 to the first input of the first actuator 13 of the sum signal, the output of the second controlled phase shifter 6 is connected to the second input ohm of the first driver 13 of the total signal and through the fifth key 12 with the second input of the first driver 10 of the differential signal, the second inputs of the fourth and fifth keys 11 and 12 are connected to the common bus, the output of the first driver 10 of the differential signal is connected to the first inputs of the blocks 14 and 15, the second input of the first comparison unit 14 is connected to the first input of the third comparison unit 16, the output of the sawtooth generator 17, the first output of the clock generator P via the inverter 19 to the second inputs of the comparison blocks 15 and 16 and the second the clock generator 18, the output of the first generator 13 of the total signal is connected to the third input of the clock generator 18, the direct outputs of the comparison blocks 14-16 are connected respectively to the first, second and third inputs of the logic block 20, and their inverse outputs are from the fourth, fifth and the sixth inputs of the logic unit 20, the seventh, eighth, nine and ten inputs of which are connected respectively to the first, second, third and fourth outputs of the clock generator 18, fifth

Since the honest bits of the R-2R matrix can be chosen sufficiently small, and the frequency of the clock pulses of the reference oscillator 23 is chosen based on the speed of the element base on which the voltmeter is fulfilled, then the accuracy of the correction is determined mainly by the level of the signals at the output of drivers 10 and 13.

The possibility of increasing the transmission coefficients of the formers 10 and 13 with an output level increase circuit is limited by the dynamic range of input signals and the need for the formers to operate in a linear mode.

The converter 7 phase - the code fixes at the output a digital readout proportional to the phase shift 41, introduced by the nonidentity of the channels:

M (, (9)

The introduction of the code (9) into the storage unit 9 through the key 8 completes the step of preliminary correction of amplitude and phase nonidentity. channels.

Before performing the second stage of accurate correction of the amplitude nonidentity of the channels, the second input of the driver 10 through the switch 12 is connected to the output of the phase shifter 6, and the first INPUT of the converter 13 through the switch 11 is connected to the output of the first phase-shifter 5. The first input of the integrator 25 and the input of the integrator 24 through the switch 42 are connected to the output key 46, and the second input of the integrator 25 and the input of the integrator 26 through the key 50 to the output of the key 48, the keys 8-29 are open, the keys 3,4 and 33 retain the previous position.

If we neglect the error of correcting the nonidentity of the phase characteristics of the channels, then after applying signals (3) and (4) to the inputs of attenuators 1 and 2, the outputs of the formers 10 and 13 form the sum and difference signals:

U. (t) t 2uK-K.-V, sinwt; (10) U (t) 2X0 V, sinot, (11)

where u k is the error of preliminary correction of amplitude nonidentity of the channels;

 the transfer coefficient of the first driver 10 differential signal (when using integrated operational amplifiers, it can be quite large).

It uses the ability of operational amplifiers to attenuate the common mode signal and isolate its differential component.

Signals (10) and (11) are fed to the inputs of blocks 14 and 15 of the comparison and to

clock generator inputs 18. /

Further, the change cycle is similar to that described. In this case, the signal V, in Fig. 5, b5, corresponds to the voltage U4. (T), the signal V. shown in

figb5 solid line - voltage and. (t) at (J- (t) О, and the signal V, shown by the dashed line, is voltage 0 (t) at (J. (t) 0.

As a result, when U (t) O pulses. As shown in Fig. 6, B, -g, are formed at the direct outputs of the comparison units 14 and 15, with U (t) 0, the voltage shown in Fig. BB is formed at the output of the comparison unit 15,

and shown in Fig. 62 is at the output of the comparison unit 14.

Comparison unit 16, of direct and inverted sawtooth stresses, forms rectangular pulses (Fig. B).

At the outputs of the tact-oscillator 18, rectangular pulses are formed, shown in Fig. 8b, g, and on the outputs of elements 39 and 40 - pulses, shown in Fig. 6l, ". With U (t) O, the voltage at the output of the logic element 37 corresponds to the voltage shown in Fig. 6, and at the output of the element 38 in Fig. 61C. When U. (t) - O (shown

in FIG. 65, a dashed line is the voltage, e in accordance with FIG. bi is formed at the output of the element 38, and in accordance with FIG. 6 k, at the output of the element 37.

At U. (t) 0, the pulses of FIG. 6a coincide in time with the pulses of FIG. 6A, and the pulses of 6k are from I, JH of FIG. 6m at the input of the logic element 42, and the voltage of FIG. At the output of the logic element 43, the zero level is constantly present.

Claims (2)

With i. (T) with O, a temporary coincidence of the pulses occurs at the inputs of the logic element 43, the signal of fig.bi appears at its output, and at the output kj, - Kg -Ku, the transmission coefficient of the second attenuator 2j kg is the transmission coefficient of the attenuators with N .0; ky is the proportionality coefficient; N + N is a digital code. at the output of the storage unit 30 after correction of the amplitude-phase characteristics of the channels: h digital codes entered into the second storage unit 30 after the first and second this correction. The transmission factors K, and K, depending on the K of the IR, are initially selected based on the dynamic range of the input signals and the linear mode of the device stages. The measurement cycle is set by the clock generator 18. The input signal is the alternating voltage formed by the second shaper 31 of the sum signal, which is the sum of the voltages (3) and (4). At the fifth output of the clock generator 18, start-up pulses (Fig. 6a) of the generator 17 of the reference saw-tooth voltage are formed. The direct reference sawtooth voltage V. is fed to the inputs of blocks 14 and 16 and to the first input of the clock generator 18, and the inverted 1 Vr (fig.bv) is fed to the inputs of blocks 15 and 16 of the comparison and to the second input of the clock generator 18. For example The voltage (3) is applied to the signal inputs of the comparison units 14 and 15, and the voltage (4) to the third input of the clock generator 18. For this mode of operation, the voltage (3) corresponds to the signal V | (fig.B5), and voltage (4) is the signal Vj, in this case the phase shift does not play a role, and in fig.bd it is equal to zero. The direct and inverse outputs of the comparison blocks 14 and 15 and the first second, third and fourth outputs of the generator 18 generate rectangular pulses when the voltage Uj (t) (t), (J5 (t), and (t) is greater than or smaller value of sawtooth voltage. In Fig. 6, the voltages on the right outputs of blocks 14 and 15 are shown in comparison, and in Fig. 6, the first and third outputs of the clock generator 18 are shown. 728 Third comparison block 16 from direct and inverted the sawtooth voltage forms rectangular pulses (Fig. 6a), the signals from the outputs of the 14-16 comparison blocks and the clock the generator 18 is fed to the inputs of the elements 37-40, as a result of which the output voltage of the element 37 has the form shown in fig.bi, the output voltage of the element 38 is the view of fig.bc, the output voltage of the element 39 is the view of fig.bd , the output voltage of the element 40 is a view of FIG. 6m. The voltages shown in FIG. k, k, through the element 41 affect the control input of the key 45, and the signals shown in FIG. 6A, m, through the element 44 - to the control input of the key 49. In this case, the output of the reference generator 23 through the keys 45 and 47 is connected to the first input of the integrator 25 and the input integrator 24, and through the keys 49 and 50 - to the second input of the integrator 25 and the input of the integrator 26. The integrators 24 and 26 are fixed number ;. N,, KvV, N kjK, V, and from the output of the second integrator 25, a digital sample M is taken, N, - N ± KV, (k, -k,), and the sign of the number M is determined by the output signal of the comparator 27 depending on which of the numbers (N, go N) is greater. Through the closed key 29, the code (7) is entered into the storage unit 30, acting on attenuators 1 and 2 in such a way that N UN 2-uK K. where 4N is a digital readout at the output of the second integrator 25, due to the error in correcting the nonidentity of the transmission coefficient U K. The limit of correction accuracy in this case is the increment of the voltage d V at the output of the forma- tor 10 and 13, which occurs during the step of wobble, If we assume that the increment of the transmission coefficients & To attenuators 1 and 2, determined, for example, by the collimator inputs of the second key element 22, the signal inputs of the key elements 21 and 22 are connected to the output of the reference generator 23, the output of the first key element 21 is connected to the input of the first integrator 24 and the first input of the second integrator 25, the output of the second key element. 22 - to the input of the third integrator 26 and the second input of the second integrator 25; the outputs of the integrator 24 and 26 through the comparator 27 are connected to the control input of the second integrator 25, the output connected to the first input of the reading unit 28 and through the serially connected sixth switch 29 and the second memory block 30 — with the control inputs of the first and second controlled attenuators 1 and 2, the control inputs of the keys 3, 4, 8, 11 12, and 29 and the third control inputs of the key elements 21 and 22 are connected respectively to c. the sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, and thirteenth outputs of the clock generator 18, trans. the left and second inputs of the second imager 31 total signal connect-. yen respectively with the outputs of controlled phase shifters 5 and 6, and its output with the fourth input of the clock generator; controls the input of the seventh key 32 is connected to the fourth output of the logic unit 20, the signal input of the seventh key 32 to the output of the reference generator 23, and the output of the seventh key 32 via the eighth key 33 to the input of the fourth integrator 34, the output of which is connected to the first inputs of the third shaper 35 of the sum signal and the second shaper 36 of the difference signal, the second inputs of which are connected to the output of the second inte ratora 25, and the outputs with the second and third inputs of the readout unit 28, the control input of the eighth key 33 is connected to the fourteenth upstream clock 18, Logic unit 20 contains the first 37 - eighth 44 logic elements, the first and second inputs of logic elements 37-40 are the first and fourth, second and fifth, seventh and eighth, ninth and tenth inputs of logic unit 20, respectively, and their third and fourth inputs are the third and sixth inputs of logical unit 20, respectively; the outputs of logic elements 37 and 38 are respectively connected to the first and second inputs of logic elements 41-43, the output of logic element 39 is connected to the third inputs of logic elements 42 and 43 and the first input of logic element 44, the output of logic element 40 is connected to the fourth inputs of logical elements 42 and 43 and the second input of logical elements element 44, the outputs of the logic elements 41-44 are the first, second, third and fourth outputs of the logic unit 20, respectively. The first key element 21 forms the ninth 45, the tenth 46 and the eleventh 47 key signal inputs The keys 45 and 46 are the signal inputs of the first key element 21, the control inputs of the keys 45-47 are respectively the first, second and third control inputs of the key element 21, the outputs of the keys 45 and 46 are connected to the inputs of the key 47, the output of which is The output of the key element 21. The second key element 22 contains the twelfth 48, the thirteenth 49 and the fourteenth 50 keys, the signal inputs of the keys 48 and 49 are the signal inputs of the key element 22, the control inputs of the keys 48-50 are co. Responsibly the first, second and third control inputs of the key element 22, the outputs of the keys 48 and 49 are connected to the inputs of the key 50, the output of which is the output of the key element 22, the voltmeter works as follows. The voltmeter can operate in the following modes, 1, In the mode of automatic correction of non-identical amplitude-phase characteristics of the channels; 2, In the mode of automatic compensation of the phase shift between the input signals; 3, In the measurement mode of the differential component of the input voltages. These modes are controlled using the keys 3, 4, 8, 11, 12, 29 and 33 and the key elements 21 and 22. In each of the listed modes, it is possible to implement an appropriate combination of voltages applied to the control inputs of the keys and key elements from the clock generator 18 and providing the necessary state according to a given program. The operation diagram of the clock generator 18 is shown in FIG. The presence of a positive voltage at the outputs (from the sixth to the fourteenth) of the tactile generator 18 corresponds to the open state of the keys 3, 4, 8, 11, 29 and 33 and the formation of a connection between the input of the key 45 and the inputs of the integrators 24 and 25 through key 47 and between; waiting for the output of the key 49 and the inputs of the integrators 25, 26 through the key 50. In the absence of voltage on the outputs of the clock generator 18, the keys 3, 4, 8, 11, 12, 29 and 33 are closed, the connections between the output the key 45 and the inputs mi of the integrators 24 and 25, the output of the key 49 and the inputs of the integrator 25 and 26, the output of the key 32 and the input of the integrator 34 are broken, in this case, connections are formed between the output of the key 46 and the inputs of the integrators 24 and 25 through the key 47 and the output of the key 48 and the inputs of the integrators 25 and 26 through the key 50. The first mode is auxiliary, performing automatic correction of the nonidentity of the transmission coefficients: the first attenuator input 1 - the output of the key 47 and the input of the second attenuator 2 - the output of the key 50, as well as the automatic correction of nonidentity of the amplitude-phase characteristics of the input paths of the device. In the second mode, the phase shift between the output signals is automatically compensated. This mode is also ancillary to ensure that the accuracy of the measurement of the mean value of the differential component of the input voltages is increased. However, in this mode, the device, taking into account the inadequate changes, can be used as a two-channel voltmeter, which allows measuring the average values of the input voltages, their differential component, as well as the phase shift of the vacuum voltage by the input voltages, these measurements can be carried out alternately or, if necessary, and with appropriate execution of the reading device at the same time. The third mode, taking into account the correction of the amplitude-phase characteristics carried out in the two previous modes, provides increased accuracy and noise immunity of the measurement of the differential component of the input signals. The first harmonics of the signals, the differential component of which is to be measured, have the form: LJ, (t) V, sincot; (1) Ui (t) Y sinCut + Cf), (2) where V | and V is the amplitude values of the signals Ji (t) and Ug (t); C is the relative phase shift between the signals; U 21T - circular frequency. In the mode of correction of amplitude-phase non-identical channels, the signal source (Jr (t) is fed to the input of the first attenuator 1 and through the first key 3 to the input of the attenuator 2. The mode of correction of the amplitude-phase characteristics of the channels is carried out in two stages. Before performing the first stage, the second input of the differential generator 10 and the first input of the generator 13 of the total signal are connected via keys 11 and 12 to the common bus, the first input of the integrator 25 and the input of the integrator 24 are connected via the key 47 to the output of the key 45, and the second input of the integrator 25 and the input of the integrator 26 through the key 50 is connected to the output of the key 49. The keys 4, 8, 29 and 33 are open. If we assume that in the initial state phase shifters 5 and 6 do not introduce a phase shift in the signals passing through them, the transfer coefficients of phase shifters 5 and 6 and the former 10 and 13 are equal to one, and the digital codes at the output of the storage units 9 and 30 - zero, the signals at the inputs of the converter 7 phase - the code and the outputs of the formers 10 and 13 are: UUt) 1, U, (t) - K, V, sinut; (3) U (t), (t) g, sinCcjt -I-AQ), where utf is the phase nonidentity of the input paths; K | -Cd + KyN - the transmission coefficient of the transmission of the first attenuator 1; The element 42 permanently has a zero voltage. Thus, when U (t) About the keys 46 and 47, the reference generator 23 is connected to the first input of the integrator 25 and the input of the integrator 24, while Ll (t) 0 through the keys 48 and 50 to the second input of the integrator 25 and the integrator's input 26. At the output of the second integrator 25, a count is fixed: N 1 2-КЬК Л -V The sign is determined by the output signal of the comparator 27. Entering the code (12) into the storage unit 30 through the key 29 ends the stage of accurate correction of the amplitude nonidentity of the channels. In this case, the correction error, controlled by the code at the output of the integrator 25, can be written into the idea: ± uN -V .. and silt where KK is. - The accuracy of the correction increases as a result of the second stage of the correction. in K times. Before performing the second mode of automatic compensation of the phase shift between the input signals, the signal source Y, (t) is connected to the input of the attenuator 1, and the source UjCt) via the second key 4 to the input of the second attenuator 2, which is simultaneously disconnected by key 3 from the source and, (t). Before supplying the signals (J, (t) and U2 (t), the storage unit 9 is set to the zero state, and the storage unit 30 stores the correction codes of the previous mode. After the signals (1) and (2) are applied to the device inputs of the converter 7, the phase - the code fixes at the output a digital sample proportional to the phase shift Cf: (1 By introducing the code (14), memory 9 provides for compensation of the phase shift (f between signals, and consequently, the sensitivity of the measurement of the differential component of the input signals increases. If is specified By compensating y, it is necessary to measure each of these signals, the preliminary value of their differential component, before executing this stage, the formers 10 and 13 are switched to single-amplifier amplifiers using keys 11 and 12, and the input of the reading unit 28 is connected to the output of the integrator 24, 26 or 25. The key 33 remains in the closed state Based on the vector diagrams of the sum of the signals (1) and (2), it is found that the amplitude of the total signal at the input of the clock generator 18 to the values of the phase shift between the signal E U | (t) and (i (t) f to 90 ° over a larger signal value that provides reliable operation at lower levels of one of the signals. After performing corrections in previous modes, the voltmeter is ready to accurately measure the differential component of the input signals. For this, the shapers 10 and 13 are switched to the differential and sum signal formation mode using the keys 11 and 12, the storage units 30 and 9 store the amplitude non-identity correction channels and the phase shift between the signals. The keys 47 and 50 are shifted to the position of the second stage of the accurate correction of the amplitude nonidentity of the channels, and the key 33 to the open state. As a result of a measurement cycle similar to that described in the second correction stage, the integrator 25 fixes a digital sample at its output proportional to the average value of the differential component of the input signals, carrying information about its sign, and integrator 34 - a digital sample proportional to the average sum of the input signals. Using the output codes of integrators 25 and 34, as well as the formulas: y, + Ui y, - and. Ut - - - and. + Uj U, 2a, the output of the generator 35 of the total signal and, therefore, the reading of the block 28 appears a signal proportional to the average value 131 of the voltage (1), similarly at the output of the driver of the differential signal 36 and the reading block 28 - a signal proportional to the average value of the voltage wives (2). Thus, the voltmeter has an increased sensitivity to the levels of the input signals and allows simultaneously with the measurement of their differential component to measure the levels of both signals. The Digital Integration Voltmeter containing the first and second controlled attenuators, the signal input of the first controlled attenuator is connected to the first input signal bus, and the signal input of the second controlled attenuator is connected via the first key to the signal input of the first controlled attenuator and through the second key bus of the second input signal, the output of the first controlled attenuator is connected to the signal input of the first controlled phase rotator and to the first input of the converter the phase - , the output of the second controlled attenuator - to the signal input of the second controlled phase rotator and to the second, the converter input phase - code, the output of which is connected through the serially connected third key and first storage unit to the control inputs of the first and second controlled phase shifters, output the first controlled phase shifter is connected to the first input of the first shaper of the difference signal and through a quarter key to the first input of the first form. worldr of the sum signal, the output of the second controlled phase shifter is connected to the second input of the first shaper of the sum signal and through the fifth key - the second input of the first shaper of the difference signal, the second inputs of the fourth and fifth keys are connected to the common bus; the output of the first shaper of the difference signal is connected to the first the inputs of the first and second comparison units, the second input of the first comparison unit is connected to the first input of the third comparison unit, with the output of the sawtooth generator 72, with the first the input of the clock generator and through the inverter with the second inputs of the second and third comparison blocks, and the second input of the clock generator, the output of the first generator of the sum signal is connected to the third input of the clock generator, the direct inputs of the first, second and third comparison blocks are connected respectively to the first, the second and third inputs of the logic block, and their inverse outputs with the fourth, fifth and second inputs of the logic block, the seventh, eighth, ninth and tenth inputs of which are connected respectively to the first The second, third, and fourth outputs of the clock generator, the fifth output of which is connected to the trigger input of the sawtooth generator, the first and second outputs of the logic unit, respectively, are connected to the first and second control inputs of the first key element, and the third and fourth outputs of the logic unit - to the first and second control inputs of the second key element, the signal inputs of the first and second key elements are connected to the output of the reference generator, the output of the first key element is connected to the input of the first integrator and the first input of the second integrator, the output of the second key element to the input of the third integrator and the second input of the second integrator, the outputs of the first and third integrators are connected via a comparator to the control input of the second integrator, output connected to the first input of the reading unit, and sequentially connected sixth key and second storage unit with control inputs of the first and second controlled attenuators, control inputs of the first, second, third, fourth, nth About, and the keys and the third control inputs of the first and second key elements are connected respectively to the sixth, seventh, eighth, ninth, tenth, eleventh, twelfth and thirteenth clock generator outputs, characterized in that, in order to increase the sensitivity and expand the functional capabilities, it introduced the second and third formers total 1512672 the second signal generator, the seventh and eighth keys, and the fourth integrator, the first and second inputs of the second generator of the sum signal being connected to the outputs of the first and second controlled phase shifters, and their output to the fourth input of the clock generator; the seventh key input is connected to the fourth output of the logic block, the seventh key signal input is connected to the output of the reference gene7216 RATOR, and the output of the seventh key through the eighth key is connected to the input of the fourth integrator, the output of which is connected to the first inputs of the third shaper of the sum signal and the second shaper of the difference signal, the second inputs of which are connected to the output of the second integrator, and the outputs to the first and third inputs of the reading unit , while the control input of the eighth key is connected to the fourteenth output of the clock generator. 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