SU955512A1 - Digital filter - Google Patents

Description

The invention relates to computing and can be used in digital signal processing systems.

A digital filter is known that contains two cyclic memory blocks, whose outputs are connected to the inputs of a multiplier, the output of which is connected to the input of an accumulating adder connected to the output bus of the filter. The counting of the output process in this device is performed by sequentially reading from the cyclic memory blocks the codes of the samples of the input process and the filter coefficients, which are multiplied at the multiplier. Intermediate products are accumulated in the adder. At the end of the N-ro calculation cycle, the output of the output process is taken from the output of the adder. Countdown time is t Nt

where tuM is the time to calculate the product

Sloan I of two numbers 1.

A disadvantage of the known device, as well as devices in which the product is calculated on a small number of multipliers, is that for calculating one sample

convolutions take considerable time, since multiplications are performed on the same equipment, which takes time equal to

N

t

M

 where M and the number of multipliers.

The number of multiplications per unit is time 10 and is not equal to N / T, where T is the sampling period of the input process.

Closest to the present invention is a digital filtering device, filtering signals in which

15 when odd N is performed in accordance with the formula

UY, YOCHD) (n. + x „.2,) + Id, Hn-m,

where h - impulse coefficients

20 digital filter characteristics with linear phase;

we .

Iri

N is the order of the filter.

Claims (2)

25 This device contains a memory block of the impulse response coefficients h (i), the first input of which is the input of the array of numbers h (i), the second input and the output are connected to the output of the address counter and the input of the first register, respectively, the output of the first register is connected to the first the input of the multiplication device, connected by its output to the input of the accumulating adder, the output of which is connected to the input of the D / A converter, the second input of the multiplication device is connected to the output of the adder, the first and second inputs of which It is connected to the outputs of the second and third registers of its registers, respectively / the first and second memory blocks of the input samples, the first inputs connected to the second and third address counters, respectively, and the second inputs to the outputs of the fourth and fifth registers and the first input of the fourth register, second input which is connected to the output of the first memory block of input samples, the first input of the third register is the input of the filter, and the second input is a third of its register and the input of the second register is connected to the outputs of the second and first memory blocks and input samples, respectively 2. The disadvantage of this device is low speed, due to unproductive expenditure of time to perform a shift in the array of input samples and a large number of multiplications per unit time required to form the output signal. The purpose of the invention is the behavior of a digital filter. The goal is achieved by the fact that a digital filter containing a memory block, the first input of which is pofo is an information input of the filter, a multiplier whose output is connected to the input of an accumulating adder, the output of which is the output of the filter, the coefficient memory, the first output of which connected to the first input of the multiplier; the first counter, the input of which is connected to the overflow output, is the second of the counter, the clock input of which is connected to the output of the pulse burst generator, the input of which is the start input of the filter, entered The first and second multiplexers, an adder, a comparison unit and a ranking unit containing the first and second counters, a register, an OR element and an element and, whose output is connected to the input of the first counter and the ranking unit, whose output is connected to the first input of the memory coefficients, the second output of which is connected to the first input of the adder, the output of which is connected to the second input of the memory unit, the output of which is connected to the first input of the first multiplexer, the output of which is connected to the second input of the multiplier OR output the ranging unit is connected to the first input of the element AND the ranging unit, the second input of which is combined with the input of the second counter of the ranking unit and is the digital filter synchronization input, the output of the second counter of the ranking unit is connected to the input of the first register group, the inputs of the second group of which are connected to the corresponding inputs of the element OR and are the inputs for setting the filter coefficients, the register output is connected to the control input of the pulse burst generator, the first input of the second multiplexer and the first The input of the comparison unit, the output of which is connected to the input of the second counter, the third input of the memory unit and the second input of the first multiplexer, the third input of which is an information input of the filter, the output of the second counter is connected to the second input of the comparison unit and the second input of the second multiplexer, whose output connected to the second input of the coefficient memory, and the output of the first counter is connected to the second input of the adder. FIG. 1 shows a functional diagram of the device; in fig. 2 is the same ranking block. The device contains filter input 1, memory block 2 (input samples), first multiplexer 3, multiplier 4, filter output 5, adder b, first counter 7, coefficient memory block 8, second multiplexer 9, ranking block 10, generator 11 packs pulses, comparison unit 12, second counter 13, start input 14, synchronization input 15, filter coefficients input 16, accumulating adder 17. The ranking block contains two counters 18 and 19, AND 20 element, OR 21 element and register 22. Digital filter works as follows. Before filtering begins, the coefficients of the impulse response are loaded into the coefficient memory block 8. The maximum length of the loaded impulse response is N + 1, where N is an integer power of 2. coefficients h; arrive at the input 16 of the recording of the coefficients of the filter sequentially in time, starting with the coefficient h and ending with the coefficient HO. Each coefficient is accompanied by a synchronization pulse arriving at the synchronization input 15. The ranking unit 10 records in block 8 only such samples h that are not equal to zero, the latter are recorded in block 8 further by address received from the output output of the ranking unit 10 through multiplexer 9 to the address input of block 8, and the count Lc is written to zero address. In ranking block 10, for each sample hj, its index number a is recorded, which is recorded together with the corresponding coefficient h; in block 8. For this purpose, each word of block 8 is divided into two floors. In the field corresponding to the first output of block 8, an index number is written, and the corresponding coefficient h, - in the field corresponding to the second output of block 8. At the same time, m coefficients b, 1, ..., h (j, not equal to zero , have the following index numbers: a ((0, a, 2 7 t 3 (. This formation of the index number is done by calculating modulo N N + 1 synchronization pulses, accompanying N + 1 coefficients h ;. The number of synchronization pulses arriving at synchronization input 15 is always equal to N + 1. If the length of the filter characteristic is less than the maximum, for example measures for k samples, the first non-zero zero Lt. |; h and its index number k will be recorded at the zero address in block 8. Next, the loading procedure of block 8 is similar to the case of the maximum characteristic having N + 1 counting. In block 8, m samples are recorded, hjj, (whose values are not equal to zero, together with their own index numbers. In this case, a code equal to t -1 is generated at the address output of the unit 10 of Groani's wounds). This code is controllable to the generator for the 11 pulse bursts generator and adjusts it to form a burst of m pulses after starting, simultaneously, during the filtering process, it is compared in comparison block 12 with the current code value at the output of counter 13. When at the output of counter 13 a code is set equal to t-1, which corresponds to the t-th state of the counter, at the output of the comparator unit there appears a signal allowing the reset of the counter 13 when it enters its counting input of the next pulse. In this case, a pulse appears at the transfer output of the counter 13. Thus, during the filtering process, the counter 13 operates modulo m. The filtering process consists in calculating the convolution samples of y (n) using the formula n Vi, Xp.Ih, Kf,. ,,. . , i.2 Mm-i 0 where n is the current number of the output sample; hj - coefficients of the impulse response of the filter; . Xj, - input signal samples; i, i, f are the numbers of the coefficients h, m-i and are not equal to zero. Dp calculation of each sample y (p) filter performs m operations calculating private products of the form ™ operations cy 1 my. In the filtering mode, filter x, x, .., x are sent to the input 1 of the filter with a sampling interval of 4. Each sample is accompanied by a pulse arriving at the launch input 14. By the time each input sample arrives, the accumulator t-1 li, accumulates in accumulator 17. PMK npvi IT counter 13 is in the state t-1. The arrival of a reference x p on the filter input 1 bus is accompanied by the start of the generator 11 bursts of pulses. The first clock pulse of the packet transfers the counter 13 to the m state, and the code at its output becomes equal to t-1 and through the multiplexer 9 arrives at the address input of the coefficient memory unit 8. At the address indicated by the counter 13, the readout hj is read and the index number from block 8. The read count h is fed to the second input of multiplier 4. Simultaneously, the compare block 12 selects the m state of the counter and generates a signal at its output that transfers the block 2 of the input sample memories to the recording mode and connects through multiplexer 3 Inu input filter 1 to the multiplier 4. Received input. Count Xf is loaded into memory block 2 of the input samples at the address generated at the output of the N-bit combinational adder 6, which calculates the sum of code A received from the output of counter 7 and the index number ad. Since, the load of reference x is made at the address Af ,. At the same time, the count x, through multiplexer 3, goes to the first input of multiplier 4, to the second input of which count h is received, from block 8. the multiplier 4 calculates the product hpX, which is then summed with the factor 17 with the accumulated sum t-1 works kind of. Thus, at the end of the clock cycle allocated by the comparator unit 12, the output count of the pack is formed at the output 5 of the filter. When the second clock pulse arrives, a code equal to zero is generated at the code output of counter 13, and a signal arriving at the counting input of counter 7 appears at the output of the overflow, and the code A p is generated at the output. is transferred to the read mode, and its output through multiplexer 3 is sent to multiplier 4. The counts h ,, and x ". 4-1 / read out from block 8 of the coefficient memory and 2 memories of the input counts, go to multiplier 4, where is calculated the product P P -h; X 1. (J 4 m At the same time, the output n the sum adder 17 forms the partial sum Sj 5, P ,. The address for counting X |,. 4 is formed at the output of cyM.iaTopa 6 in the form (Af, + l + aj) mod N. In the third cycle, the product k is calculated in a similar way the partial sum m of clock in the adder 17 forms the partial sum S. Sm-2 + mf On receipt of the reference Xp, .-) bus in yes 1 of the filter in the multiplier 4, the product is calculated by the subsequent addition with the accumulated sum Sfn- ,. As a result, at the output 5 of the filter, the output count Ynfji-i gp 5 1- + hoXn4 is formed. Simultaneously received countdown Xn. written to block 2 of memory, input samples to the reference point of the incoming filter at N sampling intervals earlier. The ad load count x is (A + l + ac,) mod N (A.) ModN, a |, 0. Indeed, the incoming samples are loaded into memory block 2, the input samples in the following order: XQ at address (A) mod N, x at address (A -I- 1) mo, d N,. . . , xN at (modN), at (A + 1) mo (A + 1) modN. Thus, the input count Xf arrived at the end of the count x. In this case, at the output of the filament, in the case of a characteristic with a length of N + 1, an extremal sample YN, hi, + .-- fXyh (, is formed. If the characteristics are shorter than the maximum by k samples, then the sample is extreme. Thus, the process is calculated at the next convolution value The sum is made up of the following shift operations by one array of input counts. Xg, relative to the array of coefficients, produced at the beginning of the calculation of the output sample Un by increasing by one the compressing counter 7, calculating the weighted sum of the input samples x with unequal zero. coefficients. In this case, the samples x are selected from block 2 of the input sample memory using index numbers a ;, which indicate the counts h on the output counter code 7, corresponding to the coefficients h. At the end of the calculation, the next sample is loaded. to the reference point X (,. у. In this case, the loading and calculation with the accumulation of products hg are combined in time. The ranking unit 10 operates as follows. Before the load of the coefficient memory block 8 is started, the triggers of the counters 18 and 19 are set to one. H coefficients; arrive at the input 16 of the recording coefficients of the filter, and the corresponding clock pulses - to the input 15 of the synchronization. The coefficients h arrive at the input, starting with the highest numbers. The number of sync pulses is always N + 1. If the length of the filter characteristic by k samples is less than the maximum, then the first non-zero coefficient has the number hf (.) I and is accompanied by the k-th sync pulse. If the received coefficient h is not zero, then an output signal is generated at the output of the OR element 21, and the corresponding sync pulse passes through the AND element 20 to the counting input of the counter 19i. The coefficient h selected so is written to the register 22 together with its index number. The index number is generated at the output of the counter 18, operating modulo N, by counting the number of incoming clock pulses. In block 8 of the coefficient memory, the order of the non-zero coefficients h is recorded in the order of receipt from the output of register 22 ;. with their index numbers. The address of the entry is indicated in the contents of the counter 19. Thus, the m coefficients h, -, h, 2, unequal to zero are. . . , h (m., with the corresponding index numbers 11 a;, im-i. and 0 is recorded in block 8 of the coefficient memory at addresses A ,, (0, 1, ...,. Thus, in the proposed device, time consuming the calculation of each y (n) is determined not by the length of the filter characteristic, but by the number m of its zero coefficients h;. The calculation time y (n) in the proposed device is tm (t + + Chzu where m is the number of np zero coefficients tijM 5. tjj , - the execution time is multiplied, the summation and the access to the memory are appropriate. The calculation time y (n) in the prototype is t 7 tijM + tj) + Nto, y, g de N is the length of the characteristic. Comparison of the computational costs of the known and proposed devices shows that, for example, when t j, the speed of the proposed device is higher. In addition, unlike the prototype, the proposed device can work with both symmetric and asymmetric pulsed Characteristics of the invention: A digital filter comprising a memory block whose first input is with the information input of the filter, a multiplier whose output is connected to the input of an accumulating accumulator whose output is the output of the filter, the coefficient memory, the first output of which is connected to the first input of the multiplier, the first counter, the input of which is connected to the overflow output of the second counter, the clock input of which is connected to the output of the pulse burst generator, the input of which is the start output of the filter, different that, in order to improve the speed, the first and second multiplexers, an adder, a comparison unit and a ranking block containing the first and second counters, the register, the OR element and the AND element, whose output with Connected to the input of the first counter of the ranking unit, the output of which is connected to the first input of the memory block: coefficients, the second output of which is connected to the first input of the adder, the output of which is connected to the second input of the memory block, the output of which is connected to the first input of the first multiplexer, whose output connected to the second input of the multiplier, the output of the OR element of the ranking unit is connected to the first input of the AND element of the ranking unit, the second input of which is combined with the input of the second counter of the ranking unit and is in digital filter synchronization ode, the output of the second counter of the ranking unit is connected to the input of the first register group, the inputs of the second group of which are connected to the corresponding input of the OR element and are inputs of the filter coefficients, the output of the register is connected to the control; the input of the second multiplexer and the first input of the comparison unit, the output of which is connected to the input of the second counter, the third input of the memory block and the second input of the first multiplexer, the third input Filter information is input, the second counter output is connected to the second input of the comparator and a second input of the second multiplexer, the output of which is connected to a second input of the memory coefficients, wherein the first counter output is connected to the second input of the adder. Sources of information taken into account in the examination 1. Rabiner L., Gould B. Theory and application of digital processing}}. Monk, M., Mir, 1978, p. 601 2. Authors certificate of the USSR 636616, cl. G 06 F 15/34, 1976 (prototype). t / f.i Uz