SU943710A1 - Accumulating adder with carry memory - Google Patents

Description

one

The invention relates to digital computing and can be used to construct arithmetic devices of newer computers.

Known accumulators are adders, which include trigger accumulating and receiving registers and AND and IDN elements necessary to implement the logic of the adder. The reception () register of such adders is used not only to receive the terms, but also participates in the performance of the addition in the logic of the organization of the transfer of nz low-order bits to the older G11 and 2 .ts

The closest to the purchase of a moo is a transfer accumulation adder, containing in each bit a 1-numbered trigger and aa pomignac transfer trigger, elements AND and OR ,. 20, the delay element, the first input of the right AND element, is connected to the input of the corresponding bit of the term. adder and the second input - with control shiva

write the adder term, the transfer output of the counting trigger is connected by a single input of the transfer memory trigger, the first input of the second element AND is connected to the transfer control bus of the adder, and the output is connected to the first viola of the first element OR, the output of which is connected to the transfer output for the next-second discharge the adder, the output of the first element is connected to the first input of the second element OR, the other input of which through a delay element is connected to the transfer input from the previous discharge of the adder, which: is also connected to the first input m of the third element And, the second input of which is connected to a single output of the countable tr of the year, the input is connected to the output of the second хhümevta% LI, the output of the third epemuth And connecting to the second input of the first alamevt OR, the second input of the second apem. transferring the first input of which, having connected to the control terminal of the settings of the adder, the unit and zero outputs of the counting trigger are connected to the direct and inverse outputs of the sum of this bit of the adder GZ. However, the device is characterized by insufficient speed, compressed with the presence in each discharge of the sum of the torus of the delay element AND with a special tact of zeroing the transfer memory triggers. The aim of the invention is to increase the speed of the adder. The goal is achieved by the fact that in a nakapivak adder with memory transfer containing a digit trigger in each bit, a transfer memory trigger, elements AND and OR, the first input of the first AND is connected to the input of the corresponding bit of the addendum number, and the second input is with the control bus of the recording of the adder term, the first transfer output of the counting trigger is connected to a single input of the transfer memory trigger, the first input of the second element I is connected to the transfer control transfer string, and the output with the first input of the first element OR, the output of which is connected to the transfer output in the subsequent discharge, the output of the transfer transfer trigger is connected to the first input of the second OR element, the output of which is connected to the second input of the second element AND, the output of which is connected to the second input of the second element OR and with the zero input of the transfer of memory transfer, the second input of the first element OR is connected to the second transfer output of the counting trigger, the first input of which is connected to the output of the first element AND, and the second input to the transfer point and the previous bit of the adder, the unit and zero outputs of the counting trigger connected to the outputs of this bit of the adder, the counting trigger contains ten AND-NOT elements, the outputs of the first and second of which are respectively the unit and zero outputs of the counting trigger, the output of the first element AND NOT connected to the first outputs of the third and fourth elements AND-NOT, the output of the second element AND-NOT connected to the first inputs of the fifth and sixth elements AND-H The outputs of the third and fifth elements AND-H are connected to the first inputs But the seventh and eighth NAND elements, the second inputs of which are the First input of the counting trigger, the output of the 7th NAND element is connected to the input of the first NAND element, the second inputs of the third and fifth NAND elements and. the third input of the eighth NAND element, the output of which is connected to the first input of the second NAND element and the third inputs of the third, fifth and seventh NAND elements, the outputs of the fourth and sixth NAND elements are connected to the first inputs of the ninth and ten, respectively addition of the NAND elements, the second inputs of the KOTOjbix are connected to the second input of the counting trigger, the output of the ninth element of the NAND is connected to the second inputs of the first, fourth and sixth elements of the NAND and the third input of the tenth element of the NAND whose output is connected with the second input of the second email And-NOT elements and the third inputs of the fourth, sixth and ninth elements AND-NOT, output / c 1 of the first and second elements AND-NOT are connected to the third inputs of the second and first elements, AND-NO, the outputs of the eighth and tenth elements of AND- NOT connected respectively to the first and second transfer outputs of the counting trigger. FIG. 1 is a functional diagram of two bits of the accumulating adder; FIG. 2 - counting trigger scheme. The accumulating adder contains in each bit a counting trigger 1, a transfer memory trigger 2, the element AND 3, an element OR 4, the element AND 5, an element OR 6, the Counting trigger is built on ten elements AND-HIt 7 - 16. The first transfer output of the counting trigger 1 is connected to a single input of transfer transfer memory 2 trigger. One input. element 3 is connected to the input of the corresponding bit of the adder's addendum, the other input is connected to the control line of the recording of the addend, and the output is connected to the input of the counting trigger 1. One input of the element OR 4 is connected to the single output of trigger 2, and the other input is connected to the output of the element And 5, one input of which is connected to the element OR 4, and the other input - from the control transfer ring of the adder. One input of the element OR 6 is connected to the output of the element AND 5, the other entrance to the second transfer output of the counting trigger 1, and the output to the transfer output to the subsequent accumulator discharge. The second input of the counting trigger 1 is connected to the transfer input from the previous accumulator of the adder. Counting trigger 1 is an asynchronous counting trigger with two separated counting inputs and corresponding transfer outputs. The construction of the counting trigger 1 using the elements AND-NOT 7-16 is shown in FIG. 2. When executing an operand, the summator works in a slower way. Let trigger 1 be the code of the first addend. In the first cycle of the adder operation, the second term is written through the elements of AND 3, when a pulse is applied to the control bus of the record, the addition of two numbers along rTiod2 occurs and the transfer pulse, which occurs when the two units are added, closes. trigger 2. In the second cycle of the operative addition, the impulse applied to the transfer control panel onpa sews the element AND 5 and in the unit state of the 2-digit trigger of the adder the pulse passes through the element AND 5 and OR 6. If the trigger 1 is of the next row of the adder is in state 1, then the transfer pulse of the previous discharge of the adder flips this trigger 1 to O and is allocated at the transfer output, which is connected to the second by the input of the OR element of this bit of the adder, and from the output of the OR element 6, the pulse passes to count input trig EPA 1 of the next discharge, and so on. d. organizuets Since the adder circuit through carry from the least significant bit in senior Moreover transfer pulse can vits on only one of the inputs of OR 6, any discharge of the adder. The result of adding two numbers is obtained recorded on the meter triggers after the end of the propagation of transfers through the bits of the adders. In this adder, when performing multiple additions, it is not necessary to enter a separate cycle for zeroing transfer transfer triggers, since this zeroing is carried out in the second cycle by a pulse, separated from the output of AND 5, and to maintain the initial potential 1 at the output of the AND element 5, required to form a pulse of the same duration as a beat. the transfer, the OR 4 element is applied, the input of which is associated with the single output of trigger 2, and the second input with the output of the AND 5 element. Such a scheme allows organizing the previous state at the input of the AND 5 element using potential electric amps The time of the pulse on the transfer control bus. The proposed adder has a slightly increased speed due to the absence of a tact of zeroing the triggers of memory transfer and the rejection of the use of delay elements. Equation formula 1. Transfer accumulator with memory transfer, containing p each bit a counting trigger, transfer memory trigger, elements AND and OR, with the first input of the first element AND connected to the input of the corresponding bit of the summation adder, and the second input from the control recording bus ala-. first accumulator of the counting trigger is connected to the single input of the pareno memory trigger, the first input of the second element is connected to the transfer control of the adder, and the output is connected to the first input of the first element OR, the output of which is connected to the transfer output to the next d, in order to improve speed, the output of the transfer memory trigger is connected to the first input of the second OR element, the output of which is connected to the second input of the second element AND, the output of which is connected to op "1M input of the second element OR, and with the zero input of the transfer memory trigger, BTCV input of the first element OR is connected to the second output, transfer of the counting trigger, the first input of which is connected to the output of the first element AND, and the second input to the transfer input from the previous bit of the adder, the unit and zero outputs of the counting trigger are connected to the outputs of this bit of the adder. 2. A dispenser according to claim 1, wherein the counting trigger cor holds ten NAND elements, the outputs of the first and second of which are 1, respectively, the unit and zero} counts of the counting trigger, of the first element of the NAND is connected to the first inputs of the third and fourth elements of the NAND, the output of the second element of the NAND is the same as the first inputs of the fifth and second elements of the NAND, the outputs of the third and fifth elements of the NAND are connected to per vamn vkodamv respectively sailed

and the eighth IS-NOT element, the second ones of which are the first inputs from the one trigger, the output of the seventh AND-NOT element is connected to the first input of the first IS-NOT element, the second inputs of the third and fifth NAND elements and the third input of the eighth NAND element, the output of which is connected to the first input of the second NAND element, and the third inputs of the third, fifth and seventh NAND element, the outputs of the fourth and sixth NAND elements are connected to the first inputs of the ninth and of the tenth element NAND, the second inputs of which are connected to the second th counting trigger input, the output of the ninth AND-NO element is connected to the second inputs of the first, Thu VERT and sixth AND-NO element and to third vhodstl tenth AND-NO element,

the output of which is connected to the second input of the second NAND element and the third input of the fourth, sixth and ninth NAND element, the outputs of the first and second NI element are connected to the third inputs of the second and first NAND elements, respectively, the eighth and The tenth element of the NAND is NOT connected to the first and second transfer outputs of the counting trigger, respectively.

Sources of information taken into account during the examination

1. USSR author's certificate number 351214, cl. G, 06F 7 / 5O, 1972.

2. USSR author's certificate No. 531157, cl. G06F 7 / 5O, 1974.

3.P. K. Richard Arn4meticheskie one- rashga on digital computers. M., IIL, 1957, p. 115119 (prototype).

giuHO Record of the number 1CSCH h S№№сс КИ + 1} 0 Bus „Transfer the transfer Om (i-l) p

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Claims (3)

Claim 1. An accumulating adder with transfer memory, containing a counting trigger, a transfer memory trigger, AND and OR elements in each category, • the first input of the first AND element being connected to the input of the corresponding digit of the adder term, and the second input to the control bus write-at. of the adder, the first transfer input of the counting trigger is connected to a single input of the transfer storage trigger, the first input of the second AND element * is connected to the control transfer bus of the adder, and the output is connected to the first input of the first OR element, the output of which is connected to the transfer output to the next discharge, whereby, in order to improve performance, the output of the transfer storage trigger is connected to the first input of the second OR element, the output of which is connected to the second input of the second AND element, the output of which is connected to the second the input of the second OR element, and with the zero input of the trigger for storing the transfer, the second input of the first OR element is connected to the second output. ", transfer the counting trigger, the first input of which is connected to the output of the first AND element, and the second input to the transfer input from the previous discharge the adder, the single and zero outputs of the counting trigger are connected to the outputs of this discharge adder. 2. The adder in π. 1, with the fact that the counting trigger of the cell holds ten AND-NOT elements, the outputs of the first and second of which are ι respectively the single and zero outputs of the counting trigger, the output of the first element And NOT connected to the first inputs of the third and fourth AND-NOT elements, the output of the second AND-NOT connected * is connected to the first inputs of the fifth and sixth AND-NOT elements, outputs (the third and fifth elements AND NOT connected to the first * inputs respectively seventh 7 943710 8 and the eighth AND-NOT element, the second inputs of which are the first input of the counting trigger, the output of the seventh AND-element is connected to the first input of the first AND-element, the second inputs of the third-5th and fifth AND-NOT elements the third input of the eighth AND-NOT element, the output of which is connected to the first input of the second AND-NOT element, and the third inputs of the third, fifth and seventh AND-NOT elements 10, the outputs of the fourth and sixth AND-NOT elements are connected to the first inputs of the ninth and tenth respectively NAND elements whose second inputs are connected with the second input of the counting trigger-ts ger, the output of the ninth AND-NOT element is connected to the second inputs of the first, fourth and sixth AND-NOT elements, and the third input of the tenth AND-NOT element, the output of which is connected to the second input of the second AND-NOT element the third inputs of the fourth, sixth and ninth AND-NOT elements, the outputs of the first and second AND-NOT elements are connected to the third inputs of the second and first AND-NOT elements respectively, the outputs of the eighth and tenth AND-NOT elements are connected to the first and second outputs, respectively transfer counting trigger.