SU935969A1 - Digital polygonal approximator - Google Patents

Description

() DIGITAL POLYGONAL APPROXIMATOR

I

The invention relates to computing technology, namely to digital functional transducers of unit codes based on polygonal approximation and can be used as a specialized calculator in channels of digital control and control automation for processing frequency signals q 1 chi, in frequency generators with digital setting a function, etc.

A device for reproducing functions, including inverse ones, based on piecewise linear approximation and providing an even quantization step on the output ll will be known.

A disadvantage of the prior art is the limited accuracy associated with the storage capacity.

Closest to the invention in its technical essence is an approximator comprising a generator.

Claims (2)

KEY, divisor and argument counter, divider and approximation step counter, binary multiplier and function counter, storage register, delay element, and controllable dividers. The known device provides a polygonal approximation for a large number of areas without using fz J. memory devices. However, rather small error-10ness is provided in the field of large values of the argument and, accordingly, large approximation step numbers. At the beginning of the range of operation, there is a significant error, for example, at the first section of the linear approximation, the function is doubled, and at the second section - by half. This creates difficulties in the operation of the device in the region of small values of the argument. To obtain a small error in the region of small values of the argument, it is necessary to significantly increase the scale 93 of the mis-pulse representation of the variables so that a sufficiently large step number falls on the required value of the argument. For processing information signals, this technique is of little use, since it is necessary either to increase the speed of the circuit, or to work out the function in real time. The purpose of the invention is to increase the accuracy in the field of small values of the argument. The goal is achieved by the fact that the 8 approximator contains a pulse generator, a key, an argument divider, an argument counter, a segment counter, a delay element, a length divider sections, a register, a binary multiplier and a subtracting function counter, the pulse generator output via a key, the divisor argument The argument and the argument counter are connected to the key stop input, the start input of which is connected to the input of the approximator, the output of the section length divider is connected to the register entry input, whose information input is through the counter the coder and the auxiliary unit is connected to the output of the section length divider, the output of the binary MIND knife is connected to the subtractive function counter, the first and second binary-decimal multipliers are additionally introduced, and the key output is connected to the information input of the first binary-decimal multiplier, the output of which connected to the input of the second binary multiplier, the output of which is connected to the inputs of the section length divider and the binary multiplier, the control inputs of the first and second dual decimal multipliers are connected to responsibly vkodami register and counter sections made subtractor. The drawing shows the block diagram: device. The multiproxator contains a generator of 1 pulses, a key 2, a divider 3 arguments, an argument counter k, a divisor 5 of the length of the section, a delay element 6, a subtracting counter of 7 sections, a register 8, a binary-multiplicator 9 and 10, a binary multiplier 11, a subtractive counter 12 functions, input 13 start input 14 stop approximation mator. 4 The device works as follows. Before starting, the conversion factor of the argument counter 4 is set to the required value of the argument; the number m is entered into the subtracting area counter; the number V is entered into the subtracting function counter at the required scale; register number 8 (t-1). The input 13 is given a signal that unlocks the key 2, with the result that the inputs of the divider 3 argument and the binary-decimal multiplier 9 receive counting pulses from the output of the generator 1. At each of the sections of the polygonal approximation, the angular coefficients are determined 1; t-and (t-i- / |) expression K -; jj --- as a result of which interpolation nodes are located on a given function, which is explained by the following numerical example for m 10. ZJZ: il..§. i§: l) -5.L5: 1) 10 10 10 10 10 10 In the section of a two-fold change in the value of the function, you have five links of the polygonal function, while in the known device there is one link, which reduces the error by almost two orders of magnitude and makes it preferable to use the proposed device in the field of small values of the argument. The invention includes a digital polygonal approximator containing a pulse generator, a key, an argument divider, an argument counter, a segment counter, a delay element, a length length divider, a register, a binary multiplier, and a subtracting function counter, the output of the pulse generator through the key, the argument divider, and the argument counter are connected with the key stop input, the start input of which is connected to the input of the approximator; The delays and the delay element are connected to the output of the section length divider, the output of the binary multiplier is connected to the input of the subtractive function counter, characterized in that, in order to improve accuracy, the first and second binary decadal multipliers are entered into it, and the output of the key is connected to the information input first binary decimal multiplier, the output of which is connected to the input. the second binary-decimal multiplier, the output of which is connected to the inputs of a section length divider and a binary; the multiplier, the control inputs of the first and second binary-decimal multipliers are connected respectively to the outputs of the register and the count of the segments; performed subtractive. Sources of information taken into account at. examination 1. Brago E, N. Methods and devices for processing measurement information. M., Nedry, 1976, p.58, fig. 25 2. USSR author's certificate. No. 538367, cl. G About F, 1976 (prototype), ei 12 f-l ff 1L