SU426318A1 - FREQUENCY CONVERTER TO CODE - Google Patents

Description

one

The invention relates to the field of computational and digital measuring equipment and they are used to convert frequency into a code, as an input device for a digital computer, or as an integral part of a pulse-frequency computing device.

According to the main author. St. No. 310382 known frequency converter in the code.

The aim of the invention is to increase the conversion speed.

This is achieved by introducing an additional reversible counter and binary multiplier into the proposed converter, a group of pulse-potential matching circuits and a multiplier of frequency-pulse signals, the signal input of which is connected to the output of the assembly circuit, the control input, with the outputs of a group of pulse-potential coincidence circuits, one output - with the input of the synchronization device, and the second output - with pulse inputs of a group of pulse-potential coincidence circuits, moreover, the potential inputs of the last are connected to zero vym outputs bits except Jr., additional down counter, individual bits of which outputs are connected to inputs of an additional binary multiplier, and its output is connected to an additional input of subtractor down counter.

the input of which is connected to the output of the assembly circuit.

Pa drawing presents the scheme of the proposed Converter.

The frequency converter in the code contains a block 1 time pulse spacing, subtracted, its device 2, the circuit 3 assembly, the device 4 synchronization, the main reversible counter b, the main binary multiplier 6,

a multiplier 7 of frequency-pulse signals, an additional binary multiplier 8, an additional reversible counter V and a group of impulse-potential circuits 10 coincidence. The frequency signal multiplier 7 consists of a pulsed pulse separation unit 11, a pulse delay circuit 12, a trigger 13, a matching circuit 14, 15 and 16, a splitter 1 / frequency, a two-frequency difference generation unit 18, a reversible counter 19, a code converter - voltage 20 and controlled frequency generator 21.

The frequency converter in the code work1 as follows. In the steady state, the value of the input frequency FX and the value of the frequency of testing FZ differ from each other by an amount no more than the value of the lower reference frequency, where P0 is the number of bits of the main reversible counter. FX and FZ frequency difference

arrives at the input of the addition

reversible counter. The code value of the additional reversible counter does not exceed the unit of the least significant bit, and the multiplication factor k is equal to one. In this case, the operation of the converter does not differ from the work of the known, and it provides a high static accuracy of converting the input frequency to the code.

Consider the operation of the transducer in dynamic relevance when the input frequency FX changes over time. The value of the output code of the known converter is determined by the expression

N (p: pT, + 1

2 "about

where is go

- constant time known1

go converter; FO is the highest reference frequency of the binary multiplier; p - Heaviside transform operator.

In this converter, the frequency difference F / X and Pr is fed to the input of the multiplier 7 frequency-pulse signals, the output of which is frequency

Py (P) k (p) F (p) F, (p).

This frequency, the passage through the synchronization device 4, is integrated by the main reversible counter 5, and the code in it is determined by the expression

ToFAP)

l And At the same time, the difference module FX and FZ is fed to the input of the addition of an additional reversible counter 9 and is converted into a code

) -FZ (P)

y (p)

pTi + i

where ti is

the time constant of the frequency converter in the code consisting of a reversible counter 9 and a binary multiplier 8;

ni + l is the number of bits of the additional reversible counter 9.

In this case, Gu is selected larger than G. The code value taken from the zero outputs of the bits of the additional reversible counter 9 (taking into account the least significant bit) is determined by the expression + -1-Ny. If the divider 17 frequency multiplier 7 frequency-pulse signals from all zero outputs of the bits of the additional reversible counter 9, except the younger one, overflows, the code 17 is inserted into the frequency divider 17 through a circuit.

ent 2-- j.

In this case, the division factor of the divider 17, and hence the multiplication factor of the multiplier 7, is determined by the expression

k ent G2 "- + I

 +

- ent

where "1 is the number of bits of the splitter 17 frequency. Thus, the time constant for converting a given converter is k times less than that of the known, and the coefficient k, and hence the speed of converting frequency to code, is proportional to the difference in frequencies FX and FZ, which depends on the rate of change of the input signal FX.

Frequency converter to auth code St.

No. 310382, characterized in that, in order to increase the conversion speed, an additional reversible counter and a binary multiplier are introduced in it, a grinded impulse-potential matching circuit and

a pulse frequency signal multiplier, the signal input of which is connected to the output of the assembly circuit, the control input to the outputs of a group of pulsed potential coincidence circuits, one output to the input of a synchronization device, and the second switch with the pulse inputs of a group of potential impulse matching circuits moreover, the potential inputs of the latter are connected to the zero outputs of bits, except the younger,

An additional reversible counter, the unit outputs of the bits of which are connected to the inputs of an additional binary multiplier, and its output is connected to the subtraction input of an additional reversible counter, the input of which is connected to the output of the assembly circuit.