SU911724A1 - Stochastic analogue-to-code converter - Google Patents

Description

(54) STOCHASTIC CONVERTER ANALOG CODE

The invention relates to computing and may; It was used to measure analog values and their expectation.

A known analog-code stochastic converter containing an analog multiplicating unit, an analog memory element, a pulse generator, a frequency divider, a comparison element, two AND elements, two reversible counters, a code-voltage converter, six keys and two switches 11.

The disadvantage of the device is the limited functionality, since it allows determining the expectation only if the input signal satisfies the stationarity conditions.

Also known is a stochastic analog-code converter containing a comparison unit, whose input is connected to the outputs of a reversible counter through a code-voltage converter, and two outputs are connected respectively to the first inputs of two And elements, the second inputs of which are connected to the output of the pulse generator 2.

The drawback of the device is its limited functionality, since it does not allow determining the expectation for non-stadial signals.

The purpose of the invention is to expand the functionality.

This goal is achieved in that in the stochastic transformation 10. Anadog code containing a comparison unit, whose input through a code-voltage converter is connected to the outputs of a reversible counter, and the two outputs are connected to 15 but to the first inputs of two elements And, the second inputs of which are connected to the output of the pulse generator, a reversible counter with control its conversion factor

20 two RS-flip-flops, four drivers, three OR elements, a shift register, a delay unit, and three switches, with the first and second AND controls correspondingly

25 through the first and second contacts of the first switch are connected to the inputs of the reversible counter with control eN fcJM conversion factor, the counting outputs of which through the third and

30 fourth contact of the first switch; the gel is connected to the inputs of the reversible counter and to the R and S inputs of the first RS flip-flop, whose outputs through the first and second drivers are connected to the inputs of the first OR element, the output of which is connected to the input of the reversible counter from controlling the conversion factor, the outputs of which through the second switch are connected to the inputs of the second OR element and R and S inputs of the second RS flip-flop, the outputs of which through the third and fourth drivers are connected the first and second inputs of the third OR element, the output of which is connected to the installation input of the shift register, whose outputs through the third switch are connected to the inputs of decreasing the conversion factor of the reversible counter with the controlled conversion factor and the delay unit, the output of which is connected to the third input of the third the OR element, and the output of the second OR element is connected. To the shift input of the shift register. In FIG. 1 shows the structural electrical circuit of the device; in fig. 2 is a structural electrical circuit of the reversible counter with controllable conversion factor. The device contains a comparison unit 1, a generator of 2 pulses, a reversible counter 3, a code-voltage converter / elements 5 and 6, a reversible counter 7 with a control slm conversion factor, an automatic increase unit for the conversion factor of this counter, consisting of RS -trigger 8, formers 9 and 10, Element OR 11, automatic reduction unit for scaling factor, consisting of shift register 12, element OR 13, RS-trigger 14, formers 15 and 16, element OR 17, switches 18-20, block 21 delays, reversible Aetchik 7 with pack equal to the conversion factor contains a binary reversible counter 22, the trigger 23 digits, ka, shift register 24, the elements AND 25 - 37, the elements OR 38-40 and the block 41 delay. The device has three modes of operation. The mode selection is a switch 20. In the first mode, the input analog value is converted into a digital code. In this mode, the switch 20 is set to the upper position, in which the outputs of the elements And 5 and 6 are connected directly to the inputs of the counter 3. At the same time, the analog variable .x (t) is fed to the input of unit 1, the second input of which is supplied the voltage from the transducer 4. In the tracking mode at an arbitrary moment of time t, - block 1 produces signals 4lf and T2. (1 for x (Ы - Vf О% lO for x (t.) - UK. “О Л 1. at X (t, -) - и, с- 0; 2-t О at xttv) - UK.- 0; where x (t) is the input analog signal; Uj is the voltage at the output of the code-voltage converter. Thus, when the input analog value-x () turns out to be greater than the contents of counter 3, block 1 generates a signal / that opens the element Both 5, and signals from generator 2, passage through element 5, and switch 20, are input to the addition of reversible counter 3, increasing its contents by one at each conversion step. If the analog value is less than soda then, block 1, as a result of comparison x (t with Vf greater than x (t |), generates a signal fg / ti opens element 6 and the pulse from generator 2 through element 6 and switch 20 goes to input subtracting the reversible counter 3, reducing its contents by 1. If the analog value is equal to the contents of the reversing counter 3, block 1 closes And 5 and B elements, stopping the flow of pulses from the generator 2 to the input of the reversing counter 3. With this device functioning, the content of the reversible counter and 3, at each sampling step of the input signal, represents the value of the input analog variable numerically. In the second mode, the device determines the estimate of the mathematical expectation of the input analog signal at the current time. In this case, the switch 20 is in the lower position, i.e. the outputs of the elements And 5 and 6 are connected to the inputs of the reversible counter 7. The device in this mode works as follows. Block 1. at each sampling step of the input signal x (t) compares it with the linearly compensating voltage Uj .. If x (t) 7 Ux (t), block 1 opens Element I 5 and adds one to the content of the reversing counter 7. At x () U, (t) block 1 opens element Ib, and one is subtracted from the contents of the reversible counter 7. When Uictti) block 1 generates signals% f2 O, i.e., elements And 5 6 are closed and the content reversible counter 7 is unchanged. This process is repeated at each step of the measurement. At the same time, if the contents of the reverse counter 3 is less than the mathematical expectation, then during the time interval t the probability of the occurrences of cops when U | c (t, -) x (C) becomes significantly greater than the probability of occurrence moments when Uy () 7 x (t). The number of pulses 1Kb are received by the generator 2 through the element AND 5 to the input of the addition of the reverse counter 7 is also significantly greater than the number of pulses coming from the generator 2 through the element AND 6 to the input of the subtraction counter 7. 7. Due to this, a certain number of ticks occur reversing counter overflow 7. As a result, at the counter of reversing counter 7, a signal is added that adds one to the contents of reversible counter 3. If the contents of reversing counter 3 are again less athematic idle, then the above process is repeated until, until it becomes equal to the mathematical ozhidaniyu.vhodnogo x {t) signal. If the content of the reversible counter 3 is greater than the mathematical expectation m of the variable x (t), then when comparing U (t) with x (), the probability of occurrence of moments when (t) is significantly greater than the probability of occurrence of moments when Un (t;). x (C). Therefore, in. In this case, the number of pulses arriving through element Ib to the input of the subtraction of the reversible counter 7 is greater than the number of pulses coming through the element AND 5 at the input of the addition. In this case, the impulse of the compiler subtracts from the contents of the reverse counter -3 unit. This decrease occurs until the contents of the reversible counter 3 become equal to the expectation of the variable x (t). When the contents of the reversible counter 3 becomes equal to the expectation of the input variable x (t), then the positive and negative is. There are no overflows on the reversible meter 7, since the number of moments when x (t) is UK (and moments when x (t)) is equal to. In the device, at the beginning of operation, the conversion factor of the reversible counter 7 for quickly reaching the desired value of x (t) is set to the minimum. At the same time, on the reversible counter 3, a rough estimate of mx "is quickly dragged out, but the contents of counter 3, then increasing, then decreasing, changing around, the true value of the desired estimate. The change of the overflow sign, the reversible counter 7 is accepted; 3a is a sign of the insufficiency of its size. The signals received from the output of the reversible counter 7 are fed to the installation inputs, units and trigger 8. In this case, if after overflow with a positive sign, when trigger 8 is set to the position, an overflow occurs with a negative sign or vice versa, after a negative overflow there is a positive , the trigger 8 changes its state and on its output by the driver 9 or 10 a signal is generated which, passing through the element OR 11, affects: the reversible counter 7, increasing its bit by one bit Thus, with each change of the overflow sign of the reversible counter 7, the device provides an increase in its size by one bit, and this, in turn, increases the overflow time of the reversing counter 7. Therefore, the time for which the count is counted larger and smaller than the estimated score. With an increase in this time, the probability of an erroneous overflow of the reversible counter 7 decreases. Therefore, there is no erroneous change in the value of the reversible counter 3 expressing the desired estimate. If the process is non-stationary, it is necessary that at the moments of changing the value of the mathematical expectation, in order to ensure a quick correction of the previously found estimate, the conversion factor of the reversible counter 7 is automatically reduced. For this purpose, a third mode is provided in the device, which makes it possible to automatically reduce the conversion factor, i.e., the size of the reversible counter .7, at the moments when the value of the mathematical expectation changes. The reduction in the size of the reversible counter 7 is performed when the contents of a certain number of its lower bits are repeatedly overflowed. In this case, only the numbers of further overflows of one are counted. If the overflow sign of the best bits of counter 7 is changed at least once, then the counting starts again, the number of minor bits from which the overflow is ignored is selected by the switch 18. The number of consecutive overflows of the same sign is counted in register 2 and selected switch 19. the beginning of the operation of the device first gap d register 12 is set

p is a single position, all the remaining bits of register 12, as well as the reversible counter 7 and trigger 14 are set to O. During processing, when the expectation of the input signal changes, the difference x (t4 - U, (t) does not change its for a certain time t. For this period of time, only one of the elements 5 or 6 is in the open state. Only the signals that increase its content or only decrease it arrive at the input of counter 7. At the same time, overflow signals appear on one exit lane a key 18 connected to the outputs of one of the low-order bits of the reversible counter 7. As a result, the trigger 14 does not change its state and, therefore, no voltage drop occurs at its output, and the register 12 is not set and the initial state Thus, the signal from the overflow of a certain number of low-order bits of the same character, the passage through switch 18 and the element OR 13, is fed to the input of the shift of the register 12, each time it carries out units for one bit to the left. Every time when this shifting unit reaches the contact of the switch 19, the signal received at its output reduces the conversion factor of the reversible counter 7 and further, passing through block 21 and the OR element 17, sets to the initial position of the register 12. Each time when the value of the mathematical expectation changes, the conversion factor of the reversible counter 7 decreases, which leads to a decrease in the overflow time of the reversible counter 7 and ensures a quick correction of the value of the reversible counter and 3. When the contents of the down counter 3 is equal to the rough evaluation of new expectation value, the apparatus again similar to the second mode increases a width of up-down counter 7, and corrects the value as long as it does not becomes equal to the desired new estimate the expectation.

In the reversible counter 22, in the course of processing, either the summation or subtraction of single pulses produced depending on the sign of the difference x (C) - L) n (t,) and the sign of the content of the reversing counter 22 is performed. In this case, the sign of the content of the reversible counter is fixed. in the trigger 23. The unit outputs of each bit of the reversible counter 22 through the corresponding elements AND 29 - 32, the element OR 40 and the elements AND 33 - 34 are connected to the inputs of the addition and subtraction of the reversible counter 3i The second inputs of the elements 29 - 32 are connected to the outputs from the corresponding register bits 24. At the beginning of the work, the first register bit 24 is set to one position, and all other bits - to zero,

The shift of this unit to the right in the register 24 is produced by the signal from the output of the element OR 11 generated by changing the sign of the transfer of the reversing counter supplied to the input 3. The shift of the unit to the left in the shift register 24 is produced by the signal from the output of the switch 19 generated when the specified number of consecutive overflows from the output of a predetermined number of low-order bits of the reversing counter 22. Thanks to such an organization, the discharge of the reversing counter 22 is connected to the inputs of the reversing counter 3 which is opened by the corresponding register bit 24 in a single position.

Thus, in the process of processing information, the magnitude and decrease of the size of the reversing counter 22 is automatically increased and reduced.

The proposed device allows reducing the time and costs required for automating the estimation of statistical characteristics of random signals in real time.

Claims (1)

Invention Formula A stochastic analog-code converter containing a comparison unit, whose input through a code-voltage converter is connected to the outputs of a reversible counter, and the two outputs are connected respectively to the first and the inputs of two And elements, the second inputs of which are connected to the output of the pulse generator, characterized in that , in order to expand its functionality, a reversible counter with a controllable conversion factor, two short-circuits, four drivers, three OR elements, a shift register, a buckle unit, and three switch, the outputs of the first and second elements And, respectively, through the first and second contacts of the first switch connected to the inputs of the reversible counter with a controlled conversion factor, the counting outputs of which through the third and fourth contacts per