SU1594691A1 - Follow-up a-d converter - Google Patents

Abstract

The invention relates to measuring and computing technology, can be used in systems of automation of scientific research. Speed increase is achieved by introducing into the converter containing comparison unit 1, analog storage unit 2, digital-to-analog converter 3, reversing counter 4, sign fixing unit 5, control unit 6, clock pulse generator 7, trigger 8, pulse distributor 9, block 10 meter control, trigger 11, bus 12 "Reset flag", bus 13 "Ready", register 14, delay element 15, bus 16 "Start", speed estimation unit 17, second trigger 18 and input bus 19, operating code block 20 , second register 21, block 22 current its averaging the rate of change of the input signal, differentiation unit 23. The performance improvement is based on the fact that to determine the next value of the varying input signal, it is sufficient to use not all the bits of the reversible counter belonging to the subband found, but only some limited sets of bits whose composition allows you to take into account the characteristics of the input signal and perform the conversion faster. A particular limited set of bits is selected depending on the current average value of the rate of change of the input signal, while the lower bit of the reversible counter belongs to all the working sets. 2 hp ff, 5 ill.

Description

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The invention relates to ana-pogo .. Digital converters (ADC) and can be used in measuring and computing technology, in systems of automation of scientific research.

The aim of the invention is to increase speed.

Figure 1 shows the functional circuit of the following analog-to-digital 30 Converter; Figures 2 and 3, respectively, the control unit and the unit for selecting the working code; ka of Figures 4 and 5 are timing diagrams of signal conversion in the device.

The next analog-digital converter contains a comparison unit 1, an analog storage unit 2, a digital analog converter 3, a reversible counter 4, a sign fixing unit 5, a control unit 6, a clock pulse generator 7, a trigger 8, a pulse distributor 9, a block 10 counter control, trigger 1, bus 12 Reset flag, bus 13 Ready, register 14, delay element 15, bus 16 Start, speed estimator 17, trigger 18, input bus 19, signal 20 select.a working code, register 21 , block 22 of the current averaging rate of change of the input Igna, differentiating unit 23.

40

45

50

The control unit 6 is implemented on D-triggers 24-27, decoder 28, inverters 29-31, elements AND 32-37, elements OR 38-41.

five

five

0

0

five

0

five

The working code selection block 20 is superimposed on the elements HE 42-45, elements AND 46-54, elements OR 55-57,

The sign fixing unit, depending on the type of signal coming from the comparison unit, can be implemented in two ways.

If an analog signal comes from the comparison unit, the informative parameter of which is the sign (+ or -, or), then the simplest implementation is the Schmitt trigger.

If a digital signal comes from the comparison unit (1 or O is greater or less), then the sign fixing unit can be implemented as a normal D-flip-flop.

. The counter control unit 10 can be executed in the form of a gated elements block I.

As a unit 22 for current averaging the rate of change of the input signal, a device for current averaging of an electrical signal can be used. In this case, the analog-to-often converter input is used as the input of the unit 22 — the device for the current averaging of the electrical signal, the outputs are connected to the display unit of the same device.

The Converter operates as follows.

Before operation, the initial setup signals set the triggers 8,18 and II to the zero state.

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9 pulses distributor - in any state. In register 14, a code with a unit in one of the bits is entered; in register 21, any code can be found. The circuit of the initial installation is not shown. ,

With the arrival of the start signal, the contents of the register 14 are copied to the pulse distributor 9. In register 21, the code corresponding to the signals taken from the output of block 22 is memorized, at the initial moment this code can be zero.

At the output of the differentiation unit 23, a signal is continuously generated corresponding to the rate of change of the input signal, in block 22 a code is generated corresponding to the current one. the mean value of the rate of change of the input signal (i.e., a sliding average of the rate of change of the input signal occurs over a period of time of a given duration). By

Start-up signal generated by

ness

l 9 pulses. Then the control unit 6 shifts the distributor 9 pulses to the right, provided that the least significant bit of the latter is not in state 1. Again, subtracting or adding one unit to the next digit of the reversing counter 4 followed by shifting the distributor 9 pulses to the right. If the unit is in the lower order of the distributor 9 pulses, the control unit 6 sends signals at the first output to change the contents of the reversible counter 4 until the signal alternates at the output of the 5-character block, then at the third: 0 ode of the control unit 6 A signal that sets the trigger 8 to O, stops the operation of the control unit 6, and also sets the trigger 11 into one state, the signal Ready appears at the unit output

thirty

the output of the delay element 15, the analog storage unit 2 stores the current value of the signal, the triggers 8 and 18 are set to one, permitting the operation of the control unit 6, respectively, and the evaluation unit 17, soon. Thereafter, the speed of the input signal will be estimated by kgk, and the signal at the output of the speed estimator 17 will register the estimated speed value (code with a unit in one of the bits), and also sets the transfer threshold j 1 to the zero state 12 Reset flag.

with in about the trigger 18, stopping the operation unit speed assessment 17.

The working code selection unit 20 connects the output of the counter control unit 10 to the counting inputs of the bits of the reversible counter 4, depending on the use of limited sets of bits to change the contents of the reversible counter 4, can be illustrated by the following example (Fig. 4). Let a three-bit pulse distributor 9 be used, a ten-digit reversible counter 4, and a code corresponding to the current average value of the rate of change of the input signal, 40 is represented by a two-digit binary number, and a two-bit register 21 is used to store it (i.e. The current average estimate can be represented by four levels: 2 4).

ti from the code stored in register 21, dz. Obviously, with the highest level, the counting input is the same. The evaluation (i.e., 11) of the current medium of the reversible counter 4 is not always the most advantageous to use. It is connected to the younger bit of the distribution — one of the higher bits of the reversing diter of 9 pulses. . counter 4, some intermediate

Depending on the mode of reversal, 50 and. Junior, for example, 8,3 and 1 st. Nago counter 4, set by block 5 fixing the sign, block 10 control counter signal to the block. 6 control subtracts or adds a simple approximation of the input signal. can be carried out using the 8th bit, and refinement using the 3rd and then the 1st. With an average of 4, 55 reversive counter, they are the levels of assessment of the current average. connected via block 20 of the output (102.012), the most efficient boron of the working code to the output of the block will work, for example, a set of

5, 3-nd and 1-st bits, with a small score of 10, which corresponds to the bit containing the unit of the distribution, a set of 3, 2 and 1-th bits.

Dp transfer trigger j 1 to the zero state is used bus 12 Reset flag.

The features of using limited sets of bits for changing the contents of the reversible counter 4 can be illustrated by the following example - (Fig. 4). Let a three-bit pulse distributor 9 be used, a ten-digit reversible counter 4, and a code corresponding to the current average value of the rate of change of the input signal be represented by a two-digit binary number, and a two-bit register 21 is used to store it (i.e. The current average can be represented by four levels: 2 4).

and junior, for example, 8.3 and 1st. The initial approximation of the input signal. can be carried out using the 8th bit, and refinement using the 3rd and then the 1st. With medium 5, 3-and 1-bit, with a small estimate

ke is a set of 3, 2 and 1 bits.

ten

The choice of possible combinations is made based on the goals and conditions of application of a particular development.

It should be noted that all bits belonging to a limited set of working bits are not necessarily used to change the contents of the reversible counter 4 with each conversion, since the bit from which this change begins is determined by the contents of the pulse distributor 9 at the start of the conversion, and this content, in turn, t5 Depends on the value of the velocity estimate of the input signal at the time of the previous, ifo conversion. So, dp is given in the example, when using a set of 8, 3 and 1 bits, if the signal speed value estimated at the previous moment is sufficiently small, a code with a unit in the lvlladsev category can be entered into the distributor 9 pulses . In this case, the unit is immediately subtracted or D is added to the lower-order bit of the reversible counter.

The advantages of the pre, convertible converter compared to the known one can be shown in the following example. Suppose that the input signal is measured slightly. In this case, the rate of change is non- harmful; much more. Suppose that in a known device that uses an 8-bit pulse distributor, the rate of change of the input signal is estimated at the time of some fluctuation of the input signal Ea - a slight burst. In this case: the speed estimate will be high, с.о-40 is appropriate, for example the pulse distributor code with a unit in the 7th bit, the actual change in the input signal is insignificant, for example IjSi, where D is the minimum 45 ffiiar quantization corresponding to the low-order unit of the reversible counter. Then, in a known device, successively 25

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conversion (at the moment of fluctuation and turned out to be high, the most senior, containing the quick unit, the pulse distributor discharge turns out to be connected. The Z-MU discharge of the reversible counter for conversion will need only three steps: adding a unit to the W-MU discharge, subtracting a unit from 2 th bit and subtract one from the 1 st bit (Fig. 5). Thus, the conversion time is reduced.

The increase in speed is also ensured by the fact that, in addition to the use of limited codes when measuring the contents of the counter, in the proposed converter during the sequential conversion of the signal. units are added or subtracted from the conserved result of the previous averaging, while the process of searching for the subband occurs at a known beginning, and then in all the subrange there is a random balance.

Form L a invention

n and

1. A next analog-to-digital converter containing a comparison unit, the first input of which is connected by the output of an analog storage unit, whose information input is an input bus, the second input of the comparison unit is connected to the output of a digital-to-analog converter, the digital inputs of which are connected The counters of the reversible counter are in the busbar, the output of the comparison unit is connected to the input of the character fixing unit, the first output of which is connected to the first input of the control unit, and second and third tii outputs - with the inputs of the reversible counter mode setting; the second input of the control unit is connected to the output of the clock pulse generator; the third input is with the single output of the first trigger, and the fourth

 f-s, -ts 1 ps: 1 Dlrl

RAN transform over all bit - jq input - with single bit minor output

ladies from the 7th to the 1st.

Let the proposed device contain a 3-bit pulse distributor. Owing to the low current average speed, the working set will be determined, containing the lower bits of the reversible counter, for example, 3, 2. and 1 st bit. Then, although speed estimate at previous

of the pulse distributor, the first output of the control unit is connected to the input of the counter control unit, the second output is connected to the installation input 55 of the first trigger and the installation input to the second trigger, the installation input of which is the bus Reset flag, and direct output - bus readiness, outputs times

the conversion (at the moment of fluctuation) turned out to be high, the most senior, containing the unit, the pulse distributor discharge is connected to the Z-MU discharge counter, and the conversion will require only three steps: adding one to the W-MU discharge, subtracting units from the 2nd bit and subtraction of the unit from the 1st bit (Fig. 5). Thus, the conversion time is reduced.

The increase in speed is also ensured by the fact that, in addition to the use of limited codes in measuring the contents of the counter, in the proposed converter at the next signal conversion. units are added or subtracted from the stored result of the previous transformation, while in the first known process the search for the subband occurs, and then in a whole subrange there is a random balancing.

Form L a invention

n and.

Claims (3)

1. A next analog-to-digital converter containing a comparison unit, the first input of which is connected to the output of an analog storage unit, whose information input is an input bus, the second input of the comparison unit is connected to the output of a digital-analog converter, whose digital inputs are connected to the corresponding bit outputs reversible counter and are the output bus, the output of the comparison unit is connected to the input of the block fixing the sign, the first output of which is connected to the first input of the control unit, and the second three outputs - to the inputs of the reversible counter setting mode, the second control unit input coupled to the output of the clock, the third vhod-- with a single output of the first flip-flop, and the fourth  f-s, -ts 1 ps: 1 Dlrl entrance - with a single exit younger the pulse distributor, the first output of the control unit is connected to the input of the control unit of the counter, the second output is connected to the input of the installation in O of the first trigger and the input of the installation in 1 of the second trigger, the installation input of which is the bus Reset flag, and the forward exit - bus readiness, exits times the pulse distributor rows are connected to the corresponding inputs of the input control unit of the counter and the installation inputs of the pulse distributor bits are connected to the digital outputs of the first register, the first control input of which is combined with the input of the delay element and the start bus, the second control input combined with the input installation in the third trigger and connected to the output of the speed estimator; the direct output of the third trigger is connected to the first input of the velocity estimator, the output group of which is dinene with the corresponding digital inputs of the first register, the output of the delay element is connected to the inputs of the installation of 1 of the first and third triggers and with the control input of the analog storage unit, which is so that, in order to improve speed, a block is inserted into it differentiation, the current averaging block of the rate of change of the input signal, the second register and the block for selecting the working code, the block input-. . differentiation is combined with the second input of the speed estimator and is an input bus, and the output through the current averaging block of the change rate of the input signal is connected to the installation inputs of the second register bits, the control input of which is with the Start bus, the digital outputs of the second register are connected with the first group of inputs of the operating code selection block, the second group of inputs of which is connected to the corresponding outputs of the counter control unit, and the outputs of the selection of the working set are connected to the counting inputs of the Dow reversing counter, the third output of the control unit is connected to the input Shift to the right of the pulse distributor. 2 .. The Converter according to claim 1, about t l and . that block upg on the decoder. Part of the implementation four P-triggers, four OR elements, six AND elements, three inverters, the first input of which is combined with the first inputs of the first and second AND elements and is a fourth block input, and the output is connected to the first input of the third And element, the first and the second inputs of the fourth element And are the second and third inputs of the block, respectively, and the output co10  , p 25. thirty 0 five 0 One with the C-inputs of the first, second, and third D-flip-flops, the D-inputs of which are connected to the outputs of the first, second, and third OR elements, respectively, and the direct outputs to the corresponding inputs of the decoder, the first output of which is directly connected to the first input The second OR element, through the second inverter, with the second input of the first element AND is the first output of the unit, the second decoder output is connected to the second inputs of the second and third AND elements and the first input of the third SHS element, the third output of the decoder The first output of the first element is the third output of the unit, the fourth output of the decoder is connected to the second input of the third element, the fifth is the second output of the unit, and the sixth output is connected to the third input of the third element OR connected to the output of the fourth element OR, the first and second inputs of which are connected to the outputs of the fifth and sixth elements And, respectively, the first input of the fifth element And through the third inverter is combined with the first input of the sixth element And, the D input of the fourth This D-flip-flop and is the first input of the block, the fourth D-flip-flop is connected to the output of the first And element, the second. the input of the fifth element And is connected to the direct output of the fourth D-flip-flop, the inverse output of which is connected to the second input of the sixth element And, and the outputs of the second and third elements And are connected to the second inputs of the first and second elements OR, respectively. 3. The converter according to claim 1, about t - that is, the working code selection block is made on nine AND elements, three OR elements and four NOT elements, the first input of the first AND element is combined with the first input of the second AND element, and inputs of the first and the second element is NOT, the second input of the first element is AND is combined with the inputs of the third and fourth elements is NOT, the first input of the third element is AND, and the output of the first element AND is connected to the first inputs of the first element OR and the fourth element AND, the second input of which is combined with the first entrances n of the first and sixth elements And, the first inputs of the seventh and eighth elements And are combined and together with the second input of the fourth element And are the second group of inputs of the block, the first group of inputs of which are the inputs of the first element And, the second inputs of the fifth element And and the first element OR connected to the output of the second element OR, the first and second inputs of which are connected to the outputs of the second and third elements AND respectively, the second INPUTS of which are connected to the outputs of the third and first elements NOT: respectively, the second inputs eleven || | 1 II From the maifmoBb / x generator. impulse 2 the sixth and eighth And elements are connected to the output of the ninth AND element, the first and second inputs of which are connected to the outputs of the second and fourth elements, respectively, the output of the first OR element is connected to the second input of the AND element, the output of which is connected to the first input of the third OR element, the second input of which is connected to the output of the sixth element AND, the output of the fourth, fifth and eighth elements AND and the output of the third element OR are the outputs of the block.  From 5 block scrutiny signs ig WMySxoffy From pci3pflaa Extending cuwana. Memorized bmd signal  New result - - - poeobooooir The result of pre & I FIG. li Previous result transformed 3onoMffeH A / u c) (one sienal raoanir The result of the previous & - - Resultul HoSow nDeofpG3oda c / fl  t FIG. five