SU1152091A1 - Dtgital-to-analog converter - Google Patents

Abstract

DIGITAL-HI.POGOVYY CONVERTER, containing the first register, the inputs of which are connected to the input bus, the source of the reference voltage, the block of bit switches, the first input of which is connected to the output of the source of the reference voltage, the matrix of resistors, the inputs of which are connected to the outputs block of bit switches, an amplifier whose input is connected to the output of a resistor array, an output with an output bus, characterized in that, in order to improve speed, an additional block of bit switches is entered into it, a second register, inputs to The first is connected to the outputs of the first register, the first subtraction unit, the first inputs of which are connected to the outputs of the first register, and the second inputs to the outputs of the second register, the multiplication unit, inputs of which are connected to the outputs of the first subtraction unit, the second subtraction unit, the first inputs of which connected to the code zero bus, and the second inputs are connected to the outputs of the multiplication unit, the switch, the first inputs of which are connected to the outputs of the multiplication unit, the second inputs to the outputs of the second subtraction unit, and the third inputs to the code zero bus, sum the aor, the first inputs of which are connected to the switch outputs, the second inputs to the outputs of the first register, the outputs of the lower bits - to the second inputs of the bit-key block, the outputs of the high bits - to the first inputs of the additional block of bit keys (L second the input of which is connected to the output of the source of the reference voltage, an additional matrix of resistors, m of the inputs of which are connected to the corresponding outputs of the additional block of discharge switches, and an output to the input of the amplifier, a delay line, 01 of which is connected to the sync bus the law, the synchronization input of the first register, the OR element, the inputs D of which are connected to the first outputs of the delay line, the counter, the counting input of which is connected to the output of the OR element, and the zero setting input to the synchronization bus, the parity and odd parity block , the inputs of which are connected to the outputs of the counter, the trigger, the installation inputs to the zero state of which are connected to the synchronization bus, and the installation input to the single state to the synchronization input of the second register and the second output of the line beyond

Description

holders, two elements And, the first inputs of which are connected to the corresponding outputs of the block of parity and oddness, the second inputs - with the inverse output of the trigger, and the outputs

Elements And and the direct output of the trigger are connected respectively to the first, second and third control inputs of the switch.

one

The invention relates to computing, namely, means for converting information from digital form to voltage, and can be used in analog-digital converters, digital filters, displays on cathode-ray tubes for generating scanning signals, computational and control systems.

Digital-to-analog converters (CDL) are known, which contain a storage register, a stabilized reference voltage source, and a digital-to-analog decoder consisting of analog switches and a chain of precision resistors. In such D / A converters, the digital code to be converted is written in the trigger register. Each trigger register is controlled by an analog key, which, depending on its state, is either disconnected or connected to the corresponding input of the resistive chain of the voltage of the reference source or the current derived from it. A resistive chain divides the reference voltage or the current derived from it in such a way that the voltage increment at the DAC output is proportional to the equivalent weight of the LN input number. Since such DACs do not contain an output amplifier, they are often much cheaper than converters with an amplifier at the output. However, they cannot be thermally stable, as the temperature instability of the multi-link chain of resistors directly affects the output signal. In addition, they are not neuiversals because they allow only high-resistance loads to be connected.

The closest technical solution to the invention is a D / A converter containing the first register, the inputs of which are connected to the single bus, the source of the reference voltage, a block of bit switches, the first inputs of which are connected to the output of the source of the reference voltage, and the other inputs the outputs of the first register, the matrix of resistors, the inputs of which are connected to the outputs of the block of bit switches, the summing amplifier, the input of which is connected to the output of the matrix of resistors, and the output is connected to the output bus 23.

The disadvantage of the known, DAC - low speed. The reason for this is a lengthy transient in the matching amplifier, due to the presence of parasitic reactive elements in the circuit. In this case, the duration of transients increases with an increase in the number of bits of the input number, as the requirements for conversion accuracy increase, i.e. more accurate D / A converters require more time for setting the output signal.

The purpose of the invention is the step-up of speed, the converter.

The goal is achieved by the fact that in the DAC, which contains the first register, the inputs of which are connected to the input, the source of the reference voltage, the block of discharge switches, the first input of which is connected to the output of the source of the reference voltage, the matrix of resistors, the inputs of which are connected to the outputs of the block single keys, an amplifier whose input is connected to the output of resistors, and an output to the output bus, an additional block of bit switches is entered, a second register whose inputs are connected to the outputs of the first register, the first subtraction block, the first The second inputs of which are connected to the outputs of the first register, and the second inputs to the outputs of the second register, the multiplication unit, the inputs of which are connected to the outputs of the first subtraction unit, the second subtraction unit, the first inputs of which are connected to the bus code zero, and the second inputs are connected to the outputs the multiplication unit, the switch, the first inputs of which are connected to the outputs of the multiplication unit, the second INPUTS - with the outputs of the second subtraction unit, and the third inputs with the code zero bus, the adder, the first inputs of which are connected to the outputs of the switch, the second inputs - to the outputs of the first register, the outputs of the lower bits - to the second inputs of the block of bit-switches, the outputs of the higher bits - to the first inputs of the additional block of bit-switches, the second input of which is connected to the output of the reference voltage source, additional inputs which is connected to the corresponding outputs of the additional block of the bit switch, and the output to the amplifier input, delay line, the input of which is connected to the synchronization bus, the synchronization input of the first register, the OR element, whose inputs dinene with the first outputs of the delay line, the counter, the counting input of which is connected to the output of the element HIttlj and the input of setting to the zero state to the synchronization bus, the block of parity and odd parity, the inputs of which are connected to the outputs of the counter, trigger, input of setting to the zero state which is connected to the synchronization bus, and the installation input in the single state to the synchronization input of the second register and the second output of the delay line, two AND elements, the first inputs of which are connected to the corresponding outputs of the control unit NOSTA and oddness, the second inputs of the flip-flop inverted output .s, and the outputs of AND gates and output latch straight- connected respectively with the first, second and third inputs of the gate switch,

FIG. 1 shows the flow chart of the proposed DAC; in fig. 2 - 5 - times (1st diagrams, explaining his work.

The DAC contains the first register 1, the source of 2. reference voltage, the block 3 of bit switches, the matrix 4 of resistors, the amplifier 5, the second register 6, the first block 7 of subtraction, block 8 of multiplication, the second block 9 of subtraction, switch 10, the adder 11 additional 12 bit block

keys, - additional matrix of 13 resistors, delay line 14, element OR 15, counter 16, parity and oddness block 17, trigger 18, first 19 and second 20 elements I.

The inputs of the first register 1 are connected to the input bus, which receives the conversion code. The output of the first register 1 is connected to the inputs of the second register 6, the first inputs of the first subtracting unit 7 and the second inputs of the adder 11. The outputs of the second

the register 6 is connected to the second inputs of the subtracting unit 7, the outputs of which through the multiplication unit 8 are connected to the first inputs of the switch 10 and the second inputs of the second subtraction unit 9, the first inputs of which are connected to the code zero bus and the third inputs of the switching unit 10. The outputs of the second subtraction unit 9 connected to the second inputs of the switch 10, the outputs of which are connected to the first inputs of the adder 11. The outputs of the higher bits of the adder 11 are connected to the first inputs of the block 12 additional keys, the second inputs of which are connected to the source output 2 reference voltages and the first inputs of the main switches, the second inputs of which are connected to the outputs of the block 3 lower bits of the adder 11. The outputs of the block 3 discharge keys through the matrix of 4 resistors are connected to the input of the amplifier 5. The outputs of the additional block of 12 bit switches via an additional matrix 13 resistors are connected to the input of the amplifier 5, the output of which is connected to the output bus.

The second register 6 is used to store the previous value of the input code of the DAC with respect to the contents of register 1. The first subtraction unit 7 forms the difference between the new (decremented) and the previous (subtracted) values of the input DAC code. The multiplication unit 8 multiplies the output DIGITAL of the first subtraction unit 7 by a constant positive number Kn S1 of the scale factor. The second subtraction unit serves to find the difference between zero (decremented) and output code (subtracted) of multiplication unit 8 and is intended to form a number opposite in sign to the output number of multiplication unit 8. The output of the switch 10 receives one of its three input combinations, depending on which of its three control inputs (direct output of the trigger 18, output of the AND 19 element, output of the AND 20 element), there is a single level (correspondence informational ;; and control inputs will be shown). Adder 11 is an ordinary binary combinational adder. Additional block 12 bit switches and a matrix of 13 resistors represent one or more additional bits of the DAC, which are subsequent higher in weight with respect to the most senior of the main bits of the DAC. Digital blocks 6-10 are designed to generate control signals — codes, blocks 14-20 are controlled by switching these codes. The time domains to which the control signals need to be switched are set using a delay line, to the input of which an external clock pulse arrives. The output of the delay line 14, connected to the synchronization input of the second register 6 and the zero setting input of the trigger 48, corresponds to the maximum signal delay in this line. The functions of the standard blocks 15-17 are fully defined by their names and do not require additional explanations. It only needs to be clarified that when elements 19 and 20 are opened with a single potential from the inverted spincode code 18, with even-numbered counter contents 16, the output code & 8 multiplication is transmitted to the output of the switch 10, and for odd, the output code of the second key 9 | subtracted When the elements, And are closed, the zero potential from the inverse output of the trigger 18, the unit potential of its direct output allows the transfer to the output of the switch 10 of the zero code. . The device works as follows. In the detail of the character of the transients at 1 output of the D / A, we consider as an example the case when the operation of analog D / A nodes (blocks 4, 13, 15) is described by a second-order differential equation. This means that the state of the DAC, as a control object, is completely characterized by two coordinates — the level of the output voltage and its first derivative with respect to time, i.e. the rate of change of this voltage. The goal of optimal transient control in the DAC is to bring the output voltage level to the specified value (corresponding to the new value of the input digital code) in the shortest time, but so that by the same time the output voltage change rate is equal to zero. The operation cycle begins with the arrival of an external clock pulse. On this pulse, the next (new) input DAC code is recorded in the first register 1, the counter 16 and the trigger 18 are set to the zero state, and the pulse itself arrives at the delay line 14. The unit potential of the inverse output of the trigger 18 opens the element And 19 and 20, The zero state of the counter 16 is perceived by the parity 17 and odd parity checker 17 as an even number, therefore the output level of this circuit and the output of the element 19 associated with it appears . As a result, the output code of the multiplication unit 8 is transmitted to the output of the switch 10. After the new code is written, the contents of the first register 1, in general, change by some value kK. In the well-known DAC, the new input code, and only it, immediately and directly enters the inputs of the block 3 of bit switches, as a result of which a certain transition process occurs in the output of the amplifier 5, shown in FIG. 5 of the AF curve and the response of the analog nodes of the DAC circuit to a jump in the input signal. In the proposed DAC, the new input code is fed to the first inputs of the adder 11. In addition, it is fed to the first subtraction unit 7, on the code of which the value of the ratio between the new and the old code stored in the second register 6 is formed. This difference, denoted by DC, is scaled up to the value of the DC (Fig. 2) using the multiplication unit 8 and the second inputs of the adder 11 (Fig. 3) are fed through the switch 10. At the same time at the inputs of blocks 3 and 12, i.e. at the outputs of the adder 11, it turns out (fig. 4) a code differing in the value of the new input code by 4 K (the sign of difference coincides with the sign of JK). Due to the fact that in the proposed DAC the initial jump in the value of the T1 code at the inputs of the analog bits of the bits is always greater than the actual change in the input code of the DAC, the transient is forced at the output of the DAC, and this process tends to develop along the ABD curve (Fig. 5). At a certain point in time t (point B has been reached), the process should be slowed down to prevent trans regulation. This is done as follows. From the impulse from the first output of the delay line 14, the content of the counter 16 is set to one. In this case, at the output of the odd unit 17 of the control of parity and oddness, a single potential arises, and at the output of an even - well, left potential. As a result, the output code of the second subtraction unit 9 is transmitted to the output of the switch 10, i.e. the magnitude of -KD (Fig. 1.3 and 4), and the output voltage of the DAC from the time t tends to vary along the curve of the WEEE (4mg. 5). The time tj, at which the output voltage of the DAC reaches a stationary level corresponding to the new input code, and the first derivative of the output voltage of the DAC becomes zero with time, is the end of the control process. The indicator of this moment is the appearance at the last (in this example, the second) output of the delay delay line 14, according to which the contents of register 1 are rewritten into the second register 6, and the trigger 18 is transferred to the unit state. The unit level of the direct output of the trigger 18 permits the transfer of the zero code to the output of the switch 10. As a result, the output of the adder 11 is the same code as. and at the output of register 1, i.e. A new input code, and therefore, the transition process in the DAC code actually develops along the ABC line (Fig. 5), i.e. ends at point B. This is where the DAC cycle ends. To implement the proposed device, it is necessary first to select the number of additional (senior) bits, due to which it is possible to force transitions of 1x processes in the DAC, and then to calculate the worst-case-optimal switching time values (in the considered example - C and t,) which determine the parameters of the delay line 14, the selection of the number of additional (senior) bits (one or more) is arbitrary. In this case, the value of the constant scale factor K is automatically determined by which the output code of the first subtraction unit 7 is multiplied in block 8. This coefficient should be set so that when the input code of the n-bit DAC changes as much as possible, i.e. by an amount of 2, the code values at the inputs of the bit's analog switches, causing the transient process to be forced at the DAC output, differed from the maximum or minimum input code by an amount equal to half the difference between the number corresponding to the full range of the output (or input) DAC signal, taking into account its additional (senior) bits, and the number corresponding to the range of operation of the main DAC. Such a condition follows from the need for optimal control of the transition process to ensure equal in magnitude and opposite in increment sign of the control parameter. This means that for two extreme cases of DAC operation, the maximum DAC input code or jMeHbmaTb need to be increased by a certain amount by the same value as the minimum DAC input code. Therefore, if n is the number of cores, am is the number of additional bits of the DAC, then the scale factor Km of multiplication unit 8 should be calculated by the formula () In other words, when forcing the transition process at the output of the DAC, in these extreme cases, the highest value is always used the control signal provided by the introduction of the Q device of additional (senior) bits of the DAC. For any other situations, the increment of control codes is K (Fig. 2 is so many times smaller than the maximum possible, how many times the change. DKN of the input cad of the DAC is less than its working range, i.e., number 2. Therefore, due to the linearity of blocks 4, 13 and 5 , with any changes in the input codes of the DAC, the reduction of the divider to carry the transient on its output occurs at the same time, which is the maximum possible dp of the worst case. For all "x." z "o" odn "l1, : it shortens the duration of a transitive contraction of a nonovnnnogo useful n process when using the reserve for increasing the control signal А К, 1 (Fig. 2-4). But the speed of the DAC is still determined by the time of establishing the worst case 9110 in dp, which is minimized in the proposed device. This means that the switching times of the control codes are performed for the worst situation, either by building a mathematical model of the analog part of the CDL or by experimentally determined dynamic characteristics. In this case, as already noted, the value of the control parameter (digital code) in the worst situation is assumed to be half the range specified by the additionally introduced t bits of the D / A converter. The technical and economic advantages of the proposed DAC compared to the known one are as follows. In the proposed DAC, by introducing additional units, redesigning a special type of transition control, speed is achieved. This is accompanied by an increase in the complexity of the device. However, most of the additional blocks introduced (13 and 15) are digital and very simple, therefore the cost of the proposed device. .. “About the level of e-technology, increases insignificantly. Speed is one of the main characteristics of a D / A converter, and its expansion significantly expands the range of application of the device.

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Claims (1)

A DIGITAL ANALOGUE CONVERTER containing a first register, the inputs of which are connected to the input bus, a reference voltage source, a block of bit switches, the first which is connected to the output of the matrix of resistors, and the output to the output bus, characterized in that, in order to improve performance, an additional block of bit keys, a second register, the inputs of which are connected are dined with the outputs of the first register, the first subtraction block, the first inputs of which are connected to the outputs of the first register, and the second inputs are connected to the outputs of the second register, the multiplication block, whose inputs are connected to the outputs of the first subtraction block, the second subtraction block, the first inputs of which are connected with a zero code bus, and the second inputs are connected to the outputs of the multiplication block, a switch whose first inputs are connected to the outputs of the multiplication block, the second inputs are with the outputs of the second subtraction block, and the third inputs are with the zero code bus, adder, the first the strokes of which are connected to the outputs of the switch, the second inputs to the outputs of the first register, the outputs of the least significant bits to the second inputs of the block of bit keys, the outputs of the senior bits to the first inputs of an additional block of bit keys, the second input of which is connected to the output the reference voltage source, an additional matrix of resistors, w inputs of which are connected to the corresponding outputs of the additional block of bit keys, and the output to the input of the amplifier, a delay line, the input of which is connected to the synchronization bus, input s timing of the first register, the OR element, the inputs of which are connected to the first outputs of the delay line, the counter, the counting input of which is connected to the output of the OR element, and the zero input state - to the synchronization bus, the parity and oddness control unit, the inputs of which are connected to the counter outputs , a trigger, the zero inputs of which are connected to the synchronization bus, as well. the installation input is in a single state - to the second synchronization input and the second line output for SU.nl 152091 latches, two AND elements, the first inputs of which are connected to the corresponding outputs of the parity and oddity control unit, the second inputs are with the inverse trigger output, and the outputs of the AND elements and a direct trigger output are connected respectively to the first, second, and third control inputs of the switch. ) _v