SU886760A3 - Digital lattice filter for speach synthesizer - Google Patents

Abstract

The digital filter comprises a memory (31) storing filter coefficients, a multiplier (30) multiplying internal data of the filter by the said filter coefficients, an adder/subtracter (33) adding the results of the multiplications to other data obtained in the filter, a delay circuit (34) connected up to the output of the adder/subtracter, a shift register (35) storing and retrieving at the requisite the time the data coming from the delay circuit, and an interlock output memory (36) storing a datum output by the filter. These various elements are interconnected with the aid of switches (37, 38) in order to perform the successive operations of multiplication and addition during a cycle. This filter, equivalent to a lattice filter, can be used in a voice synthesizer. <IMAGE>

Description

(54) DIGITAL GRATINIZED FILTER OF SPEECH SYNTHESIZER

This invention relates to acoustics, in particular, digital lattice filters of a speech synthesizer. The known digital lattice speech synthesizer filter contains input buses connected to the transducer block, the outputs of which are connected to the matrix element tl This device has a relatively simple design, but does not allow for a sufficiently high accuracy of speech synthesis. Also known is a digital lattice speech synthesizer filter containing input busses of filter coefficients connected to a block of shift registers whose outputs are connected to a matrix multiplier connected to the first input of the adder and extractor, delay element for one period, shift register, memory element , the input bus of the signal components of the sound, the input bus of the digital-to-analog converter and the keys 2. Although the indicated device provides relatively high accuracy of speech synthesis, however, significant bubbled envelopes. The purpose of the invention is to reduce the size of a digital lattice filter, speech synthesizer. The goal is achieved by connecting the output of the addition and subtraction unit via the first key to its second input connected via the second key to the input bus of the signal components of the sound, and connected to the delay element for one period connected by the output to the shift register whose output is connected through the third key with the input of the memory element connected by the output to the input bus of the D / A converter and connected via the fourth key to the input of the matrix multiplier, and the input of the matrix multiplier L is connected via the fifth and sixth keys, respectively, to the subcontrol unit of the addition and subtraction and the delay element for one period, and the second input of the addition and subtraction unit through the seventh and eighth keys, respectively, to the outputs of the shift register and the memory element. The drawing shows the proposed device, one of the options. The digital trellis filter contains input ratios of 1 coefficients.

filtering connected to the shift register unit 2, the outputs of which are connected to the matrix multiplier 3 connected to the first input of the addition and subtraction unit 4. The output of the latter is connected via the first key 5 with its second input connected via the second key 6 to the input bus 7 of the sound components and connected to the delay element 8 for one period. The delay element for one period is connected by an output to the shift register 9, the output of which is connected via the third key 10 to the input of the AND memory element. The output of the long-term is connected to the input bus 12 of the digital-to-analog converter and connected via the fourth key 13 to the input of the matrix multiplier 3, the input of which is connected through the fifth 14 and sixth 15 keys respectively to the outputs of block 4 of addition and subtraction and delay element 8 for one period. In this case, the second input of the block 4 for addition and subtraction is connected via the seventh 16 and eighth 17 keys, respectively, to the outputs of the shift register 9 and the memory element 11.

The filter works as follows

The input bus signals 1 of the filter coefficients are fed through a shift register unit 2 to a matrix multiplier 3, which also receives signals from the outputs of memory element 11, addition and subtraction unit 4, and delay element 8 for one period, respectively, through the fourth 13, fifth .14 and the sixth -15key locked at different time intervals. From the matrix multiplier 3, the signal is fed to the first input of block 4 of addition and subtraction, to the second input of which the signal of the components of the sound is fed.

The present invention significantly reduces the size of a digital speech synthesizer trellis filter.

Claims (2)

1. Japanese Patent No. 50-4402, class 96 (3) A 02, published. 1975. 2. Japanese Patent No. 50-19881, cl. 96 (3) A 02, published, 1975 (prototype),.