CS266303B2 - Digital filter - Google Patents

Abstract

The digital filter comprises a memory (31) storing filter coefficients, a multiplier (30) multiplying internal data of the filter by the said filter coefficients, an adder/subtracter (33) adding the results of the multiplications to other data obtained in the filter, a delay circuit (34) connected up to the output of the adder/subtracter, a shift register (35) storing and retrieving at the requisite the time the data coming from the delay circuit, and an interlock output memory (36) storing a datum output by the filter. These various elements are interconnected with the aid of switches (37, 38) in order to perform the successive operations of multiplication and addition during a cycle. This filter, equivalent to a lattice filter, can be used in a voice synthesizer. <IMAGE>

Description

The present invention relates to the generation of complex waveforms using digital signals, in particular digital circuit speech synthesis using linear prediction methods and the object of which is a cross-type digital filter for circuits intended for speech synthesis or time waveform generation. The speech synthesis filter of the present invention may be contained within a single integrated circuit, thereby facilitating its use in a variety of industrial applications (i): у, 'Ί l ih ih rh> ih ih ih ih ih í г.-1гп) п, л »1 * '1пулг (devices such as telephones, speech secrecy devices, radio and television equipment, etc.) and other devices that generate the sound of a human voice.

Currently, several methods of digital representation of human speech are used in practice and in experiments. For example, the following methods of digital speech coding are known: pulse code modulation, differential pulse code modulation, adaptive prediction coding, delta modulation, channel vocoders, voice excited vocoders, cepstral vocoders, formant vocoders, and linear prediction coding. These methods are briefly described in Voice signals: Bit by bit on pages 28-34 of IEEE Spektrum, October 1973.

Simulations of individual digital speech coding methods generally show that linear predictive digital speech prediction methods can provide more natural speech than earlier vocoder systems (eg, a channel vocoder) at a concurrently lower data flow than pulse code modulation systems. Linear prediction systems often use multistage digital filters, and the higher the number of degrees, the more natural the resulting generated speech becomes.

The first applications of linear prediction methods for digital speech generation fall into the late sixties and early seventies. A historical analysis of some of these early works is given in Markel and Gray's Linear Prediction of Speech (Spriqger Verlag, New York 1976) on pages 18-20.

The multistage digital filter used in linear prediction coding is preferably of the all-pole type, with all roots preferably within the unit circle (z) = '1, if the mathematical transfer function is expressed as a z transformation. 2a and 2b, however, other types of filter are known, including rung filters, normalized rung filters, and others, as explained in Chap. 5 books Linear Prediction of Speech. Each step of the cross-link filter requires two addition operations, two multiplication operations, and one delay operation. The filter is excited either from a periodic signal source for loud or from a random signal source for loud noises. Preferably, the filter coefficients are reset every few milliseconds, while the excitation signal is repeatedly applied more frequently.

Previously, the filter circuitry of the cross-cells of FIG. 2a was implemented by suitable programming of large digital computers. An example of programming a computer in Fortran for computer speech synthesis is explained in the aforementioned book Linear Prediction of Speech. Given the data flow of the wake-up signal and the large number of arithmetic operations, ie two multiplications and two additions for each stage of the multi-stage filter, and since increasing the number of filter stages increases the naturalness of the generated speech, fast digital computers. Attempts have also been made to implement a multi-stage filter using the technique of large integration circuits with MOS-type elements and the multiprocessing principle with a number of arithmetic units operating simultaneously; however, this technique requires the implementation of a very large number of multiplication and addition circuits on a single semiconductor substrate. By replacing the lattice structure in Fig. 2a with individual adders and multipliers, a complex and extensive semiconductor substrate is formed.

In US Pat. No. 4,022,974 discloses a speech synthesizer which comprises a recursive or a partition filter as part of it. Such a recursive filter needs only two mathematical operations to perform, one multiplication and one addition, but it does not have the inherent stability of the cross-cell filter.

CS 266 303 B2

US Pat. No. 4,052,563 is directed to a speech transmission system comprising an analysis section and a speech synthesis section. After the speech waveform analysis, the resulting encoded digital signal exists in each of the plurality of transmission channels carrying the respective synthetic speech signals. The clear speech signals in the plurality of speech channels are encoded by multiplexing the digital outputs, which then exit) to bring into the ééΙéééééééééééééééééééééééééééééééééΐéΐΐΐΐΐΐééééééééééééééééééééé Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení Provedení na na na na na na 8 na 8 na 8 shows a single digital multiplier filter with feedback and multiplexing, wherein multiplexing is also required between a series of temporary memories according to the channel timing of the time-multiplexed signal resulting from a series of separate speech channels. entrance only pros However, the digital filter is not described in detail and can only be assumed to correspond to the embodiment of FIG. 6, which includes a series of arithmetic units cooperating with a multiplier and including two adders and a subtractor.

The present invention eliminates the disadvantages of prior art filters and relates to a digital filter with digital excitation signal inputs and digital values displaying filter coefficients, particularly for speech synthesizers, consisting of a coefficient stack connected by a multiplier line, a subtractor-subtractor whose input is connected to a multiplier output. and the output is connected to a memory circuit whose output is connected to the multiplier input by a bus. SUMMARY OF THE INVENTION The first switch is connected to the bus at the multiplier input to selectively connect the adder-subtractor output and the memory circuit output to the multiplier input. The memory circuit includes a first delay circuit with a short delay time, a second delay circuit with a longer delay time, and a memory coupled via the first switch to the multiplier input, the output of the first delay circuit being connected to the multiplier input. At the adder-subtractor input a second switch is connected to selectively connect the adder-subtractor output, the second delay circuit and the memory to the adder-subtractor. Preferably, the first switch comprises switches for selectively adding the adder-subtractor output, the first delay circuit output or the memory output to the multiplier input, and the second switch comprises switches for selectively adding the adder-subtractor output, the second delay circuit output or the memory output to the adder-input. odčítačky. A third switch is connected between the second delay circuit and the memory to selectively connect the output of the second delay circuit to the memory input.

The invention makes it possible to implement a cross-link filter to generate complex waveforms, such as human speech, on a single substrate using MOS structures, which is relatively simple and has smaller dimensions.

The invention and its features will be explained in conjunction with the embodiments shown in the drawings, in which Fig. 1a shows a block diagram of the basic elements of a speech synthesizer, Fig. 1b shows the timing of the excitation signal and the coefficients K _n Fig. 2a, 2b Fig. 3 timing for generating intermediate results in a N-degree cross-section filter, Fig. 4 timing for generating intermediate results in a 10-degree cross-section filter, Fig. 5 one embodiment of a digital filter equivalent 6 shows another embodiment of a digital filter, an equivalent cross-link filter, FIG. 7 a matrix multiplier used in an equivalent digital filter. Giant. 8A to 8D are logic diagrams of the individual elements of FIGS. 7 and 9, a generalized shape of a digital filter according to the invention.

Fig. 1a shows the basic elements of a speech synthesizer in block diagram form.

The speech synthesis circuit comprises a multi-stage cross-link filter 10 that digitally filters the excitation signal U using coefficients Κχ ^to * _n . ^{At the} output of the cross-link filter 10 is a digital signal 12 which is converted by analog-to-analog converter 13. The output of the converter 13 changes into audible sounds through the loudspeaker

CS 266 303 B2 or other sound transducer; it will be understood that amplifiers may be used between the converter 13 and the loudspeaker 14 to amplify the analog output of the converter 13 to the level required for the loudspeaker 14.

The excitation signal U is generally derived from one of two sources, the source 15 of the loud alarm of the drawbar wall 16 silence 1 annélio algnúlu. The one of the two * is determined by the digital switch 17. · The source 15 of the loud signal is used to generate sounds during which human vocal cords or vocal ligaments vibrate, such as the E sound in the word Eva. The speed at which voice ligaments close and open determines the pitch of the generated sound. The non-loud signal source 16 is used in generating sounds such as F in the word Fish, where the voice ligaments are permanently open and air is blown through them into the vocal tract. Thus, the source 15, 16 used depends on the sound to be generated.

Generally, the loud signal source 16 generates a random digital signal, while the loud signal source 15 generates a periodic digital signal. However, the digital data supplied by the two sources 15 and 16 may be stored in one or more permanent memories. However, it is preferable to store this data in a coded form, e.g. as a voice pitch or as a code controlling a random number generator. As a rule, the data is first decoded before random or periodic data (e.g., a V signal) is sent to the .10 filter. However, depending on how the data is stored, it is possible to eliminate the need for a switch 17. When the data is stored For example, as a voice pitch or code to control the random number generator, the gain A is preferably also stored in the permanent memory. The gain A adjusts the constant amplitude signal V from the loud signal source 15 or from the loud signal source 16 to produce a wake-up signal filter 10.

The excitation signal U, which generally corresponds to or modeles the function of the voice ligaments, is changed by the filter 10 of the cross-links. The cross-link filter 16 generally corresponds to or modeles the voice tract function that filters the sounds generated by the voice ligaments. The filter coefficients K i to K _n show the shape (ie resonance) of the voice tract during speech. Therefore, the coefficients Ki to K _n periodically re-adjusted to correspond to changes in shape of the vocal tract, and can be saved with the data signal and the loud nehlasného resources to permanent memory.

In Fig. 1b, the time course of the output of the loud source 16 and the loud source 15 is shown as a graph. At the output of the loud source, pulses with a period of 5 ms, corresponding to a voice pitch of 200 Hz, are indicated; this pitch corresponds to the loud sounds in the vocal range of many women. Because men typically have a lower pitch, the output pulses for the male speaker will have a lower repetition rate.

The loud source 15 is indicated with output pulses whose period corresponds to the pitch of the person's voice; however, it should be understood that the periodic pulses can be replaced by other periodic functions, such as the fading sine wave or the so-called chirping, which are repeated with a period corresponding to the pitch of the voice. The signal of the loud source 16 is indicated as random.

In Fig. 1b it is indicated that the cross-section filter coefficients 10 are reset every 5 ms. It is to be understood that the frequency setting of the filter coefficients 10 is selectable at design. The more often the coefficients are set, the more precisely the filter 10 modeles the dynamics of the voice tract, but with a corresponding increase in the amount of data stored in the aforementioned non-volatile memory. However, the less frequent adjustment of the coefficients has the opposite effect. It has been found that by adjusting the coefficients approximately every 5 ms, high quality human speech synthesis is achieved with a cross-link filter 10 with reasonable memory capacity requirements.

In Fig. 1b, the timeline is divided into intervals of 100 ms. These intervals correspond to the frequency data from the loud source 15 _f of nehlasného source 16 and frequency of data input and output filter 10 of cross-links. Although it may appear from Fig. 1b that the signals from the loud source 16 and the loud source 15 are analogous, it should be noted that

In fact, these signals are digital signals whose size is indicated and which are reset at the intervals indicated in the timeline in Fig. Ib. Regarding Information regarding the Derivation of Filter Coefficients, reference is made to the previously mentioned book ^by Lin &amp; Prodlet i on Sponch.

*

Thus, in the configuration, the data rate at the input of the converter 13 will be 10 kHz and the upper limit of the synthetic speech from the converter 13 will be 5 kli. However, this frequency can be changed according to the design. For example, a 9 kHz data rate would trigger a 4 kHz synthesizer cutoff frequency.

2a and 2b, a block diagram of a cross-link filter 10 is shown. Fig. 2a shows a cross-link filter 10 comprising ten stages S1 to S10, each of which is equivalent to that shown in Figure 2b. For clarity, only three stages are shown in detail in FIG. 2a. At the input of stage S10 there is an excitation signal U and the output 12 of stage S1 is supplied to the converter 13 (see FIG. 1a). One skilled in the art will recognize that the output 17 of stage S10 is not used, so that the adder 17a and the multiplier 17b can be omitted.

In Fig. 2b, a single stage Sn of the cross-link filter 10 is indicated. The input (jL) to this stage is fed to one input of the first adder 18, the output of which is Y _n (i). The second input of this first adder 18, which is fed to its subtraction input, is derived from the output of the first multiplier 19, which multiplies the coefficient by the output b _n (i-1) of the delay circuit 22. The output of the delay circuit 22 is also fed to the second adder. 21, which receives the output from the second multiplier 20 at the second input. The second multiplier 20 multiplies the coefficient K by the output from the first adder 18, which is, however, equal to Y _p (_i). The output of the second adder 21 is b ₊ + (i). As can be seen, the index u Y ab determines the degree to which the data is used, while the number in parentheses indicates the cycle in which the data is generated. The delay circuit 22 performs a one-time delay function such as a shift register. Once in each time cycle, a new data value U (i) of data (or Y ^ j (i.)) Is applied to stage S10 as an excitation signal U. Thus, two multiplication and two additions, i.e. at the data frequency of FIG. Ib, these four operations must be performed at each stage of the filter 10 during 100 / is. The cross-link filter 10 of Figure 2a was designed with ten stages; however, it is known to the skilled person that the number of stages can be selected according to the desired quality of the sounds synthesized by the filter 10. It has been found that a 10-degree cross-cell filter can generate synthetic speech that is virtually indistinguishable from real human speech.

Obviously, during any time cycle, ten stages of the cross-link filter 10 must perform twenty multiplication operations and twenty addition / subtraction operations. Further, we find that all these operations cannot be performed simultaneously, since ř ^ θ must be calculated earlier than Y, which must be calculated earlier than Υθ, etc., in each time cycle. During the same time cycle, it is also necessary to calculate _b10 to b4 and insert them into the delay circuits 22 of the individual stages for use in the following time cycle. The variables Y and b, as defined in Fig. 2b, are also indicated in steps S1, S9 and S10 in Fig. 2a. The equations giving the relationships between the individual variables Y and b are given in Table. I. It should be noted that the variables Y and b and the coefficients are several-digit numbers; coefficients up to Κ ^ θ can range in decimal equivalent between plus one and minus one and are periodically adjusted as described.

Fig. 3 shows, in an illustrative form, the individual intermediate results obtained from multipliers and adders of the N-step filter from the cross-links; the horizontal axis shows the time and the vertical individual stages of the N-stage cross-link filter 10. E.g. in the Nth stage, the intermediate results -K _n «b _n and Κ _η · Χ _η * are generated by multipliers 19 and 20 (see Fig. 2b) and the intermediate results Y _n and obtained from the adders 18 and 21 (Fig. 2b). Time must be PartResult -η' ^{enerov 9-n-n} before they can gain Yfi; Yn must be generated before Κη · Χη can be generated ^and ϋη · Χ _η ^{must be} generated before generating b _{n +} i «According to the indicated time scale, the addition operation requires an interval of 5 yUs, while multiplication requires a longer time

CS 266 303 B2

section. Regarding interrelationships of generating intermediate values in each stage, it is seen that the output of the addition operation must be available before starting к multiplication operation .rK _n ».b. _n as indicated by the arrow 2j>. This forces the insertion of an empty operation interval 23 between the addition operation b _{n + 1} and the multiplication operation -K _n »b _n when only one addition operation and one multiplication operation such as p < il.ino of J. J destroyed 24 paused operations яе insert between the second addition operations and subsequent multiplication operations because of symmetry. As can be seen, the operations outlined in all stages of the N-stage cross-link filter can be performed simultaneously in the order shown in Fig. 3 and the respective intermediate results will be available as needed. Giant. 3 shows the overall nature and usability of the digital implementation of the multi-stage cross-link filter that we will describe. It should be noted that the illustration in Fig. 3 shows operations performed during one of said time cycles. The time interval 5 / is for the addition operation was chosen at design since it corresponds to MOS type ICs with p channel. However, other time intervals may be used if desired. < ^? * \. v '!

Fig. 4 is a similar view to Fig. 3 except that Fig. 4 represents the numerical realization of the equivalent of a 10-degree cross-cell filter 10 and the horizontal axis has been extended to show more than one cycle of time. In addition, each time cycle was divided into twenty intervals T1 to T20, each preferably having a duration of the order of 5 / is. As already mentioned, it is possible to choose another duration. In FIG. 4, the time cycles i-1 and i + 1 are also indicated to facilitate comparison of the arrival of the intermediate results in the filter 10 with the requirements resulting from the mathematical expression representing the filter 10 in Table 1. AND.

In the first interval T1, an excitation signal U is applied to the input; the output Y ^ from the filter is obtained in the interval Til. In comparison, FIG. It can be seen that the individual inputs required for multiplication operations are available when needed, and also that the individual inputs for addition operations are available when needed. Z obř. 4 further shows that the addition operation (which lasts one interval) starts and ends at each interval, and similarly, that the set multiplication operation also starts (and finishes) at every interval, even if a specific multiplication operation triggered is completed after eight intervals. The apparatus performing these operations will be described in more detail with reference to FIGS. 5, 9 and 10a-10d.

We have stated that multiplication and addition operations are preferably triggered at each time interval. In fact, the number of time intervals per cycle is preferably equal to twice the degrees of the equivalent cross-link filter. Thus, for an eight or twelve step cross-link filter, the equivalent digital filter will preferably have sixteen or twenty-four intervals per cycle. 3 and 4, the number of time intervals allocated to the multiplication operation depends in part on the number of intervals in the cycle. Eight intervals can be used for a multiplication operation in a 10-degree equivalent digital filter, while six intervals can be used in an 8-degree equivalent digital filter, as long as the digital equivalent filter shown in FIGS. 3 and 4 is used. multiplication determines the number of bits that are multiplied, ie limits the number of bits displaying coefficients К. In most applications, the number of bits allocated to the coefficients K _n in the arrangement of FIGS. 3 and 4 will provide a very acceptable synthetic speech. However, if even greater accuracy is required for the display of the coefficients K, it is not possible to run multiplication and addition operations at each cycle interval, and some delay at a cycle point will have to be entered. Then, however, the cycle will require a longer time to complete, thereby reducing the system's data rate (and frequency response).

As can be seen from FIG. 4, intermediate results can be obtained or intermediate results can be obtained, but, as mentioned in FIG. 2a, these particular intermediate results are not required in the digital implementation of the cross-link filter. Referring to Fig. 5, we show that the intermediate results ^K 10'-10 ^and - 11 ^or some other numbers are often easier to generate and neglect than to prevent the device from performing these calculations. In the next we describe how the multiplication operation, performed by multiplier 18 (Fig. 1) can be done instead of calculating K _1Q course, Y ₁₀ in the device.

CS 266 303 B2

Fig. 5 shows a block diagram of a digital implementation of an equivalent cross-link filter 10. The content of the contents is a matrix multiplier 31, a reader / subtractor 33, a first delay circuit 34 for one interval delay, a second delay circuit 35, and a memory 36. It has an incoming and outgoing one-inch in each of the twenty. The time intervals T1-120 (for the equivalent 10-stage filter) are shown in FIG. 6. The matrix multiplier 30 of FIGS. 5 and 6 realizes the multiplication performed by the multipliers 19 and 20 (FIGS. 2a and 2b) in each. from a 10-degree cross-link filter. Matrix multiplier JO. it receives, via lines 32, the coefficients Κ _χ to Κ ^ θ stored in the cartridge 31, and the bus 40 to either Y ^ or b ^. The cartridge 11 preferably comprises ten shift registers, each having ten degrees. The data stored in the stack of coefficients J1 are shown in Tab. The matrix multiplier 30 triggers further multiplication operations at each time interval (as indicated in FIG. 4), i.e. approximately every 5 / is. The matrix multiplier 30 preferably has eight stages as shown in FIG. 9. A series of addition and feeds operations take place as the data is shifted by these eight stages and the data is multiplied by the respective coefficient K _n stored in the coefficient stack 31. The multiplication operation takes 40 / is; since the new multiplication operation begins every 5 / is, there is eight multiplication at each time at a different degree of elaboration. The eight matrix multiplier calculation intervals 30 are shown in Figure 6 along with the multiplier inputs and outputs. For example, multiplier inputs in the T1 interval output from the multiplier eight intervals later, ie in T9. The coefficients stored in stack 11 are stored as nine-bit numbers with one additional bit for the sign. As stated herein, these numbers range from -1 to +1 (in decimal), which simplifies the matrix multiplier structure of 30.

The output of the matrix multiplier 30 is fed to the adder-subtractor 11. This output takes the form of a thirteen-bit parallel channel in the proposed configuration: 12 bits of data and 1 bit for the sign. However, it is clear that the number of bits of the data channel is a design issue. The second input arrives at the adder-subtractor JJ via the second switch 37 and consists of a wake-up signal U at intervals T1, at the intervals T2 to T10 the adder-subtractor JJ intervals, at T1 to T19 intervals the second delay circuit 35 and T20 memory JJ . For the sake of clarity, simple single-pole switches 37A to 37D are shown at the adder-subtractor 33; however, it will be appreciated that it will be preferable to use solid-state switches for both these switching functions and the other switching functions indicated. The output of the adder-subtractor 33 is applied to switch 37B of second switch 37, to the input of the first delay circuit 14 for a one-time delay, and to switch 38A of the first switch 38 connected to the bus input 40. The output of the adder-subtractor 33 is also implemented as a 13 bit wide channel, which is delayed by one interval in the delay circuit 34 before being applied to the input of the second delay circuit 35 and to the switch 38B of the first switch 18. The second delay circuit 35 stores data from the thirteen-bit channel in thirteen shift registers, each of which has eight degrees. The second delay circuit 35 is arranged such that the displacement is performed only at intervals T1 to T2. The output of the second delay circuit 35 is fed to switches 17c and 39. This switch 39 closes at the interval T20 for timing the output Y1 of the filter to memory 36. The output 12 of memory 36 is fed to the analog-to-digital converter 13 (FIG. 3d and 38c.

Switch 37b is closed at intervals T2 to T10, switch 37c is closed at intervals T1 to T1J, and switch 37d is closed at T20. Switch 38a is closed at intervals T13 to T1, switch 38b is closed between intervals T3 to T12, and switch 38c is closed at T2. The other sides of the switches 38a, 38b and 38c are coupled by the bus 40 to the input of the matrix multiplier 10.

FIG. 6 shows the individual intermediate results that appear in the circuit of FIG. 5 at time intervals T1 to T20. In Fig. 6, one input of the multiplier is information of the coefficient K i, while the other input varies according to which of the switches 38a to 38c is closed. In the interval T1, the switch 38a is closed, as already mentioned, so that the output of the adder / subtractor 31, in this case b ₂ (i-1), is applied to the multiplier input. At the same time, the second input of the adder / subtractor 33 receives the drive signal U (i). In the interval T2, the value of b _x (i-1) is input to the multiplier 30, which, according to FIG. 5, comes from the memory output 36 via the switch 38c.

CS 266 303 B2

Referring to FIG. 6 the output of the memory is 36 Υ _χ (i - 1), but according to the last item tab. I find that b ^ (i__2__i) is equal to the delayed γ _χ (_i), ie (i - 1). In the interval T2 the second input of the adder / subtractor 33 is supplied with an instantaneous output of this adder / subtractor, i.e. in this case X ₁₀ (i) · ^{in the} interval T3 there are inputs of a multiplier of K _{i Q} and X ₁₀ (i) derives from the output of the first delay circuit 344.

At the interval T1, a second delay circuit 35 is output to the second input of the adder / subtractor 33. The first expression coming from the second delay circuit 35 is (i-1) that first appeared at the output of this delay circuit 35 at interval T2 and This output remains, since the delay circuit 35, as mentioned above, does not shift between the intervals T3 and Til.

At the interval T13, the addition of the adder / subtractor 33 via the switch 38a is again supplied to the input of the matrix multiplier 30. In the interval T20, the value of Y ^ (.i) from the second delay circuit 35 outputs to the memory 36 and the current output of the memory 36, Y ^ (i-1) is fed to the second adder-subtractor 33 via switch 37D to obtain the value b ^. (i - 1) as we mentioned earlier. The memory 36 stores the filter output Y1 for one cycle.

The filter of FIG. 5 can also be used in an application equivalent to an N-stage filter with an M-stage multiplier (for example, the coefficients may have M + 2 bits) if a shift register with a delay equal to or lower is inserted between the adder-subtractor 33 and the first delay circuit. N - M - 2 time intervals. The connection to the switch 38A is then made from the output of this added shift register and the delay in the second delay circuit 35 is set to N + Μ - 1. This generalized filter shape is shown in Figure 9. In the arrangement of Figure 5, N - M - 2 equal to zero, so no delay is required in this case.

In the filter of FIG. II is N + Μ - 1 equal to seventeen, which corresponds to the number of time intervals between the time the data arrives at the second delay circuit 35 and the data output from the second delay circuit 35. For example, FIG. in tab. II, the value b1 (i-1) is input to the second delay circuit 35 at the time interval T2 and is based on it at the interval T19, that is, seventeen intervals later. However, the second delay circuit 35 has only eight degrees in this embodiment and the additional delay occurs at intervals T3 to T1 when the second memory circuit 35 formed by the shift register is not shifted. These nine time intervals take place at a time when the values of Y2-Y10 are at the output of the first delay circuit 34 and are not to be fed to the second delay circuit 35, as shown in Tab. II. Thus, the number of degrees in the second delay circuit 35 plus the number of time intervals in one cycle when the data in the small delay circuit 35 does not shift is equal to the delay N + Μ - 1 time intervals in the second delay circuit 35.

As can be seen, the equivalent ten-stage filter of FIG. 5 performs the filtration operation achieved by the cross-link filter of FIG. 1a at a satisfactory speed. For example, in the proposed arrangement, a 10 kHz excitation signal U is provided, i.e. every 10 0 / is, and the basic operation in both the adder / subtractor 33 and the matrix multiplier 30, in the first delay circuit 34 and in the second delay circuit 35 performed at nominal intervals of 5 / is. It is known to those skilled in the art that these speeds are well achievable by using MOS large integration with the p-channel so that the entire filter of Fig. 5 can be realized as a relatively inexpensive MOS large integration with the p-channel for speech synthesis or generating complex waveforms.

It will be appreciated by those skilled in the art that the basic arrangement of the 10-stage cross-cell filter of FIG. 5 is also applicable to digital filters equivalent to cross-cell filters with a different number of degrees. Ten degrees were selected for the chosen filter arrangement because ten-stage cross-cell filters were chosen by the US Department of Defense as the standard for use in prediction coded speech synthesis circuits. However, should it be desired to use the present invention to realize a digital filter with a different number of equivalent degrees, it should be noted that the number of

CS 266 303 B2 shall be at least twice the number of degrees equivalent. In the selected arrangement, the number of intervals (twenty) is twice the number of equivalent stages (ten). For example, if we wanted a 12-stage equivalent filter, the number of intervals within a cycle should be at least twenty-four, and the described basic solution would extend somewhat. Лг need рот namona t, ·>. «·» For twelve 11 n I clamp. ·) <In I VI last year II i The Chinese face lily will need ten intervals to perform multiplication, based on the basic scheme described above. that is, one addition operation and one multiplication operation are triggered at each interval. This is evident from Fig. 3 if we substitute N = 12 and add the diagram accordingly. However, if the interval of 5 / is kept for each interval, the data rate obtainable by the 12-stage version will be lower than that of the 10-stage version of the filter. It should also be noted that by increasing the delay in the matrix multiplier 30, it is also possible to increase the number of bits of the coefficients up to ^{2 of the} total number of ten to a total of twelve bits. Similarly, if we wanted an equivalent eight-stage filter, the number of cycle intervals would be at least sixteen, and by inserting N = 8 in Figure 3, we would find that the pass time of the multiplier of 30 would be six itals. In this case, using a matrix multiplier, which will be described in more detail below, would limit the number of coefficient bits in stack 31 to a maximum of 8 bits. However, as mentioned earlier in the description of FIG. 4, in some cases even more time intervals can be used to perform the multiplication operation. This may be desirable when designing an increased accuracy of the coefficients К. This increased accuracy will require more bits of the coefficients K _n , which in turn requires a greater delay in the matrix multiplier 30. The basic solution of the equivalent filter of FIG. 5 is thus somewhat modified, since the multiplication and addition operations then do not start at every time interval. It will be apparent to those skilled in the art that in this case some of the intermediate results need to be stored temporarily, requiring additional filter elements to be added to the filter of FIG. These modifications are not described in detail here, since such modifications of the digital realization of the filter are among the capabilities of an experienced digital circuit designer.

We have previously stated that the digital filter of FIG. 5 generates intermediate results

But that these intermediate results are not used, since they are not required for the realization of the filter 10 of FIG. 1a. Recalling that the data V from a loud or non-loud source is multiplied by the gain factor A in the multiplier 18 in the known speech synthesis circuit of FIG. 1a, we find that this multiplication can be performed by a matrix multiplier 30 at the time the multiplier generates product Κ ^ θ. (i.). Digital filter arrangement with multiplication V (i). A is shown in FIG. IV shows the individual intermediate results generated in the circuit of FIG. 7.

FIG. 6 and FIG. It can be seen that this circuit, including the generated intermediate results, is similar to the circuit of Figure 5 with the modifications that follow. The reference numerals in FIG. 6 are the same as in FIG. 5. Data V to be multiplied by the factor A is fed via switch j38_D to one input of matrix multiplier 30 at intervals T3 instead of the output signal from the first delay circuit 34 for one delay. interval. In the interval T1, when the multiplication is complete and U (i + 1), i.e. AV (i + 1), it enters the second input of the adder-subtractor 33, instead of outputting _Q (i - 1) from the second delay circuit 35, logic zeros. However, the coefficients K as well as the gain A must be inserted into the coefficient magazine 31. As can be seen from FIG. 6 and tab. IV, this arrangement incorporates the function performed by the multiplier 18 in FIG. 1a into the digital implementation of the cross-link filter 10. The data stored in the stack are shown in Tab. V. The gain factor A update is preferably performed as frequently as the update of the coefficients K _n in the stack 31.

In Fig. 7, a matrix multiplier 30 is shown in block diagram form

1 to 32-9 receive the lowest to highest coefficient bit from the coefficient stack 31. On line 32-10, the sign enters from the coefficient stack 31. The second input to the matrix multiplier 30 is via the bus 60. The lines 40-1 to 40-12 of the bus 40 carry the lowest to the highest bit, and the lines 40-13 carry the sign of the data to the bus 40.

In Fig. 7 there is a matrix of elements labeled with the letters А, В, C and D (the elements označeníег are

CS 266 303 B2 also type A, i.e. also correspond to Fig. 8a). Elements A to D correspond to the circuits of Figures 8A to 8D. In Figures 8A-8D, the circuits are delimited by dashed lines with certain wires extending beyond these dashed lines. The relative position of the wires crossing the dashed lines in FIGS. 8 to 8D corresponds to the wiring connecting the elements A to D in FIG. 7 in FIG. 7. In FIG. 7, the elements are arranged in eight rows and twelve columns. The eight rows correspond to the aforementioned eight stages of the matrix multiplier 10. These n and th are denoted n n right n Fig. 7 and contain eight shift register cells 51 connected to lines 40 ~ 13. Twelve columns correspond to twelve bits of digital data on lines 40-1. Up to 40-12 entering matrix multiplier 30. Data on lines 40-1 through 40-13 travels through matrix multiplier 30 degree by step as a shift register while multiplying it in matrix multiplier 30, propagation time to any degree is of the order of 5 ^ s. as previously stated.

The line 32-1 from the reservoir 31 is connected to one input of twelve product gates 51-1 to 52-12, whose second inputs are individually connected to the lines 40-1 to 40-12. The outputs of these gates 52-1 to 52-12 are connected to inputs of Subtotals · elements of type А а В stage 1 (see Fig. 8A а 8B).

The lines 32-2 to 32-8 from the magazine 31 are individually connected to the coefficient inputs to the type A elements (Fig. 8A) in stages 1 to 7 of the matrix multiplier 30. The lines 32-9 are connected to the same labeled input of the type C elements of stage 8 (see Fig. 8C). Data on lines 40-1 through 40-12 are fed to and through the data inputs and stage 2 elements through their data outputs and further to stages 2 to 8. The input b of the subtotal of stage 1 elements is derived from gate outputs 52-1 to 52 - 12. In the next stages, it is derived from the outputs and the subtotal of the next higher bit of the previous stage, with the exception of the partial input.

the sum of the elements in the highest bit (order), where the subtotal input is derived from the výstupu transmission output c from the highest bit of the previous stage. In addition, the transmission outputs c * of the elements are connected in series with the transmission inputs c of the elements at each stage.

Referring to FIG. 10A, the data from the stack 31 determines whether the subtotal output b is coupled directly to the subtotal input b through the transfer gate 60 or the output of the exclusive sum circuit 62 via the transfer gate 61. The product gate 63 and the exclusive sum circuit 64 it controls the signals at data input a and at sub-sum input b. The exclusive sum circuit 62 controls the output of the exclusive sum circuit 64 and the signal at the transmission input c. The automatic gate 65 controls the output of the exclusive sum circuit 64 and the signal at the transmission input e and its output is fed together with the gate output 63 to the summation inputs. The data output b corresponds to the signal at the data input b through a delayed section of the shift register 62, consisting, for example, of two inverters. As can be seen from Fig. 8C, the type C element is identical to the type Λ element except that it does not contain a data output and 'nor the shift register 62. In Fig. 8B a type B element which contains only the shift register 67' is indicated. coupled to the data input a and data output a -, and the product gate 68 coupled to the data input a and sub-sum input b and forming the transmission output c '. Fig. 8D shows a D-type element generating a transmission output c 'from the product gate 68' to which the data input a and the sub-sum input b leads.

As can be seen, a new subtotal is calculated at each stage, including the necessary transmission of transmission information between the stage elements, but the output of the subtotal does not change if the line from the coefficient stack 31 is logical zero or added to the input data to obtained a subtotal output if logical 1 is on the line from the coefficient stack 31. Subtotals shift to other lower locations as data passes through a matrix multiplier. However, at each stage the lowest bit is lost. However, the coefficients K _n from stack 21 correspond to numbers ranging from -1 to +1. Thus, if logic zeros appear on lines 32 1 to 32 - 9, the output from the matrix multiplier will be zero, and vice versa, if all bits on lines 32-1 through 32-9 are one, the data output across bus 40 passes through the matrix multiplier without changes. For the other possible combinations of data on lines 32-1 to 32 - 9, the data on bus 40 will be scaled between zero and the value input on bus 40 in 29 possible steps according to the data size on lines 43-1 to 32-2.

CS 266 303 B2

As the data passes through the stages of the matrix multiplier 30 as if it were a shift register, the data from the coefficient stack 31 is shifted differently, as is evident from e.g. III and tab. In order to ensure that the correct bit of the correct coefficient arrives at the right moment at the matrix multiplier 31. FIGS. 8-16 to 8C do not show timing pulses for controlling the counter face. .1 <<> vt 1 у The mane of the above-mentioned as a rog i tru tru · interleaves, as is well known to those skilled in the art, can be obtained by adding clock-controlled gates to the circuits of FIGS. 8-1 through 8C or using logic circuits. using pre-charge and conditional discharge, and therefore these timing considerations are not detailed here.

According to Fig. 7, the sign data on lines 40-13 is only delayed in the eighth stage of the matrix multiplier 30 in the shift register elements 51 and then compared with the sign data from the coefficient stack 31 on lines 32-10 in circuit 53 for the exclusive sum to obtain the correct sign of the output data according to the usual multiplication rules.

The matrix multiplier 30 shown in FIGS. 5 and 6 has been described in detail. The remaining elements, such as adder-subtractor 33. ' the first delay circuit 34, the second delay circuit 35, and the memory 36 are not described in detail, as these conventional elements are well known. Adder-Subtractor 33 receives data including a sign at its inputs and must decide whether a subtraction or addition operation is required by the sign coming with the data.

Table I

Equation Degree ^Y io ⁽ⁱ⁾ = - ^K 10 ^b 10 < ⁱ - ^{11 10}

Y, (i) = Y ₁₀ (i) - Kjbgli 9 bi ₀ (i) = _b9 (i - 1) + KgYgii) 9 ^Y 8 = Y ₉ (i) - Va ⁽ⁱ - ¹¹ 8 b ₉ i - ba ' ¹ ' 1) + KgYg (I) 8 Y ₇ (i) = ^Y and ⁽ⁱ > - K _? b ₇ (i -1) 7 b ₈ (i) = b ₇ (i - 1) + to ₇ y ₇ (i) 7 Y ₆ (i) = Y ₇ (I) - w ¹ - 6 b ₇ (i) = b ₆ (i - (i) ₊ K ₆ Y ₆ (i) 6 Y ₅ (i) = Y ₆ (i) - K ₅ b ₅ (i-1) 5 b ₆ (i) = b ₅ (i - 1) 4- K ₅ Y ₅ (i) 5 Y ₄ (i) = Y ₅ (i) - K ₄ b ₄ li - η 4 b ₅ (i) = b ₄ (i - i) + k ₄ y ₄ U> 4 Y ₃ ⁽ i) = Y ₄ (i) - K ₃ b ₃ (i-1) 3 b ₄ (i) = b ₃ (i - 1) + K ₃ Y ₃ (i) 3 Y ₂ (i) = Y ₃ (i) - K ₂ b ₂ (i-1) 2 b ₃ (i) = b ₂ (i - 1) + K ₂ Y ₂ (i) 2 (and) = Y ₂ (i) - K ₁ b ₁ (i-1) 1 b ₂ (i) = bj (i - 1) + K ₁ Y ₁ (i) 1 b _x (i) = Yj (I)

CS 266 303 B2

Table II

Interval Inputs multipliers 1 2 Multiplier outputs and one adder-subtractor input Second input of adder-subtractor Adder-Subtractor output Delay circuit output Output Pos. re gistru Memory output 11 K ₂ bj (i - 1) —К _IO * l), o (i-1) U (i) b ₂ (i) Ь _д (1 1) li.iO 11 Y | (< .... π T2 -TO, b | (i - υ -K ₉ · b ₉ (i - n Y | o (i> Υ, ο (ί) b ₂ (i-1) b, o (i-1) T3 К 10 Yio -K ₈ · b ₈ (i - 1) Y ₉ i Y ₉ (0 Yjo (i) T4 к ₉ Y ₉ (i> -K ₇ 'b ₇ (i-1) Y ₈ (i) Y ₈ (I) Y ₉ i T5 Kg in _e (i) -K ₆ · b ₆ (i-1) Y ₇ (i) Y ₇ (i) Ys (i) T6 κ ₇ γ ₇ ω -k ₅ · b ₅ (i - υ γ «ω γ _β ω Y ₇ (i) T7 Кб Υ ₆ (ί) -K ₄ · b ₄ (i-1) Y ₅ (i) Y ₅ (i) γ _β ω T8 Κ ₅ Y ₅ (i) -K ₃ · b ₃ (i-1) γ «ω Y ₄ (i) in _s (i) T9 κ ₄ γ ₄ (ί) -K ₂ · b ₂ (i-1) Y ₃ (i) Yj (i) Y ₉ w T10 Кз Y ₃ (i> -K, · b, (i-1) Y ₂ (·) Y ₂ () Y ₃ (I) Til κ ₂ Y _and (i) К io. * Yjo (·) b | o (i-11 Yi (i) Y ₂ (i) b ₁₀ (i - υ T12 Κι Y | ω K ₉ · Y ₉ (i) b »(i-1) b _lt (i) Yj (0 b ₉ (i - n T13 -Κ, ο bio (i) Ke · Y _e (i) b, (i-1) bio (i) White) b ₈ (i - υ T14 -κ ₉ b ₉ i K ₇ · Y ₇ (i) b, (i - 1) b ₉ i Ь10 (· 1 b ₇ (i - n T15 -κ ₈ b ₈ (i) K ₆ · Y ₆ (il b «(i - 2) be (i) b ₉ i b ₆ (i - n T16 -κ ₇ b ₇ (i) K ₅ · Y _s b ₅ (i-1) b ₇ (i) b _B (i) bs (i - υ T17 -κ _β b _A K ₄ · Y ₄ (i) b, (i-11 b ₆ (i) b ₇ (i) b ₄ (i - i) T18 -κ ₅ b ₅ (i> K ₃ · Y ₃ (s) b, (i-1) bs (i) bji) b ₃ (i - υ T19 -κ ₄ b ₄ (i) K ₂ · Y ₂ (i) b ₂ (i - 11 b ₄ (i) b $ (i) b ₂ (i - υ T20 -κ ₃ bj (i) K, · Y, (i) b, (i-1) b ₃ (i) b ₄ (i) Y | (and) Y | (and - υ TI ~ κ ₂ b, (i) —К 10 · bio (i) U (i + 2) b ₂ (i) b ₃ (i) bjj (i) on, (i)

Table III

Data from stack 31 (FIG. 5) at intervals

Output from the stack Intervals Bit Line TI T2 T3 T4 T5 T6 T7 T8 T9 T10 Til T12 T13 TI 4 T15 TI 6 T17 T18 T19 T20 LSB 32 - 1 ^K 2 ^K 1 ^K 10 ^K 9 what ^K 7 ^K 6 ^K 5 ^K 4 ^K 3 32-2 ^K 2 ^K í ^K 10 ^K 9 ^K 8 ^K 7 ^K 6 ^K 5 ^K 4 ^K 3 32-3 ^K 3 K ₂ ^K 1 ^K 10 Kg ^K 8 ^K 7 ^K 6 ^K 5 ^K 4 32-4 ^K 4 ^K 3 ^K 2 ^K 1 ^K 10 Kg ^K 8 ^K 7 ^K 6 ^K 5 32-5 ^K 5 ^K 4 ^K 3 ^K 2 ^K 1 ^K 10 ^K 9 ^K 8 · ^K 7 ^K 6 32-6 ^K 6 ^K 5 ^K 4 ^K 3 ^K 2 ^K 1 ^K 10 ^K 9 ^K 8 ^K 7 32-7 k ₇ ^K 6 ^K 5 ^K 4 ^K 3 ^K 2 ^K 1 ^K 10 ^K 9 ^K 8 32-8 ^K 8 ^K 7 ^K 6 ^K 5 ^K 4 ^K 3 k ₂ ^K 1 ^K 10 ^K 9 MSB 32-9 ^K 9 ^K 8 ^K 7 ^K 6 ^K 5 ^K 4 ^K 3 ^K 2 ^K 1 ^K 10 SIGN BIT 32 - 10 ^K 9 ^K 8 ^K 7 ^K 6 ^K 5 ^K 4 ^K 3 ^K 2 ^K 1 ^K 10

CS 266 303 B2

Table IV

Interval Inputs Multiplier outputs and one adder-subtractor «10 · '> _l0 (i 1) Second input of adder-subtractor U (i) Adder-Subtractor b ₂ (i 0 Delay circuit output b ₃ (i - П Output Pos. registry U (i> Memory output Υ. (i - 1) T 1 multipliers 1 »<2 2 l> ₂ (i AND) T2 -TO, bj (i - n —K ₉ · b ₉ (i-1) Y.o (i) Yio (i) b ₂ (i-1) b | ₀ (Í i - υ T3 AND V (i + 1) -Ke · b ₈ (i-1) Y ₉ i Y ₉ i Yio (i> T4 K ₉ Y ₉ (s) -K ₇ · b ₇ (i - 1) Y ₈ (i) Y ₈ (i) Y ₉ i T5 Ke Y ₈ (i) -K ₆ · b ₆ (i - П Y ₇ (il Y ₇ (i) Y ₈ (i) T6 K ₇ Y ₇ W -K ₅ · b $ (i-1) Y _e (i) Y ₆ (i) Y7GI T7 Ke Y ₆ (i) -K ₄ · b ₄ (i-1) Y $ (f) Ys (i) Y ₆ (i) T8 Pcs Ys (i) -K ₃ · b ₃ (i-1) Y ₄ (i> Y ₄ (i) Ys (i) T9 K ₄ Y «(i> -K ₂ · b ₂ (i-1) Y ₃ (il Y ₃ (i) Y ₄ (0 T1O K ₃ Y ₃ (I) -Kj · b, (i-1) Y ₂ (i) Y ₂ (i) γ ₃ ω Til K ₂ Y ₂ (0 U (i + 2) 0 Y1 (i) Y ₂ (s) bio (i - υ T12 К, Y1 (i) K ₉ · Y ₉ (i) b ₉ (i - 1) U (i + 2) Yi (i> b ₉ (i - υ T13 - to 10 bio (i) K ₈ · Y ₈ (i) b ₈ (i-1) b ₁₀ (<) U (i + 2) b ₈ (i - υ T14 -к ₉ b ₉ i K ₇ · Y ₇ (i) b ₇ (i - 1) b ₉ i bio (i) b ₇ (i - η T15 -κ _β b _e (i) K ₆ · YJi) b ₆ (i-1) b ₈ (i) b ₉ i b ₈ (i - η T16 -К- » b ₇ (i) Ks · Y _with bs (i - n b ₇ (i> b ₈ (i) b $ (i - η T17 -κ _β b ₆ (s) K ₄ · Y ₄ (i) b ₄ (i - n b ₆ (i) b ₇ <i) b ₄ (i - υ T18 -K ₅ b ₅ (i) K ₃ · Y ₃ (i) b ₃ (i - υ b $ (i) b ₆ (i) b ₃ (i - η T19 -K ₄ b ₄ (i) K ₂ · Y ₂ (i) b ₂ (i-1) b ₄ (i) b ₅ (i) b ₂ (i - η T20 -K ₃ b ₃ (i) Kj · YJi) ь, »(υ b ₃ (i) b ₄ (i) Y. (i> YJi- η TI -K ₂ b ₂ (i) - K | 0 * b | o (i) U (i + 2) b ₂ (i) b ₃ (i) U (i + 2) Y. (I)

CS 266 303 В2

Claims (8)

1. A digital filter with digital excitation signal inputs and digital values displaying filter coefficients, especially for speech synthesizers, which consists of a coefficient stack connected by a line with a multiplier, from one to the other, by a duck. vnlup is fi |> <)) <4> я t t t up výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup výstup a first switch (38) is connected to selectively connect the adder-subtractor output (33) and the memory circuit output (41) to the multiplier input (30). 2. A digital filter according to claim 1, wherein the memory circuit (41) comprises a first delay circuit (34) with a short delay time, a second delay circuit (35) with a longer delay time and a memory (36) connected via the first switch (38). ) with the input of the multiplier (30), the output of the first delay circuit (34) being connected to the input of the multiplier (30). A digital filter according to claim 1 or 2, characterized in that a second switch (37) is connected at the input of the adder-subtractor (33) to selectively connect the adder-subtractor output (33), the second delay circuit (35) and the memory. 36) to the adder-subtractor (33). 4. The digital filter of claim 3, wherein the first switch (38) comprises switches (3ΘΑ, 38В, 38C) for selectively adding the adder-subtractor output (33), the first delay circuit output (34), or the memory output (36). to the multiplier input (30), and the second switch (37) comprises switches (37В, 37C, 37D) for selectively connecting the adder-subtracter output (33), the second delay circuit output (35), or the memory output (36) to the adder input. readers (33). A digital filter according to claim 3 or 4, characterized in that a third switch (39) is connected between the second delay circuit (35) and the memory (36) to selectively connect the output of the second delay circuit (35) to the memory input (36). Digital filter according to one of Claims 3 to 5, characterized in that the excitation signal source (11) is connected to the adder-subtractor (33) input via a switch (37A) of the second switch (37). Digital filter according to one of Claims 1 to 5, characterized in that the excitation signal source (11) is connected by a bus (40) to the multiplier (30) input via a switch (38D) of the first switch (38). Digital filter according to one of Claims 2 to 7, characterized in that the output of the digital signal (12) is connected to a digital-to-analog converter (13) 2a by which the loudspeaker (14) is connected.