JPS6320048B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter used in a speech synthesis circuit using the principle of linear predictive coding. More specifically, one method of configuring a lattice-type linear prediction type speech synthesis digital filter will be described.

Markel and Gray for lattice filters
Co-authored “Linear Prediction of Speech” (New
Springer-Verlag, York, 1976), Chapter 5.

A historical analysis of the method for implementing the above-mentioned lattice filter is described in detail in Japanese Patent Application Laid-Open No. 7838/1983, which describes the method of implementing the lattice filter using one multiplication circuit and one addition/subtraction circuit. We are proposing a method for this purpose.

The present invention has a configuration similar to the above method, and attempts to further propose a method for realizing a lattice filter using one multiplier circuit and one addition/subtraction circuit, as well as a method for realizing a lattice filter using one multiplication circuit and one addition/subtraction circuit. This is what we are trying to achieve.

The model of a lattice filter with an attenuation term and its implementation using a stored program method were presented by Yamada and four others from the Musashino Telecommunications Research Institute of Nippon Telegraph and Telephone Public Corporation in the proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers. “One chip”
PARCOR Synthesizer”.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A lattice filter of a speech synthesizer, which is the basis of the present invention, will be explained below based on the drawings. Regarding the basic configuration of the speech synthesizer used in the present invention,
“Linear Predictive Coding (LPC) Vocoder Speech Synthesizer with 3 Chips” (Nikkei Electronics)
1979-1-8, pages 147-162, R. Wiggins and L. Brandingham).

Figure 1 shows a model of a lattice filter used in a speech synthesizer. In FIG. 1, AU(i) is an input signal consisting of the product of the amplitude signal A and the excitation signal U(i) in the i-th time cycle. y ₁ is the composite output signal and is applied to the DA converter. Figure 1 is 10
An example is shown for the case of stages, 1 to 10 are subtractors, 11 to
19 is an adder, 21 to 30 and 22' to 30' are multipliers for multiplying by filter coefficients ki (i=1, 2, to 10), and 41 to 50 are one-hour cycle delay units. y ₁₀ to y ₁ are output signals of subtracters 1 to 10, respectively, and b ₁₀ to b ₂ are output signals of adders 11 to 19, respectively.
is the output signal of , and b ₁ is equal to y ₁ . For example, the signal y ₈ is the signal b ₈ one hour cycle before the signal y ₉ .
It is calculated by multiplying by a coefficient _k8 and subtracting the result. Further, the signal b ₈ is calculated by adding the result of multiplying the signal y ₇ by the coefficient k ₇ to the signal b ₇ one hour cycle ago.

Table 1 (attached) shows each signal in Figure 1.
The relationship between y ₁₀ to y ₁ and b ₁₀ to b ₁ is expressed in the form of an equation.

FIG. 2 shows a block diagram of a lattice filter that actually operates the model shown in FIG. In FIG. 2, 101 is a K stack as a memory means, which stores digital values k ₁ to _{k 10} representing filter coefficients.
and amplitude signal A are stored. 102 is a multiplication circuit, and the output from the K stack 101 is inputted in parallel to one input a of the multiplication circuit. As the multiplication circuit 102, an array type parallel arithmetic circuit is usually used. When Booth's algorithm is used, complement operations are performed without considering the sign. For example, using Booth's quadratic algorithm, the K stack is 10.
If the number of parallel bits starting from 1 is 10, the process ends with repeating four stages of parallel addition. Booth's quadratic algorithm is detailed in ``Looking at multiplier circuit systems based on parallel calculation methods that are becoming increasingly popular in LSI'' (Nikkei Electronics 1978-5-29, pages 76-90).

103 is a three-stage shift register as a first delay circuit means, and 104 is a one-stage intermittent operation shift register as a first intermittent operation delay circuit means. Reference numeral 105 denotes a changeover switch which receives the output of the shift register 103 and the output of the intermittent operation shift register 104, and switches between them to output either of them.
06 is an addition/subtraction circuit which takes the output of the changeover switch 105 as one input c, 107 is a changeover switch, 108 is a one-stage shift register as second delay circuit means, and 109 is 9 as second intermittent operation delay circuit means. A stage intermittent operation shift register is connected to the shift register 108. Reference numeral 110 denotes a latch circuit, which holds and outputs the digital value created by the calculations up to the previous stage, and sends it to a DA converter (not shown). Reference numeral 111 denotes a changeover switch, which inputs the output of the addition/subtraction circuit 106 and the output of the intermittent operation shift register 109, and outputs either one by switching.
becomes the other input d. Also, the changeover switch 107
outputs the output of the adding/subtracting circuit 106, the output of the intermittent operation shift register 109, and the excitation signal U(i), and inputs the output to the shift register 108. The other input b of the multiplier circuit 102 is connected to the shift register 10.
This is part of the output of 8.

In FIG. 2, since there is room to multiply the amplitude signal A and the excitation signal U(i), the input method for this purpose is to shift the amplitude signal A from the K stack 101 and the excitation signal U(i) through the changeover switch 107. It is assumed that the data is input to the register 108.

FIG. 3 shows in detail a timing diagram when the arithmetic expressions in Table 1 are executed by the circuit in FIG. 2. In FIG. 3, information on the coefficient ki or amplitude A is input to the input a of the multiplication circuit 102, and the output of the one-stage shift register 108 is input to the input b. The multiplication result passes through a four-stage multiplication circuit 102 and a three-stage shift register 103, and appears at the output of the three-stage shift register 103 after seven periods.

The one-stage intermittent operation shift register 104 has a period of
Shift operation is performed from T ₁ to T ₁₁ , and period T ₁₂ to _{T 20}
Until then, the shift operation is stopped. Addition/subtraction circuit 1
The output of the one-stage intermittent operation shift register 104 is input to the input c of 06 during the periods T ₂₀ and T ₁ to T ₁₀ , and the output of the three-stage shift register 103 is input to the period T ₁₁ to T ₁₉ . Ru. Also, the addition/subtraction circuit 10
Addition/subtraction circuit 1 is connected to the input d of 6 for the period T ₁ to T ₁₀ .
The output of 06 is input, and the output is 9 for the period T ₁₁ to _{T 19} .
The output of the intermittent operation shift register 109 of the stage is input, and 0 is input during period _T20 . The addition/subtraction circuit 106 performs a subtraction operation of subtracting the input c from the input d during the period _T1 to _T10 , and performs an addition operation of adding the input c to the input d during the period _T11 to _T20 .

The input of the first stage shift register 108 has a period
During T ₁ , the output of the 9-stage intermittent operation shift register 109 is input, and during period T ₂ , the excitation signal U(i+
1) is input, and the output of the addition/subtraction circuit 106 is input during the period T ₃ to _{T 20} . The 9-stage intermittent operation shift register 109 operates from period _T11 to _T2 ,
The operation is stopped during the period _T3 to _T10 . The contents of the latch circuit 110 hold data during periods T ₂ -T ₂₀ -T ₁ and are updated when transitioning from period T ₁ to T ₂ .

With the above circuit configuration, the operations shown in Table 1 can be performed using simple circuit elements, and the connections between the circuit elements are also simple.

An embodiment of the present invention will be described below based on the drawings. This is the model of FIG. 1 in which attenuation calculation is introduced. As a countermeasure for suppressing abnormal amplitude of synthesized sound, a small loss is inserted into the synthesis filter. Regarding its effect, see “Deformed lattice shape”.
"Study of PARCOR Analysis and Synthesis Method" (Acoustical Society of Japan, Speech Research Group Materials, Material No. S77-06, May 1977)
I am familiar with

FIG. 4a shows a model of a lattice filter incorporating attenuation calculation. 51 to 60 are attenuators;
b′ ₁₀ to b′ ₁ are the inputs of attenuators 51 to 60, and b ₁₀
~b ₁ corresponds to its output. The rest is the same as in Figure 1. For example, when moving from b′ ₃ to b ₃ , the value decreases to 255/256. FIG. 4b shows a specific circuit example of the attenuators 51-60.

Table 2 (attached) shows each signal in Figure 4.
The relationship among y ₁₀ to y ₁ , b ₁₀ to b ₁ , and b' ₁₀ to b' ₁ is expressed in the form of an equation.

FIG. 5 shows a block diagram of the lattice filter of FIG. 4, which is an embodiment of the present invention. The difference from FIG. 2 is that the one-stage shift register 108 in FIG. The output of the changeover switch 107 is multiplied by (1-1/256) and output. In FIG. 5, the output of the shift circuit 112 is set to 0.
In this case, the shift circuit 112 and the subtraction circuit 113 simply constitute a one-stage shift register, so that attenuation calculation can be easily employed or excluded.

FIG. 6 shows a timing diagram when the operations shown in Table 2 are executed with the configuration shown in FIG. Here, subtraction circuit 1
This is the same as FIG. 3 except that the attenuation calculation is performed at the input and output of 13. It should be noted that the structure shown in FIG. 6 may be such that the latch circuit is connected to the subtraction circuit output and b ₁ (i-1) is input to the latch circuit during the period T ₂ .

As described above, according to the present invention, the output of the shift circuit is made zero by providing the second delay circuit means composed of a shift circuit and a subtraction circuit in order to incorporate attenuation calculation into the lattice filter of the speech synthesizer. You can freely choose whether or not to insert a damping term depending on whether or not to insert a damping term. By inserting a damping term, you can prevent abnormal amplitudes caused by oscillation phenomena, and if unnecessary, It can be removed to prevent deterioration of sound quality.

[Brief explanation of the drawing]

Figure 1 is a model diagram of a synthetic digital filter.
Fig. 2 is a block diagram of the synthetic digital filter shown in Fig. 1, Fig. 3 is a timing diagram explaining its operation, Fig. 4 is a model diagram of the synthetic digital filter incorporating the attenuation term of the present invention, and Fig. 5 is a block diagram of the synthetic digital filter of Fig. 1. FIG. 6 is a block diagram showing one embodiment of the digital filter, and a timing diagram illustrating its operation. 101...K stack, 102...Multiplication circuit,
103...3-stage shift register, 104...1
stage intermittent operation shift register, 105, 107,
111...Switchover switch, 106...Addition/subtraction circuit, 108...1-stage shift register, 109...
...9-stage shift register, 110... latch circuit, 112... shift circuit, 113... subtraction circuit.

Claims (1)

Claims: 1. A digital filter responsive to a digital excitation signal and a plurality of digital values representing filter coefficients, comprising memory means for storing a plurality of digital values representing filter coefficients; a multiplier circuit connected to the output of the memory means; a first delay circuit means connected to the output of the multiplier circuit; a first intermittent operation delay circuit means connected to the output of the first delay circuit means; a first switch means for selectively switching and outputting the first delay circuit means output and the first intermittent operation delay circuit means output;
an adder/subtracter circuit having a first input connected to the output of the first switch means; and a second delay circuit means having a portion of the output connected to a second input of the multiplier circuit;
a second intermittent operation delay circuit means connected to the output of the second delay circuit means; a third switch means for selectively switching between the output of the adder/subtractor circuit and the output of the second intermittent operation delay circuit means and outputting the output to the second delay circuit means;
and a latch means for temporarily storing data output from the second intermittent operation delay circuit means, the second delay circuit means having one input connected to the third switch. A digital filter comprising a subtractor circuit to which the output of the switch means is directly connected and the output of the third switch means is connected to the other input through a shift circuit. 2. The digital filter according to claim 1, wherein the third switch means further selectively outputs the excitation signal to the second delay circuit means.